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-------------------------------------------------------------------------------
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--
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-- (c) Copyright 2009-2011 Xilinx, Inc. All rights reserved.
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--
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-- This file contains confidential and proprietary information
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-- of Xilinx, Inc. and is protected under U.S. and
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-- international copyright and other intellectual property
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-- laws.
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--
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-- DISCLAIMER
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-- This disclaimer is not a license and does not grant any
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-- rights to the materials distributed herewith. Except as
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-- otherwise provided in a valid license issued to you by
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-- Xilinx, and to the maximum extent permitted by applicable
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-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
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-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
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-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
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-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
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-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
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-- (2) Xilinx shall not be liable (whether in contract or tort,
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-- including negligence, or under any other theory of
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-- liability) for any loss or damage of any kind or nature
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-- related to, arising under or in connection with these
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-- materials, including for any direct, or any indirect,
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-- special, incidental, or consequential loss or damage
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-- by a third party) even if such damage or loss was
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-- reasonably foreseeable or Xilinx had been advised of the
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-- possibility of the same.
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--
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-- CRITICAL APPLICATIONS
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-- Xilinx products are not designed or intended to be fail-
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-- safe, or for use in any application requiring fail-safe
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-- performance, such as life-support or safety devices or
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-- systems, Class III medical devices, nuclear facilities,
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-- applications related to the deployment of airbags, or any
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-- other applications that could lead to death, personal
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-- injury, or severe property or environmental damage
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-- (individually and collectively, "Critical
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-- Applications"). Customer assumes the sole risk and
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-- liability of any use of Xilinx products in Critical
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-- Applications, subject only to applicable laws and
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-- regulations governing limitations on product liability.
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--
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-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
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-- PART OF THIS FILE AT ALL TIMES.
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--
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-------------------------------------------------------------------------------
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-- Project : Virtex-6 Integrated Block for PCI Express
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-- File : PIO_EP.vhd
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-- Version : 1.7
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----
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---- Description: Endpoint Programmed I/O module.
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----
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----------------------------------------------------------------------------------
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_arith.all;
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use ieee.numeric_std.all;
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entity PIO_EP is
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port (
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clk : in std_logic;
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rst_n : in std_logic;
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-- LocalLink Tx
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trn_td : out std_logic_vector(63 downto 0);
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trn_trem_n : out std_logic_vector(7 downto 0);
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trn_tsof_n : out std_logic;
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trn_teof_n : out std_logic;
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trn_tsrc_dsc_n : out std_logic;
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trn_tsrc_rdy_n : out std_logic;
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trn_tdst_dsc_n : in std_logic;
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trn_tdst_rdy_n : in std_logic;
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-- LocalLink Rx
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trn_rd : in std_logic_vector(63 downto 0);
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trn_rrem_n : in std_logic_vector(7 downto 0);
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trn_rsof_n : in std_logic;
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trn_reof_n : in std_logic;
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trn_rsrc_rdy_n : in std_logic;
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trn_rsrc_dsc_n : in std_logic;
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trn_rbar_hit_n : in std_logic_vector(6 downto 0);
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trn_rdst_rdy_n : out std_logic;
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req_compl_o : out std_logic;
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compl_done_o : out std_logic;
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cfg_completer_id : in std_logic_vector(15 downto 0);
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cfg_bus_mstr_enable : in std_logic
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);
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end PIO_EP;
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architecture rtl of PIO_EP is
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-- Local signals
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signal rd_addr : std_logic_vector(10 downto 0);
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signal rd_be : std_logic_vector(3 downto 0);
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signal rd_data : std_logic_vector(31 downto 0);
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signal wr_addr : std_logic_vector(10 downto 0);
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signal wr_be : std_logic_vector(7 downto 0);
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signal wr_data : std_logic_vector(31 downto 0);
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signal wr_en : std_logic;
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signal wr_busy : std_logic;
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signal req_compl : std_logic;
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signal compl_done : std_logic;
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signal req_tc : std_logic_vector(2 downto 0);
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signal req_td : std_logic;
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signal req_ep : std_logic;
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signal req_attr : std_logic_vector(1 downto 0);
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signal req_len : std_logic_vector(9 downto 0);
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signal req_rid : std_logic_vector(15 downto 0);
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signal req_tag : std_logic_vector(7 downto 0);
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signal req_be : std_logic_vector(7 downto 0);
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signal req_addr : std_logic_vector(12 downto 0);
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component PIO_RX_ENGINE is
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port (
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clk : in std_logic;
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rst_n : in std_logic;
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trn_rd : in std_logic_vector(63 downto 0);
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trn_rrem_n : in std_logic_vector(7 downto 0);
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trn_rsof_n : in std_logic;
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trn_reof_n : in std_logic;
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trn_rsrc_rdy_n : in std_logic;
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trn_rsrc_dsc_n : in std_logic;
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trn_rbar_hit_n : in std_logic_vector(6 downto 0);
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trn_rdst_rdy_n : out std_logic;
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req_compl_o : out std_logic;
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compl_done_i : in std_logic;
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req_tc_o : out std_logic_vector(2 downto 0); -- Memory Read TC
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req_td_o : out std_logic; -- Memory Read TD
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req_ep_o : out std_logic; -- Memory Read EP
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req_attr_o : out std_logic_vector(1 downto 0); -- Memory Read Attribute
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req_len_o : out std_logic_vector(9 downto 0); -- Memory Read Length (1DW)
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req_rid_o : out std_logic_vector(15 downto 0); -- Memory Read Requestor ID
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req_tag_o : out std_logic_vector(7 downto 0); -- Memory Read Tag
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req_be_o : out std_logic_vector(7 downto 0); -- Memory Read Byte Enables
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req_addr_o : out std_logic_vector(12 downto 0); -- Memory Read Address
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wr_addr_o : out std_logic_vector(10 downto 0); -- Memory Write Address
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wr_be_o : out std_logic_vector(7 downto 0); -- Memory Write Byte Enable
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wr_data_o : out std_logic_vector(31 downto 0); -- Memory Write Data
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wr_en_o : out std_logic; -- Memory Write Enable
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wr_busy_i : in std_logic -- Memory Write Busy
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);
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end component;
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component PIO_TX_ENGINE is
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port (
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clk : in std_logic;
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rst_n : in std_logic;
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trn_td : out std_logic_vector( 63 downto 0);
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trn_trem_n : out std_logic_vector(7 downto 0);
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trn_tsof_n : out std_logic;
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trn_teof_n : out std_logic;
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trn_tsrc_rdy_n : out std_logic;
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trn_tsrc_dsc_n : out std_logic;
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trn_tdst_rdy_n : in std_logic;
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trn_tdst_dsc_n : in std_logic;
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req_compl_i : in std_logic;
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compl_done_o : out std_logic;
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req_tc_i : in std_logic_vector(2 downto 0);
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req_td_i : in std_logic;
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req_ep_i : in std_logic;
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req_attr_i : in std_logic_vector(1 downto 0);
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req_len_i : in std_logic_vector(9 downto 0);
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req_rid_i : in std_logic_vector(15 downto 0);
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req_tag_i : in std_logic_vector(7 downto 0);
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req_be_i : in std_logic_vector(7 downto 0);
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req_addr_i : in std_logic_vector(12 downto 0);
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rd_addr_o : out std_logic_vector(10 downto 0);
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rd_be_o : out std_logic_vector( 3 downto 0);
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rd_data_i : in std_logic_vector(31 downto 0);
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completer_id_i : in std_logic_vector(15 downto 0);
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cfg_bus_mstr_enable_i : in std_logic
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);
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end component;
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component PIO_EP_MEM_ACCESS is
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port (
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clk : in std_logic;
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rst_n : in std_logic;
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-- Read Port
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rd_addr_i : in std_logic_vector(10 downto 0);
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rd_be_i : in std_logic_vector(3 downto 0);
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rd_data_o : out std_logic_vector(31 downto 0);
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-- Write Port
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wr_addr_i : in std_logic_vector(10 downto 0);
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wr_be_i : in std_logic_vector(7 downto 0);
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wr_data_i : in std_logic_vector(31 downto 0);
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wr_en_i : in std_logic;
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wr_busy_o : out std_logic
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);
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end component;
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begin
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-- ENDPOINT MEMORY : 8KB memory aperture implemented in FPGA BlockRAM(*)
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EP_MEM : PIO_EP_MEM_ACCESS port map (
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clk => clk, -- I
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rst_n => rst_n, -- I
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-- Read Port
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rd_addr_i => rd_addr, -- I [10:0]
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rd_be_i => rd_be, -- I [3:0]
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rd_data_o => rd_data, -- O [31:0]
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-- Write Port
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wr_addr_i => wr_addr, -- I [10:0]
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wr_be_i => wr_be, -- I [7:0]
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wr_data_i => wr_data, -- I [31:0]
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wr_en_i => wr_en, -- I
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wr_busy_o => wr_busy -- O
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);
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EP_RX : PIO_RX_ENGINE port map (
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clk => clk, -- I
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rst_n => rst_n, -- I
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-- LocalLink Rx
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trn_rd => trn_rd, -- I [63:0]
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trn_rrem_n => trn_rrem_n, -- I [7:0]
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trn_rsof_n => trn_rsof_n, -- I
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trn_reof_n => trn_reof_n, -- I
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trn_rsrc_rdy_n => trn_rsrc_rdy_n, -- I
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trn_rsrc_dsc_n => trn_rsrc_dsc_n, -- I
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trn_rbar_hit_n => trn_rbar_hit_n, -- I [6:0]
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trn_rdst_rdy_n => trn_rdst_rdy_n, -- O
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-- Handshake with Tx engine
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req_compl_o => req_compl, -- O
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compl_done_i => compl_done, -- I
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req_tc_o => req_tc, -- O [2:0]
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req_td_o => req_td, -- O
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req_ep_o => req_ep, -- O
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req_attr_o => req_attr, -- O [1:0]
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req_len_o => req_len, -- O [9:0]
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req_rid_o => req_rid, -- O [15:0]
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req_tag_o => req_tag, -- O [7:0]
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req_be_o => req_be, -- O [7:0]
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req_addr_o => req_addr, -- O [12:0]
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-- Memory Write Port
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wr_addr_o => wr_addr, -- O [10:0]
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wr_be_o => wr_be, -- O [7:0]
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wr_data_o => wr_data, -- O [31:0]
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wr_en_o => wr_en, -- O
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wr_busy_i => wr_busy -- I
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);
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-- Local-Link Transmit Controller
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EP_TX : PIO_TX_ENGINE port map (
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clk => clk, -- I
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rst_n => rst_n, -- I
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-- LocalLink Tx
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trn_td => trn_td, -- O [63:0]
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trn_trem_n => trn_trem_n , -- O [7:0]
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trn_tsof_n => trn_tsof_n, -- O
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trn_teof_n => trn_teof_n, -- O
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trn_tsrc_dsc_n => trn_tsrc_dsc_n, -- O
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trn_tsrc_rdy_n => trn_tsrc_rdy_n, -- O
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trn_tdst_dsc_n => trn_tdst_dsc_n, -- I
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trn_tdst_rdy_n => trn_tdst_rdy_n, -- I
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-- Handshake with Rx engine
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req_compl_i => req_compl, -- I
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compl_done_o => compl_done, -- 0
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req_tc_i => req_tc, -- I [2:0]
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req_td_i => req_td, -- I
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req_ep_i => req_ep, -- I
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req_attr_i => req_attr, -- I [1:0]
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req_len_i => req_len, -- I [9:0]
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req_rid_i => req_rid, -- I [15:0]
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req_tag_i => req_tag, -- I [7:0]
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req_be_i => req_be, -- I [7:0]
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req_addr_i => req_addr, -- I [12:0]
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-- Read Port
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rd_addr_o => rd_addr, -- O [10:0]
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rd_be_o => rd_be, -- O [3:0]
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rd_data_i => rd_data, -- I [31:0]
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332 |
|
|
|
333 |
|
|
completer_id_i => cfg_completer_id, -- I [15:0]
|
334 |
|
|
cfg_bus_mstr_enable_i => cfg_bus_mstr_enable -- I
|
335 |
|
|
|
336 |
|
|
);
|
337 |
|
|
|
338 |
|
|
req_compl_o <= req_compl;
|
339 |
|
|
compl_done_o <= compl_done;
|
340 |
|
|
|
341 |
|
|
end rtl; -- PIO_EP
|
342 |
|
|
|