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//-----------------------------------------------------------------------------
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//
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// (c) Copyright 2009-2011 Xilinx, Inc. All rights reserved.
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//
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// This file contains confidential and proprietary information
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// of Xilinx, Inc. and is protected under U.S. and
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// international copyright and other intellectual property
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// laws.
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//
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// DISCLAIMER
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// This disclaimer is not a license and does not grant any
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// rights to the materials distributed herewith. Except as
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// otherwise provided in a valid license issued to you by
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// Xilinx, and to the maximum extent permitted by applicable
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// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
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// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
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// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
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// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
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// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
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// (2) Xilinx shall not be liable (whether in contract or tort,
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// including negligence, or under any other theory of
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// liability) for any loss or damage of any kind or nature
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// related to, arising under or in connection with these
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// materials, including for any direct, or any indirect,
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// special, incidental, or consequential loss or damage
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// (including loss of data, profits, goodwill, or any type of
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// loss or damage suffered as a result of any action brought
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// by a third party) even if such damage or loss was
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// reasonably foreseeable or Xilinx had been advised of the
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// possibility of the same.
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//
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// CRITICAL APPLICATIONS
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// Xilinx products are not designed or intended to be fail-
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// safe, or for use in any application requiring fail-safe
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// performance, such as life-support or safety devices or
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// systems, Class III medical devices, nuclear facilities,
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// applications related to the deployment of airbags, or any
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// other applications that could lead to death, personal
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// injury, or severe property or environmental damage
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// (individually and collectively, "Critical
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// Applications"). Customer assumes the sole risk and
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// liability of any use of Xilinx products in Critical
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// Applications, subject only to applicable laws and
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// regulations governing limitations on product liability.
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//
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// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
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// PART OF THIS FILE AT ALL TIMES.
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//
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//-----------------------------------------------------------------------------
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// Project : Virtex-6 Integrated Block for PCI Express
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// File : PIO_EP_MEM_ACCESS.v
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// Version : 1.7
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//--
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//-- Description: Endpoint Memory Access Unit. This module provides access functions
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//-- to the Endpoint memory aperture.
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//--
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//-- Read Access: Module returns data for the specifed address and
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//-- byte enables selected.
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//--
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//-- Write Access: Module accepts data, byte enables and updates
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//-- data when write enable is asserted. Modules signals write busy
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//-- when data write is in progress.
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//--
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//--------------------------------------------------------------------------------
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`timescale 1ns/1ns
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`define TCQ 1
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`define PIO_MEM_ACCESS_WR_RST 3'b000
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`define PIO_MEM_ACCESS_WR_WAIT 3'b001
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`define PIO_MEM_ACCESS_WR_READ 3'b010
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`define PIO_MEM_ACCESS_WR_WRITE 3'b100
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module PIO_EP_MEM_ACCESS (
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clk,
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rst_n,
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// Read Access
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rd_addr_i, // I [10:0]
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rd_be_i, // I [3:0]
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rd_data_o, // O [31:0]
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// Write Access
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wr_addr_i, // I [10:0]
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wr_be_i, // I [7:0]
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wr_data_i, // I [31:0]
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wr_en_i, // I
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wr_busy_o // O
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);
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input clk;
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input rst_n;
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// * Read Port
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input [10:0] rd_addr_i;
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input [3:0] rd_be_i;
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output [31:0] rd_data_o;
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// * Write Port
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input [10:0] wr_addr_i;
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input [7:0] wr_be_i;
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input [31:0] wr_data_i;
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input wr_en_i;
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output wr_busy_o;
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wire [31:0] rd_data_o;
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reg [31:0] rd_data_raw_o;
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wire [31:0] rd_data0_o, rd_data1_o, rd_data2_o, rd_data3_o;
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wire wr_busy_o;
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reg write_en;
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reg [31:0] post_wr_data;
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reg [31:0] w_pre_wr_data;
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reg [2:0] wr_mem_state;
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reg [31:0] pre_wr_data;
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wire [31:0] w_pre_wr_data0;
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wire [31:0] w_pre_wr_data1;
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wire [31:0] w_pre_wr_data2;
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wire [31:0] w_pre_wr_data3;
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reg [31:0] pre_wr_data0_q, pre_wr_data1_q, pre_wr_data2_q, pre_wr_data3_q;
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reg [31:0] DW0, DW1, DW2;
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// ** Memory Write Process
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// * Extract current data bytes. These need to be swizzled
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// * BRAM storage format :
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// * data[31:0] = { byte[3], byte[2], byte[1], byte[0] (lowest addr) }
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wire [7:0] w_pre_wr_data_b3 = pre_wr_data[31:24];
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wire [7:0] w_pre_wr_data_b2 = pre_wr_data[23:16];
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wire [7:0] w_pre_wr_data_b1 = pre_wr_data[15:08];
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wire [7:0] w_pre_wr_data_b0 = pre_wr_data[07:00];
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// * Extract new data bytes from payload
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// * TLP Payload format :
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// * data[31:0] = { byte[0] (lowest addr), byte[2], byte[1], byte[3] }
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wire [7:0] w_wr_data_b3 = wr_data_i[07:00];
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wire [7:0] w_wr_data_b2 = wr_data_i[15:08];
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wire [7:0] w_wr_data_b1 = wr_data_i[23:16];
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wire [7:0] w_wr_data_b0 = wr_data_i[31:24];
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always @(posedge clk or negedge rst_n) begin
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if ( !rst_n ) begin
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pre_wr_data <= 32'b0;
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post_wr_data <= 32'b0;
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pre_wr_data <= 32'b0;
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write_en <= 1'b0;
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pre_wr_data0_q <= 32'b0;
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pre_wr_data1_q <= 32'b0;
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pre_wr_data2_q <= 32'b0;
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pre_wr_data3_q <= 32'b0;
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wr_mem_state <= `PIO_MEM_ACCESS_WR_RST;
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end else begin
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case ( wr_mem_state )
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`PIO_MEM_ACCESS_WR_RST : begin
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if (wr_en_i) begin // read state
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wr_mem_state <= `PIO_MEM_ACCESS_WR_WAIT; //Pipelining happens in RAM's internal output reg.
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end else begin
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write_en <= 1'b0;
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wr_mem_state <= `PIO_MEM_ACCESS_WR_RST;
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end
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end
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`PIO_MEM_ACCESS_WR_WAIT : begin
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// * Pipeline B port data before processing. Virtex 5 Block RAMs have internal
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// output register enabled.
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//pre_wr_data0_q <= w_pre_wr_data0;
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// pre_wr_data1_q <= w_pre_wr_data1;
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// pre_wr_data2_q <= w_pre_wr_data2;
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// pre_wr_data3_q <= w_pre_wr_data3;
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write_en <= 1'b0;
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wr_mem_state <= `PIO_MEM_ACCESS_WR_READ ;
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end
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`PIO_MEM_ACCESS_WR_READ : begin
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// * Now save the selected BRAM B port data out
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pre_wr_data <= w_pre_wr_data;
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write_en <= 1'b0;
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wr_mem_state <= `PIO_MEM_ACCESS_WR_WRITE;
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end
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`PIO_MEM_ACCESS_WR_WRITE : begin
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// * Merge new enabled data and write target BlockRAM location
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post_wr_data <= {{wr_be_i[3] ? w_wr_data_b3 : w_pre_wr_data_b3},
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{wr_be_i[2] ? w_wr_data_b2 : w_pre_wr_data_b2},
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{wr_be_i[1] ? w_wr_data_b1 : w_pre_wr_data_b1},
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{wr_be_i[0] ? w_wr_data_b0 : w_pre_wr_data_b0}};
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write_en <= 1'b1;
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wr_mem_state <= `PIO_MEM_ACCESS_WR_RST;
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end
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endcase
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end
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end
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// * Write controller busy
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assign wr_busy_o = wr_en_i | (wr_mem_state != `PIO_MEM_ACCESS_WR_RST);
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// * Select BlockRAM output based on higher 2 address bits
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always @* // (wr_addr_i or pre_wr_data0_q or pre_wr_data1_q or pre_wr_data2_q or pre_wr_data3_q) begin
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begin
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case ({wr_addr_i[10:9]}) // synthesis parallel_case full_case
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2'b00 : w_pre_wr_data = w_pre_wr_data0;
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2'b01 : w_pre_wr_data = w_pre_wr_data1;
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2'b10 : w_pre_wr_data = w_pre_wr_data2;
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2'b11 : w_pre_wr_data = w_pre_wr_data3;
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endcase
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end
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// * Memory Read Controller
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wire rd_data0_en = {rd_addr_i[10:9] == 2'b00};
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wire rd_data1_en = {rd_addr_i[10:9] == 2'b01};
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wire rd_data2_en = {rd_addr_i[10:9] == 2'b10};
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wire rd_data3_en = {rd_addr_i[10:9] == 2'b11};
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always @(rd_addr_i or rd_data0_o or rd_data1_o or rd_data2_o or rd_data3_o)
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begin
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case ({rd_addr_i[10:9]}) // synthesis parallel_case full_case
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2'b00 : rd_data_raw_o = rd_data0_o;
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2'b01 : rd_data_raw_o = rd_data1_o;
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2'b10 : rd_data_raw_o = rd_data2_o;
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2'b11 : rd_data_raw_o = rd_data3_o;
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endcase
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end
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// Handle Read byte enables
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assign rd_data_o = {{rd_be_i[0] ? rd_data_raw_o[07:00] : 8'h0},
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{rd_be_i[1] ? rd_data_raw_o[15:08] : 8'h0},
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{rd_be_i[2] ? rd_data_raw_o[23:16] : 8'h0},
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{rd_be_i[3] ? rd_data_raw_o[31:24] : 8'h0}};
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EP_MEM EP_MEM (
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.clk_i(clk),
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.a_rd_a_i_0(rd_addr_i[8:0]), // I [8:0]
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.a_rd_en_i_0(rd_data0_en), // I [1:0]
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.a_rd_d_o_0(rd_data0_o), // O [31:0]
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.b_wr_a_i_0(wr_addr_i[8:0]), // I [8:0]
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.b_wr_d_i_0(post_wr_data), // I [31:0]
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.b_wr_en_i_0({write_en & (wr_addr_i[10:9] == 2'b00)}), // I
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.b_rd_d_o_0(w_pre_wr_data0[31:0]), // O [31:0]
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.b_rd_en_i_0({wr_addr_i[10:9] == 2'b00}), // I
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.a_rd_a_i_1(rd_addr_i[8:0]), // I [8:0]
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.a_rd_en_i_1(rd_data1_en), // I [1:0]
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.a_rd_d_o_1(rd_data1_o), // O [31:0]
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.b_wr_a_i_1(wr_addr_i[8:0]), // [8:0]
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.b_wr_d_i_1(post_wr_data), // [31:0]
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.b_wr_en_i_1({write_en & (wr_addr_i[10:9] == 2'b01)}), // I
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.b_rd_d_o_1(w_pre_wr_data1[31:0]), // [31:0]
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.b_rd_en_i_1({wr_addr_i[10:9] == 2'b01}), // I
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.a_rd_a_i_2(rd_addr_i[8:0]), // I [8:0]
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.a_rd_en_i_2(rd_data2_en), // I [1:0]
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.a_rd_d_o_2(rd_data2_o), // O [31:0]
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.b_wr_a_i_2(wr_addr_i[8:0]), // I [8:0]
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.b_wr_d_i_2(post_wr_data), // I [31:0]
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.b_wr_en_i_2({write_en & (wr_addr_i[10:9] == 2'b10)}), // I
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.b_rd_d_o_2(w_pre_wr_data2[31:0]), // I [31:0]
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.b_rd_en_i_2({wr_addr_i[10:9] == 2'b10}), // I
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.a_rd_a_i_3(rd_addr_i[8:0]), // [8:0]
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.a_rd_en_i_3(rd_data3_en), // [1:0]
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.a_rd_d_o_3(rd_data3_o), // O [31:0]
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.b_wr_a_i_3(wr_addr_i[8:0]), // I [8:0]
|
329 |
|
|
.b_wr_d_i_3(post_wr_data), // I [31:0]
|
330 |
|
|
.b_wr_en_i_3({write_en & (wr_addr_i[10:9] == 2'b11)}), // I
|
331 |
|
|
.b_rd_d_o_3(w_pre_wr_data3[31:0]), // I [31:0]
|
332 |
|
|
.b_rd_en_i_3({wr_addr_i[10:9] == 2'b11}) // I
|
333 |
|
|
|
334 |
|
|
);
|
335 |
|
|
|
336 |
|
|
// synthesis translate_off
|
337 |
|
|
reg [8*20:1] state_ascii;
|
338 |
|
|
always @(wr_mem_state)
|
339 |
|
|
begin
|
340 |
|
|
if (wr_mem_state==`PIO_MEM_ACCESS_WR_RST) state_ascii <= #`TCQ "PIO_MEM_WR_RST";
|
341 |
|
|
else if (wr_mem_state==`PIO_MEM_ACCESS_WR_WAIT) state_ascii <= #`TCQ "PIO_MEM_WR_WAIT";
|
342 |
|
|
else if (wr_mem_state==`PIO_MEM_ACCESS_WR_READ) state_ascii <= #`TCQ "PIO_MEM_WR_READ";
|
343 |
|
|
else if (wr_mem_state==`PIO_MEM_ACCESS_WR_WRITE) state_ascii <= #`TCQ "PIO_MEM_WR_WRITE";
|
344 |
|
|
else state_ascii <= #`TCQ "PIO MEM STATE ERR";
|
345 |
|
|
|
346 |
|
|
end
|
347 |
|
|
// synthesis translate_on
|
348 |
|
|
|
349 |
|
|
endmodule
|
350 |
|
|
|