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-------------------------------------------------------------------------------
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--
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-- (c) Copyright 2009-2011 Xilinx, Inc. All rights reserved.
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--
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-- This file contains confidential and proprietary information
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-- of Xilinx, Inc. and is protected under U.S. and
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-- international copyright and other intellectual property
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-- laws.
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--
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-- DISCLAIMER
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-- This disclaimer is not a license and does not grant any
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-- rights to the materials distributed herewith. Except as
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-- otherwise provided in a valid license issued to you by
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-- Xilinx, and to the maximum extent permitted by applicable
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-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
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-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
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-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
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-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
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-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
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-- (2) Xilinx shall not be liable (whether in contract or tort,
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-- including negligence, or under any other theory of
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-- liability) for any loss or damage of any kind or nature
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-- CRITICAL APPLICATIONS
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-- other applications that could lead to death, personal
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-- injury, or severe property or environmental damage
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-- (individually and collectively, "Critical
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-- Applications"). Customer assumes the sole risk and
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-- Applications, subject only to applicable laws and
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--
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-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
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-- PART OF THIS FILE AT ALL TIMES.
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--
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-------------------------------------------------------------------------------
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-- Project : Virtex-6 Integrated Block for PCI Express
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-- File : pci_exp_usrapp_pl.vhd
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-- Version : 1.7
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--
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--------------------------------------------------------------------------------
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library ieee;
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use ieee.std_logic_1164.all;
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entity pci_exp_usrapp_pl is
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generic (
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LINK_CAP_MAX_LINK_SPEED : integer := 1);
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port (
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pl_initial_link_width : in std_logic_vector(2 downto 0);
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pl_lane_reversal_mode : in std_logic_vector(1 downto 0);
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pl_link_gen2_capable : in std_logic;
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pl_link_partner_gen2_supported : in std_logic;
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pl_link_upcfg_capable : in std_logic;
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pl_ltssm_state : in std_logic_vector(5 downto 0);
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pl_received_hot_rst : in std_logic;
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pl_sel_link_rate : in std_logic;
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pl_sel_link_width : in std_logic_vector(1 downto 0);
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pl_directed_link_auton : out std_logic;
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pl_directed_link_change : out std_logic_vector(1 downto 0);
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pl_directed_link_speed : out std_logic;
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pl_directed_link_width : out std_logic_vector(1 downto 0);
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pl_upstream_prefer_deemph : out std_logic;
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speed_change_done_n : out std_logic;
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trn_lnk_up_n : in std_logic;
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trn_clk : in std_logic;
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trn_reset_n : in std_logic
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);
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end pci_exp_usrapp_pl;
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architecture rtl of pci_exp_usrapp_pl is
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constant Tcq : integer := 1;
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begin
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process
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begin
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pl_directed_link_auton <= '0';
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pl_directed_link_change <= "00";
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pl_directed_link_speed <= '0';
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pl_directed_link_width <= "00";
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pl_upstream_prefer_deemph <= '0';
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speed_change_done_n <= '1';
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if (LINK_CAP_MAX_LINK_SPEED = 2) then
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wait until trn_lnk_up_n = '0';
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pl_directed_link_speed <= '1';
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pl_directed_link_change <= "10";
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wait until pl_ltssm_state = "100000";
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pl_directed_link_speed <= '0';
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pl_directed_link_change <= "00";
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wait until pl_sel_link_rate = '1';
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speed_change_done_n <= '0';
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end if;
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wait;
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end process;
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end rtl;
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-- pci_exp_usrapp_pl
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