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//-----------------------------------------------------------------------------
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//
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// (c) Copyright 2009-2011 Xilinx, Inc. All rights reserved.
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//
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// This file contains confidential and proprietary information
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// of Xilinx, Inc. and is protected under U.S. and
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// international copyright and other intellectual property
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// laws.
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//
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// DISCLAIMER
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// This disclaimer is not a license and does not grant any
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// rights to the materials distributed herewith. Except as
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// otherwise provided in a valid license issued to you by
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// Xilinx, and to the maximum extent permitted by applicable
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// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
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// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
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// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
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// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
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// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
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// (2) Xilinx shall not be liable (whether in contract or tort,
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// including negligence, or under any other theory of
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// liability) for any loss or damage of any kind or nature
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// related to, arising under or in connection with these
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// materials, including for any direct, or any indirect,
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// special, incidental, or consequential loss or damage
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// (including loss of data, profits, goodwill, or any type of
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// loss or damage suffered as a result of any action brought
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// by a third party) even if such damage or loss was
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// reasonably foreseeable or Xilinx had been advised of the
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// possibility of the same.
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//
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// CRITICAL APPLICATIONS
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// Xilinx products are not designed or intended to be fail-
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// safe, or for use in any application requiring fail-safe
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// performance, such as life-support or safety devices or
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// systems, Class III medical devices, nuclear facilities,
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// applications related to the deployment of airbags, or any
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// other applications that could lead to death, personal
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// injury, or severe property or environmental damage
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// (individually and collectively, "Critical
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// Applications"). Customer assumes the sole risk and
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// liability of any use of Xilinx products in Critical
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// Applications, subject only to applicable laws and
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// regulations governing limitations on product liability.
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//
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// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
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// PART OF THIS FILE AT ALL TIMES.
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//
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//-----------------------------------------------------------------------------
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// Project : Virtex-6 Integrated Block for PCI Express
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// File : pci_exp_usrapp_tx.v
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// Version : 1.7
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//
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//------------------------------------------------------------------------------
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`include "board_common.v"
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module pci_exp_usrapp_tx (
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trn_td,
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trn_trem_n,
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trn_tsof_n,
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trn_teof_n,
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trn_terrfwd_n,
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trn_tsrc_rdy_n,
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trn_tsrc_dsc_n,
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trn_clk,
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trn_reset_n,
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trn_lnk_up_n,
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trn_tdst_rdy_n,
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trn_tdst_dsc_n,
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trn_tbuf_av,
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speed_change_done_n
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);
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output [(64 - 1):0] trn_td;
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output [(8 - 1):0] trn_trem_n;
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output trn_tsof_n;
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output trn_teof_n;
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output trn_terrfwd_n;
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output trn_tsrc_rdy_n;
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output trn_tsrc_dsc_n;
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input trn_clk;
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input trn_reset_n;
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input trn_lnk_up_n;
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input trn_tdst_rdy_n;
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input trn_tdst_dsc_n;
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input [(6 - 1):0] trn_tbuf_av;
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input speed_change_done_n;
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parameter Tcq = 1;
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parameter LINK_CAP_MAX_LINK_SPEED = 4'h1;
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/* Output Variables */
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reg [(64 - 1):0] trn_td;
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reg [(8 - 1):0] trn_trem_n;
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reg trn_tsof_n;
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reg trn_teof_n;
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reg trn_terrfwd_n;
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reg trn_tsrc_rdy_n;
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reg trn_tsrc_dsc_n;
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/* Local Variables */
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integer i, j, k;
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reg [7:0] DATA_STORE [4095:0];
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reg [31:0] ADDRESS_32_L;
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reg [31:0] ADDRESS_32_H;
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reg [63:0] ADDRESS_64;
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reg [15:0] COMPLETER_ID;
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reg [15:0] COMPLETER_ID_CFG;
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reg [15:0] REQUESTER_ID;
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reg [15:0] DESTINATION_RID;
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reg [2:0] DEFAULT_TC;
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reg [9:0] DEFAULT_LENGTH;
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reg [3:0] DEFAULT_BE_LAST_DW;
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reg [3:0] DEFAULT_BE_FIRST_DW;
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reg [1:0] DEFAULT_ATTR;
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reg [7:0] DEFAULT_TAG;
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reg [3:0] DEFAULT_COMP;
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reg [11:0] EXT_REG_ADDR;
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reg TD;
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reg EP;
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reg [15:0] VENDOR_ID;
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reg [9:0] LENGTH; // For 1DW config and IO transactions
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reg [6:0] RAND_;
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reg [9:0] CFG_DWADDR;
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reg [15:0] P_DEV_BDF;
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reg [31:0] P_IO_ADDR;
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reg [31:0] P_ADDRESS_1L;
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reg [31:0] P_ADDRESS_2L;
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reg [31:0] P_ADDRESS_3L;
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reg [31:0] P_ADDRESS_4L;
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reg [31:0] P_ADDRESS_H;
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reg [9:0] P_CFG_DWADDR;
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event test_begin;
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reg [31:0] P_ADDRESS_MASK;
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reg [31:0] P_READ_DATA; // will store the results of a PCIE read completion
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reg [31:0] data;
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reg p_read_data_valid;
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reg [31:0] P_WRITE_DATA;
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reg [31:0] temp_register;
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reg error_check;
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// BAR Init variables
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reg [32:0] BAR_INIT_P_BAR[6:0]; // 6 corresponds to Expansion ROM
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// note that bit 32 is for overflow checking
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reg [31:0] BAR_INIT_P_BAR_RANGE[6:0]; // 6 corresponds to Expansion ROM
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reg [1:0] BAR_INIT_P_BAR_ENABLED[6:0]; // 6 corresponds to Expansion ROM
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// 0 = disabled; 1 = io mapped; 2 = mem32 mapped; 3 = mem64 mapped
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reg [31:0] BAR_INIT_P_MEM64_HI_START; // start address for hi memory space
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reg [31:0] BAR_INIT_P_MEM64_LO_START; // start address for hi memory space
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reg [32:0] BAR_INIT_P_MEM32_START; // start address for low memory space
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// top bit used for overflow indicator
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reg [32:0] BAR_INIT_P_IO_START; // start address for io space
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reg [100:0] BAR_INIT_MESSAGE[3:0]; // to be used to display info to user
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reg [32:0] BAR_INIT_TEMP;
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reg OUT_OF_LO_MEM; // flags to indicate out of mem, mem64, and io
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reg OUT_OF_IO;
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reg OUT_OF_HI_MEM;
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reg [3:0] ii;
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integer jj;
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reg [31:0] DEV_VEN_ID; // holds device and vendor id
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integer PIO_MAX_NUM_BLOCK_RAMS; // holds the max number of block RAMS
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reg [31:0] PIO_MAX_MEMORY;
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reg [31:0] PIO_ADDRESS; // holds the current PIO testing address
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reg pio_check_design; // boolean value to check PCI Express BAR configuration against
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// limitations of PIO design. Setting this to true will cause the
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// testbench to check if the core has been configured for more than
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// one IO space, one general purpose Mem32 space (not counting
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// the Mem32 EROM space), and one Mem64 space.
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reg cpld_to; // boolean value to indicate if time out has occured while waiting for cpld
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reg cpld_to_finish; // boolean value to indicate to $finish on cpld_to
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reg verbose; // boolean value to display additional info to stdout
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integer NUMBER_OF_IO_BARS;
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integer NUMBER_OF_MEM32_BARS; // Not counting the Mem32 EROM space
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integer NUMBER_OF_MEM64_BARS;
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initial
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begin
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ADDRESS_32_L = 32'b1011_1110_1110_1111_1100_1010_1111_1110;
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ADDRESS_32_H = 32'b1011_1110_1110_1111_1100_1010_1111_1110;
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ADDRESS_64 = { ADDRESS_32_H, ADDRESS_32_L };
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COMPLETER_ID = 16'b0000_0000_1010_0000;
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COMPLETER_ID_CFG = 16'b0000_0001_1010_0000;
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REQUESTER_ID = 16'b0000_0001_1010_1111;
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DESTINATION_RID = 16'b0000_0001_1010_1111;
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DEFAULT_TC = 3'b000;
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DEFAULT_LENGTH = 10'h000;
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DEFAULT_BE_LAST_DW = 4'h0;
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DEFAULT_BE_FIRST_DW = 4'h0;
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DEFAULT_ATTR = 2'b01;
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DEFAULT_TAG = 8'h00;
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DEFAULT_COMP = 4'h0;
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EXT_REG_ADDR = 12'h000;
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TD = 0;
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EP = 0;
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VENDOR_ID = 16'h10ee;
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LENGTH = 10'b00_0000_0001;
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end
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initial begin
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// Pre-BAR initialization
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BAR_INIT_MESSAGE[0] = "DISABLED";
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BAR_INIT_MESSAGE[1] = "IO MAPPED";
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BAR_INIT_MESSAGE[2] = "MEM32 MAPPED";
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BAR_INIT_MESSAGE[3] = "MEM64 MAPPED";
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OUT_OF_LO_MEM = 1'b0;
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OUT_OF_IO = 1'b0;
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OUT_OF_HI_MEM = 1'b0;
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// Disable variables to start
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for (ii = 0; ii <= 6; ii = ii + 1) begin
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BAR_INIT_P_BAR[ii] = 33'h00000_0000;
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BAR_INIT_P_BAR_RANGE[ii] = 32'h0000_0000;
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BAR_INIT_P_BAR_ENABLED[ii] = 2'b00;
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end
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BAR_INIT_P_MEM64_HI_START = 32'h0000_0001; // hi 32 bit start of 64bit memory
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BAR_INIT_P_MEM64_LO_START = 32'h0000_0000; // low 32 bit start of 64bit memory
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BAR_INIT_P_MEM32_START = 33'h00000_0000; // start of 32bit memory
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BAR_INIT_P_IO_START = 33'h00000_0000; // start of 32bit io
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DEV_VEN_ID = (32'h6014 << 16) | (32'h10EE);
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PIO_MAX_MEMORY = 8192; // PIO has max of 8Kbytes of memory
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PIO_MAX_NUM_BLOCK_RAMS = 4; // PIO has four block RAMS to test
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PIO_MAX_MEMORY = 2048; // PIO has 4 memory regions with 2 Kbytes of memory per region, ie 8 Kbytes
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PIO_MAX_NUM_BLOCK_RAMS = 4; // PIO has four block RAMS to test
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pio_check_design = 1; // By default check to make sure the core has been configured
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// appropriately for the PIO design
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cpld_to = 0; // By default time out has not occured
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cpld_to_finish = 1; // By default end simulation on time out
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| 275 |
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| 276 |
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verbose = 0; // turned off by default
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| 277 |
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| 278 |
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NUMBER_OF_IO_BARS = 0;
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| 279 |
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NUMBER_OF_MEM32_BARS = 0;
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| 280 |
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NUMBER_OF_MEM64_BARS = 0;
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| 282 |
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end
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| 285 |
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| 286 |
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| 287 |
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| 288 |
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reg [255:0] testname;
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integer test_vars [31:0];
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reg [7:0] expect_cpld_payload [4095:0];
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reg [7:0] expect_msgd_payload [4095:0];
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reg [7:0] expect_memwr_payload [4095:0];
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reg [7:0] expect_memwr64_payload [4095:0];
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reg [7:0] expect_cfgwr_payload [3:0];
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| 295 |
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reg expect_status;
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reg expect_finish_check;
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| 297 |
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initial begin
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| 299 |
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if ($value$plusargs("TESTNAME=%s", testname))
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$display("Running test {%0s}......", testname);
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else
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begin
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// $display("[%t] %m: No TESTNAME specified!", $realtime);
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// $finish(2);
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testname = "pio_writeReadBack_test0";
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$display("Running default test {%0s}......", testname);
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end
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expect_status = 0;
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expect_finish_check = 0;
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| 310 |
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// Tx transaction interface signal initialization.
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trn_td = 0;
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trn_tsof_n = 1;
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| 313 |
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trn_teof_n = 1;
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| 314 |
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trn_trem_n = 0;
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| 315 |
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trn_terrfwd_n = 1;
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| 316 |
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trn_tsrc_rdy_n = 1 ;
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trn_tsrc_dsc_n = 1;
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| 318 |
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| 319 |
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// Payload data initialization.
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TSK_USR_DATA_SETUP_SEQ;
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| 322 |
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//Test starts here
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| 323 |
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if (testname == "dummy_test")
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begin
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| 325 |
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$display("[%t] %m: Invalid TESTNAME: %0s", $realtime, testname);
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| 326 |
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$finish(2);
|
| 327 |
|
|
end
|
| 328 |
|
|
`include "tests.v"
|
| 329 |
|
|
else begin
|
| 330 |
|
|
$display("[%t] %m: Error: Unrecognized TESTNAME: %0s", $realtime, testname);
|
| 331 |
|
|
$finish(2);
|
| 332 |
|
|
end
|
| 333 |
|
|
end
|
| 334 |
|
|
|
| 335 |
|
|
task TSK_SYSTEM_INITIALIZATION;
|
| 336 |
|
|
begin
|
| 337 |
|
|
//--------------------------------------------------------------------------
|
| 338 |
|
|
// Event # 1: Wait for Transaction reset to be de-asserted..
|
| 339 |
|
|
//--------------------------------------------------------------------------
|
| 340 |
|
|
|
| 341 |
|
|
wait (trn_reset_n == 1);
|
| 342 |
|
|
|
| 343 |
|
|
$display("[%t] : Transaction Reset Is De-asserted...", $realtime);
|
| 344 |
|
|
|
| 345 |
|
|
|
| 346 |
|
|
//--------------------------------------------------------------------------
|
| 347 |
|
|
// Event # 2: Wait for Transaction link to be asserted..
|
| 348 |
|
|
//--------------------------------------------------------------------------
|
| 349 |
|
|
|
| 350 |
|
|
wait (trn_lnk_up_n == 0);
|
| 351 |
|
|
|
| 352 |
|
|
wait (((LINK_CAP_MAX_LINK_SPEED == 4'h2) && (speed_change_done_n == 1'b0)) || (LINK_CAP_MAX_LINK_SPEED == 4'h1))
|
| 353 |
|
|
|
| 354 |
|
|
$display("[%t] : Transaction Link Is Up...", $realtime);
|
| 355 |
|
|
|
| 356 |
|
|
|
| 357 |
|
|
TSK_SYSTEM_CONFIGURATION_CHECK;
|
| 358 |
|
|
|
| 359 |
|
|
end
|
| 360 |
|
|
endtask
|
| 361 |
|
|
|
| 362 |
|
|
|
| 363 |
|
|
/************************************************************
|
| 364 |
|
|
Task : TSK_SYSTEM_CONFIGURATION_CHECK
|
| 365 |
|
|
Description : Check that options selected from Coregen GUI are
|
| 366 |
|
|
set correctly.
|
| 367 |
|
|
Checks - Max Link Speed/Width, Device/Vendor ID, CMPS
|
| 368 |
|
|
*************************************************************/
|
| 369 |
|
|
task TSK_SYSTEM_CONFIGURATION_CHECK;
|
| 370 |
|
|
begin
|
| 371 |
|
|
|
| 372 |
|
|
error_check = 0;
|
| 373 |
|
|
|
| 374 |
|
|
// Check Link Speed/Width
|
| 375 |
|
|
TSK_TX_TYPE0_CONFIGURATION_READ(DEFAULT_TAG, 12'h70, 4'hF);
|
| 376 |
|
|
TSK_WAIT_FOR_READ_DATA;
|
| 377 |
|
|
|
| 378 |
|
|
if (P_READ_DATA[19:16] == 4'h1) begin
|
| 379 |
|
|
if (P_READ_DATA[19:16] == 1)
|
| 380 |
|
|
$display("[%t] : Check Max Link Speed = 2.5GT/s - PASSED", $realtime);
|
| 381 |
|
|
else
|
| 382 |
|
|
$display("[%t] : Check Max Link Speed = 5.0GT/s - PASSED", $realtime);
|
| 383 |
|
|
end else begin
|
| 384 |
|
|
$display("[%t] : Check Max Link Speed - FAILED", $realtime);
|
| 385 |
|
|
$display("[%t] : Data Error Mismatch, Parameter Data %s != Read Data %x", $realtime, "1", P_READ_DATA[19:16]);
|
| 386 |
|
|
end
|
| 387 |
|
|
|
| 388 |
|
|
|
| 389 |
|
|
if (P_READ_DATA[23:20] == 4'h04)
|
| 390 |
|
|
$display("[%t] : Check Negotiated Link Width = 04x - PASSED", $realtime);
|
| 391 |
|
|
else
|
| 392 |
|
|
$display("[%t] : Data Error Mismatch, Parameter Data %s != Read Data %x", $realtime, "04", P_READ_DATA[23:20]);
|
| 393 |
|
|
|
| 394 |
|
|
|
| 395 |
|
|
// Check Device/Vendor ID
|
| 396 |
|
|
TSK_TX_TYPE0_CONFIGURATION_READ(DEFAULT_TAG, 12'h0, 4'hF);
|
| 397 |
|
|
TSK_WAIT_FOR_READ_DATA;
|
| 398 |
|
|
|
| 399 |
|
|
if (P_READ_DATA[31:16] != 16'h6014) begin
|
| 400 |
|
|
$display("[%t] : Check Device/Vendor ID - FAILED", $realtime);
|
| 401 |
|
|
$display("[%t] : Data Error Mismatch, Parameter Data %x != Read Data %x", $realtime, 16'h6014, P_READ_DATA);
|
| 402 |
|
|
error_check = 1;
|
| 403 |
|
|
end else begin
|
| 404 |
|
|
$display("[%t] : Check Device/Vendor ID - PASSED", $realtime);
|
| 405 |
|
|
end
|
| 406 |
|
|
|
| 407 |
|
|
|
| 408 |
|
|
// Check CMPS
|
| 409 |
|
|
TSK_TX_TYPE0_CONFIGURATION_READ(DEFAULT_TAG, 12'h64, 4'hF);
|
| 410 |
|
|
TSK_WAIT_FOR_READ_DATA;
|
| 411 |
|
|
|
| 412 |
|
|
if (P_READ_DATA[2:0] != 3'd2) begin
|
| 413 |
|
|
$display("[%t] : Check CMPS ID - FAILED", $realtime);
|
| 414 |
|
|
$display("[%t] : Data Error Mismatch, Parameter Data %x != Read data %x", $realtime, 3'h2, P_READ_DATA);
|
| 415 |
|
|
error_check = 1;
|
| 416 |
|
|
end else begin
|
| 417 |
|
|
$display("[%t] : Check CMPS ID - PASSED", $realtime);
|
| 418 |
|
|
|
| 419 |
|
|
end
|
| 420 |
|
|
|
| 421 |
|
|
|
| 422 |
|
|
if (error_check == 0) begin
|
| 423 |
|
|
$display("[%t] : SYSTEM CHECK PASSED", $realtime);
|
| 424 |
|
|
end else begin
|
| 425 |
|
|
$display("[%t] : SYSTEM CHECK FAILED", $realtime);
|
| 426 |
|
|
$finish;
|
| 427 |
|
|
end
|
| 428 |
|
|
|
| 429 |
|
|
end
|
| 430 |
|
|
endtask
|
| 431 |
|
|
|
| 432 |
|
|
|
| 433 |
|
|
|
| 434 |
|
|
|
| 435 |
|
|
|
| 436 |
|
|
|
| 437 |
|
|
|
| 438 |
|
|
|
| 439 |
|
|
|
| 440 |
|
|
/************************************************************
|
| 441 |
|
|
Task : TSK_TX_TYPE0_CONFIGURATION_READ
|
| 442 |
|
|
Inputs : Tag, PCI/PCI-Express Reg Address, First BypeEn
|
| 443 |
|
|
Outputs : Transaction Tx Interface Signaling
|
| 444 |
|
|
Description : Generates a Type 0 Configuration Read TLP
|
| 445 |
|
|
*************************************************************/
|
| 446 |
|
|
|
| 447 |
|
|
task TSK_TX_TYPE0_CONFIGURATION_READ;
|
| 448 |
|
|
input [7:0] tag_;
|
| 449 |
|
|
input [11:0] reg_addr_;
|
| 450 |
|
|
input [3:0] first_dw_be_;
|
| 451 |
|
|
begin
|
| 452 |
|
|
if (trn_lnk_up_n) begin
|
| 453 |
|
|
|
| 454 |
|
|
$display("[%t] : Trn interface is MIA", $realtime);
|
| 455 |
|
|
$finish(1);
|
| 456 |
|
|
|
| 457 |
|
|
end
|
| 458 |
|
|
|
| 459 |
|
|
TSK_TX_SYNCHRONIZE(0, 0);
|
| 460 |
|
|
|
| 461 |
|
|
trn_td <= #(Tcq) {
|
| 462 |
|
|
1'b0,
|
| 463 |
|
|
2'b00,
|
| 464 |
|
|
5'b00100,
|
| 465 |
|
|
1'b0,
|
| 466 |
|
|
3'b000,
|
| 467 |
|
|
4'b0000,
|
| 468 |
|
|
1'b0,
|
| 469 |
|
|
1'b0,
|
| 470 |
|
|
2'b00,
|
| 471 |
|
|
2'b00,
|
| 472 |
|
|
10'b0000000001, // 32
|
| 473 |
|
|
COMPLETER_ID_CFG,
|
| 474 |
|
|
tag_,
|
| 475 |
|
|
4'b0000,
|
| 476 |
|
|
first_dw_be_ // 64
|
| 477 |
|
|
};
|
| 478 |
|
|
|
| 479 |
|
|
trn_tsof_n <= #(Tcq) 0;
|
| 480 |
|
|
trn_teof_n <= #(Tcq) 1;
|
| 481 |
|
|
trn_trem_n <= #(Tcq) 0;
|
| 482 |
|
|
trn_tsrc_rdy_n <= #(Tcq) 0 ;
|
| 483 |
|
|
|
| 484 |
|
|
TSK_TX_SYNCHRONIZE(1, 0);
|
| 485 |
|
|
|
| 486 |
|
|
trn_td <= #(Tcq) {
|
| 487 |
|
|
COMPLETER_ID_CFG,
|
| 488 |
|
|
4'b0000,
|
| 489 |
|
|
reg_addr_[11:2],
|
| 490 |
|
|
2'b00,
|
| 491 |
|
|
32'b0
|
| 492 |
|
|
};
|
| 493 |
|
|
|
| 494 |
|
|
trn_tsof_n <= #(Tcq) 1;
|
| 495 |
|
|
trn_teof_n <= #(Tcq) 0;
|
| 496 |
|
|
trn_trem_n <= #(Tcq) 8'h0F;
|
| 497 |
|
|
trn_tsrc_rdy_n <= #(Tcq) 0 ;
|
| 498 |
|
|
|
| 499 |
|
|
TSK_TX_SYNCHRONIZE(1, 1);
|
| 500 |
|
|
|
| 501 |
|
|
trn_teof_n <= #(Tcq) 1;
|
| 502 |
|
|
trn_trem_n <= #(Tcq) 0;
|
| 503 |
|
|
trn_tsrc_rdy_n <= #(Tcq) 1;
|
| 504 |
|
|
|
| 505 |
|
|
end
|
| 506 |
|
|
endtask // TSK_TX_TYPE0_CONFIGURATION_READ
|
| 507 |
|
|
|
| 508 |
|
|
/************************************************************
|
| 509 |
|
|
Task : TSK_TX_TYPE1_CONFIGURATION_READ
|
| 510 |
|
|
Inputs : Tag, PCI/PCI-Express Reg Address, First BypeEn
|
| 511 |
|
|
Outputs : Transaction Tx Interface Signaling
|
| 512 |
|
|
Description : Generates a Type 1 Configuration Read TLP
|
| 513 |
|
|
*************************************************************/
|
| 514 |
|
|
|
| 515 |
|
|
task TSK_TX_TYPE1_CONFIGURATION_READ;
|
| 516 |
|
|
input [7:0] tag_;
|
| 517 |
|
|
input [11:0] reg_addr_;
|
| 518 |
|
|
input [3:0] first_dw_be_;
|
| 519 |
|
|
begin
|
| 520 |
|
|
if (trn_lnk_up_n) begin
|
| 521 |
|
|
|
| 522 |
|
|
$display("[%t] : Trn interface is MIA", $realtime);
|
| 523 |
|
|
$finish(1);
|
| 524 |
|
|
|
| 525 |
|
|
end
|
| 526 |
|
|
|
| 527 |
|
|
TSK_TX_SYNCHRONIZE(0, 0);
|
| 528 |
|
|
|
| 529 |
|
|
trn_td <= #(Tcq) {
|
| 530 |
|
|
1'b0,
|
| 531 |
|
|
2'b00,
|
| 532 |
|
|
5'b00101,
|
| 533 |
|
|
1'b0,
|
| 534 |
|
|
3'b000,
|
| 535 |
|
|
4'b0000,
|
| 536 |
|
|
1'b0,
|
| 537 |
|
|
1'b0,
|
| 538 |
|
|
2'b00,
|
| 539 |
|
|
2'b00,
|
| 540 |
|
|
10'b0000000001, // 32
|
| 541 |
|
|
COMPLETER_ID_CFG,
|
| 542 |
|
|
tag_,
|
| 543 |
|
|
4'b0000,
|
| 544 |
|
|
first_dw_be_ // 64
|
| 545 |
|
|
};
|
| 546 |
|
|
|
| 547 |
|
|
trn_tsof_n <= #(Tcq) 0;
|
| 548 |
|
|
trn_teof_n <= #(Tcq) 1;
|
| 549 |
|
|
trn_trem_n <= #(Tcq) 0;
|
| 550 |
|
|
trn_tsrc_rdy_n <= #(Tcq) 0 ;
|
| 551 |
|
|
|
| 552 |
|
|
TSK_TX_SYNCHRONIZE(1, 0);
|
| 553 |
|
|
|
| 554 |
|
|
trn_td <= #(Tcq) {
|
| 555 |
|
|
COMPLETER_ID_CFG,
|
| 556 |
|
|
4'b0000,
|
| 557 |
|
|
reg_addr_[11:2],
|
| 558 |
|
|
2'b00,
|
| 559 |
|
|
32'b0
|
| 560 |
|
|
};
|
| 561 |
|
|
|
| 562 |
|
|
trn_tsof_n <= #(Tcq) 1;
|
| 563 |
|
|
trn_teof_n <= #(Tcq) 0;
|
| 564 |
|
|
trn_trem_n <= #(Tcq) 8'h0F;
|
| 565 |
|
|
trn_tsrc_rdy_n <= #(Tcq) 0 ;
|
| 566 |
|
|
|
| 567 |
|
|
TSK_TX_SYNCHRONIZE(1, 1);
|
| 568 |
|
|
|
| 569 |
|
|
trn_teof_n <= #(Tcq) 1;
|
| 570 |
|
|
trn_trem_n <= #(Tcq) 0;
|
| 571 |
|
|
trn_tsrc_rdy_n <= #(Tcq) 1;
|
| 572 |
|
|
|
| 573 |
|
|
end
|
| 574 |
|
|
endtask // TSK_TX_TYPE1_CONFIGURATION_READ
|
| 575 |
|
|
|
| 576 |
|
|
/************************************************************
|
| 577 |
|
|
Task : TSK_TX_TYPE0_CONFIGURATION_WRITE
|
| 578 |
|
|
Inputs : Tag, PCI/PCI-Express Reg Address, First BypeEn
|
| 579 |
|
|
Outputs : Transaction Tx Interface Signaling
|
| 580 |
|
|
Description : Generates a Type 0 Configuration Write TLP
|
| 581 |
|
|
*************************************************************/
|
| 582 |
|
|
|
| 583 |
|
|
task TSK_TX_TYPE0_CONFIGURATION_WRITE;
|
| 584 |
|
|
input [7:0] tag_;
|
| 585 |
|
|
input [11:0] reg_addr_;
|
| 586 |
|
|
input [31:0] reg_data_;
|
| 587 |
|
|
input [3:0] first_dw_be_;
|
| 588 |
|
|
begin
|
| 589 |
|
|
if (trn_lnk_up_n) begin
|
| 590 |
|
|
|
| 591 |
|
|
$display("[%t] : Trn interface is MIA", $realtime);
|
| 592 |
|
|
$finish(1);
|
| 593 |
|
|
|
| 594 |
|
|
end
|
| 595 |
|
|
|
| 596 |
|
|
TSK_TX_SYNCHRONIZE(0, 0);
|
| 597 |
|
|
|
| 598 |
|
|
trn_td <= #(Tcq) {
|
| 599 |
|
|
1'b0,
|
| 600 |
|
|
2'b10,
|
| 601 |
|
|
5'b00100,
|
| 602 |
|
|
1'b0,
|
| 603 |
|
|
3'b000,
|
| 604 |
|
|
4'b0000,
|
| 605 |
|
|
1'b0,
|
| 606 |
|
|
1'b0,
|
| 607 |
|
|
2'b00,
|
| 608 |
|
|
2'b00,
|
| 609 |
|
|
10'b0000000001, // 32
|
| 610 |
|
|
COMPLETER_ID_CFG,
|
| 611 |
|
|
tag_,
|
| 612 |
|
|
4'b0000,
|
| 613 |
|
|
first_dw_be_ // 64
|
| 614 |
|
|
};
|
| 615 |
|
|
|
| 616 |
|
|
trn_tsof_n <= #(Tcq) 0;
|
| 617 |
|
|
trn_tsrc_rdy_n <= #(Tcq) 0 ;
|
| 618 |
|
|
|
| 619 |
|
|
TSK_TX_SYNCHRONIZE(1, 0);
|
| 620 |
|
|
|
| 621 |
|
|
trn_td <= #(Tcq) {
|
| 622 |
|
|
COMPLETER_ID_CFG,
|
| 623 |
|
|
4'b0000,
|
| 624 |
|
|
reg_addr_[11:2],
|
| 625 |
|
|
2'b00, // 32
|
| 626 |
|
|
reg_data_[7:0],
|
| 627 |
|
|
reg_data_[15:8],
|
| 628 |
|
|
reg_data_[23:16],
|
| 629 |
|
|
reg_data_[31:24] // 64
|
| 630 |
|
|
};
|
| 631 |
|
|
|
| 632 |
|
|
trn_tsof_n <= #(Tcq) 1;
|
| 633 |
|
|
trn_teof_n <= #(Tcq) 0;
|
| 634 |
|
|
trn_trem_n <= #(Tcq) 8'h00;
|
| 635 |
|
|
|
| 636 |
|
|
TSK_TX_SYNCHRONIZE(1, 1);
|
| 637 |
|
|
|
| 638 |
|
|
trn_teof_n <= #(Tcq) 1;
|
| 639 |
|
|
trn_trem_n <= #(Tcq) 0;
|
| 640 |
|
|
trn_tsrc_rdy_n <= #(Tcq) 1;
|
| 641 |
|
|
|
| 642 |
|
|
end
|
| 643 |
|
|
endtask // TSK_TX_TYPE0_CONFIGURATION_WRITE
|
| 644 |
|
|
|
| 645 |
|
|
/************************************************************
|
| 646 |
|
|
Task : TSK_TX_TYPE1_CONFIGURATION_WRITE
|
| 647 |
|
|
Inputs : Tag, PCI/PCI-Express Reg Address, First BypeEn
|
| 648 |
|
|
Outputs : Transaction Tx Interface Signaling
|
| 649 |
|
|
Description : Generates a Type 1 Configuration Write TLP
|
| 650 |
|
|
*************************************************************/
|
| 651 |
|
|
|
| 652 |
|
|
task TSK_TX_TYPE1_CONFIGURATION_WRITE;
|
| 653 |
|
|
input [7:0] tag_;
|
| 654 |
|
|
input [11:0] reg_addr_;
|
| 655 |
|
|
input [31:0] reg_data_;
|
| 656 |
|
|
input [3:0] first_dw_be_;
|
| 657 |
|
|
begin
|
| 658 |
|
|
if (trn_lnk_up_n) begin
|
| 659 |
|
|
|
| 660 |
|
|
$display("[%t] : Trn interface is MIA", $realtime);
|
| 661 |
|
|
$finish(1);
|
| 662 |
|
|
|
| 663 |
|
|
end
|
| 664 |
|
|
|
| 665 |
|
|
TSK_TX_SYNCHRONIZE(0, 0);
|
| 666 |
|
|
|
| 667 |
|
|
trn_td <= #(Tcq) {
|
| 668 |
|
|
1'b0,
|
| 669 |
|
|
2'b10,
|
| 670 |
|
|
5'b00101,
|
| 671 |
|
|
1'b0,
|
| 672 |
|
|
3'b000,
|
| 673 |
|
|
4'b0000,
|
| 674 |
|
|
1'b0,
|
| 675 |
|
|
1'b0,
|
| 676 |
|
|
2'b00,
|
| 677 |
|
|
2'b00,
|
| 678 |
|
|
10'b0000000001, // 32
|
| 679 |
|
|
COMPLETER_ID_CFG,
|
| 680 |
|
|
tag_,
|
| 681 |
|
|
4'b0000,
|
| 682 |
|
|
first_dw_be_ // 64
|
| 683 |
|
|
};
|
| 684 |
|
|
|
| 685 |
|
|
trn_tsof_n <= #(Tcq) 0;
|
| 686 |
|
|
trn_tsrc_rdy_n <= #(Tcq) 0 ;
|
| 687 |
|
|
|
| 688 |
|
|
TSK_TX_SYNCHRONIZE(1, 0);
|
| 689 |
|
|
|
| 690 |
|
|
trn_td <= #(Tcq) {
|
| 691 |
|
|
COMPLETER_ID_CFG,
|
| 692 |
|
|
4'b0000,
|
| 693 |
|
|
reg_addr_[11:2],
|
| 694 |
|
|
2'b00, // 32
|
| 695 |
|
|
reg_data_[7:0],
|
| 696 |
|
|
reg_data_[15:8],
|
| 697 |
|
|
reg_data_[23:16],
|
| 698 |
|
|
reg_data_[31:24] // 64
|
| 699 |
|
|
};
|
| 700 |
|
|
|
| 701 |
|
|
trn_tsof_n <= #(Tcq) 1;
|
| 702 |
|
|
trn_teof_n <= #(Tcq) 0;
|
| 703 |
|
|
trn_trem_n <= #(Tcq) 8'h00;
|
| 704 |
|
|
|
| 705 |
|
|
TSK_TX_SYNCHRONIZE(1, 1);
|
| 706 |
|
|
|
| 707 |
|
|
trn_teof_n <= #(Tcq) 1;
|
| 708 |
|
|
trn_trem_n <= #(Tcq) 0;
|
| 709 |
|
|
trn_tsrc_rdy_n <= #(Tcq) 1;
|
| 710 |
|
|
|
| 711 |
|
|
end
|
| 712 |
|
|
endtask // TSK_TX_TYPE1_CONFIGURATION_WRITE
|
| 713 |
|
|
|
| 714 |
|
|
/************************************************************
|
| 715 |
|
|
Task : TSK_TX_MEMORY_READ_32
|
| 716 |
|
|
Inputs : Tag, Length, Address, Last Byte En, First Byte En
|
| 717 |
|
|
Outputs : Transaction Tx Interface Signaling
|
| 718 |
|
|
Description : Generates a Memory Read 32 TLP
|
| 719 |
|
|
*************************************************************/
|
| 720 |
|
|
|
| 721 |
|
|
task TSK_TX_MEMORY_READ_32;
|
| 722 |
|
|
input [7:0] tag_;
|
| 723 |
|
|
input [2:0] tc_;
|
| 724 |
|
|
input [9:0] len_;
|
| 725 |
|
|
input [31:0] addr_;
|
| 726 |
|
|
input [3:0] last_dw_be_;
|
| 727 |
|
|
input [3:0] first_dw_be_;
|
| 728 |
|
|
begin
|
| 729 |
|
|
if (trn_lnk_up_n) begin
|
| 730 |
|
|
|
| 731 |
|
|
$display("[%t] : Trn interface is MIA", $realtime);
|
| 732 |
|
|
$finish(1);
|
| 733 |
|
|
|
| 734 |
|
|
end
|
| 735 |
|
|
|
| 736 |
|
|
TSK_TX_SYNCHRONIZE(0, 0);
|
| 737 |
|
|
|
| 738 |
|
|
trn_td <= #(Tcq) {
|
| 739 |
|
|
1'b0,
|
| 740 |
|
|
2'b00,
|
| 741 |
|
|
5'b00000,
|
| 742 |
|
|
1'b0,
|
| 743 |
|
|
tc_,
|
| 744 |
|
|
4'b0000,
|
| 745 |
|
|
1'b0,
|
| 746 |
|
|
1'b0,
|
| 747 |
|
|
2'b00,
|
| 748 |
|
|
2'b00,
|
| 749 |
|
|
len_, // 32
|
| 750 |
|
|
COMPLETER_ID_CFG,
|
| 751 |
|
|
tag_,
|
| 752 |
|
|
last_dw_be_,
|
| 753 |
|
|
first_dw_be_ // 64
|
| 754 |
|
|
};
|
| 755 |
|
|
trn_tsof_n <= #(Tcq) 0;
|
| 756 |
|
|
trn_teof_n <= #(Tcq) 1;
|
| 757 |
|
|
trn_trem_n <= #(Tcq) 0;
|
| 758 |
|
|
trn_tsrc_rdy_n <= #(Tcq) 0 ;
|
| 759 |
|
|
|
| 760 |
|
|
TSK_TX_SYNCHRONIZE(1, 0);
|
| 761 |
|
|
|
| 762 |
|
|
trn_td <= #(Tcq) {
|
| 763 |
|
|
addr_[31:2],
|
| 764 |
|
|
2'b00,
|
| 765 |
|
|
32'b0
|
| 766 |
|
|
};
|
| 767 |
|
|
|
| 768 |
|
|
trn_tsof_n <= #(Tcq) 1;
|
| 769 |
|
|
trn_teof_n <= #(Tcq) 0;
|
| 770 |
|
|
trn_trem_n <= #(Tcq) 8'h0F;
|
| 771 |
|
|
trn_tsrc_rdy_n <= #(Tcq) 0 ;
|
| 772 |
|
|
|
| 773 |
|
|
TSK_TX_SYNCHRONIZE(1, 1);
|
| 774 |
|
|
|
| 775 |
|
|
trn_teof_n <= #(Tcq) 1;
|
| 776 |
|
|
trn_trem_n <= #(Tcq) 0;
|
| 777 |
|
|
trn_tsrc_rdy_n <= #(Tcq) 1;
|
| 778 |
|
|
|
| 779 |
|
|
end
|
| 780 |
|
|
endtask // TSK_TX_MEMORY_READ_32
|
| 781 |
|
|
|
| 782 |
|
|
/************************************************************
|
| 783 |
|
|
Task : TSK_TX_MEMORY_READ_64
|
| 784 |
|
|
Inputs : Tag, Length, Address, Last Byte En, First Byte En
|
| 785 |
|
|
Outputs : Transaction Tx Interface Signaling
|
| 786 |
|
|
Description : Generates a Memory Read 64 TLP
|
| 787 |
|
|
*************************************************************/
|
| 788 |
|
|
|
| 789 |
|
|
task TSK_TX_MEMORY_READ_64;
|
| 790 |
|
|
input [7:0] tag_;
|
| 791 |
|
|
input [2:0] tc_;
|
| 792 |
|
|
input [9:0] len_;
|
| 793 |
|
|
input [63:0] addr_;
|
| 794 |
|
|
input [3:0] last_dw_be_;
|
| 795 |
|
|
input [3:0] first_dw_be_;
|
| 796 |
|
|
begin
|
| 797 |
|
|
if (trn_lnk_up_n) begin
|
| 798 |
|
|
|
| 799 |
|
|
$display("[%t] : Trn interface is MIA", $realtime);
|
| 800 |
|
|
$finish(1);
|
| 801 |
|
|
|
| 802 |
|
|
end
|
| 803 |
|
|
|
| 804 |
|
|
TSK_TX_SYNCHRONIZE(0, 0);
|
| 805 |
|
|
|
| 806 |
|
|
trn_td <= #(Tcq) {
|
| 807 |
|
|
1'b0,
|
| 808 |
|
|
2'b01,
|
| 809 |
|
|
5'b00000,
|
| 810 |
|
|
1'b0,
|
| 811 |
|
|
tc_,
|
| 812 |
|
|
4'b0000,
|
| 813 |
|
|
1'b0,
|
| 814 |
|
|
1'b0,
|
| 815 |
|
|
2'b00,
|
| 816 |
|
|
2'b00,
|
| 817 |
|
|
len_, // 32
|
| 818 |
|
|
COMPLETER_ID_CFG,
|
| 819 |
|
|
tag_,
|
| 820 |
|
|
last_dw_be_,
|
| 821 |
|
|
first_dw_be_ // 64
|
| 822 |
|
|
};
|
| 823 |
|
|
trn_tsof_n <= #(Tcq) 0;
|
| 824 |
|
|
trn_teof_n <= #(Tcq) 1;
|
| 825 |
|
|
trn_trem_n <= #(Tcq) 0;
|
| 826 |
|
|
trn_tsrc_rdy_n <= #(Tcq) 0 ;
|
| 827 |
|
|
|
| 828 |
|
|
TSK_TX_SYNCHRONIZE(1, 0);
|
| 829 |
|
|
|
| 830 |
|
|
trn_td <= #(Tcq) {
|
| 831 |
|
|
addr_[63:2],
|
| 832 |
|
|
2'b00
|
| 833 |
|
|
};
|
| 834 |
|
|
|
| 835 |
|
|
trn_tsof_n <= #(Tcq) 1;
|
| 836 |
|
|
trn_teof_n <= #(Tcq) 0;
|
| 837 |
|
|
trn_trem_n <= #(Tcq) 8'h00;
|
| 838 |
|
|
trn_tsrc_rdy_n <= #(Tcq) 0 ;
|
| 839 |
|
|
|
| 840 |
|
|
TSK_TX_SYNCHRONIZE(1, 1);
|
| 841 |
|
|
|
| 842 |
|
|
trn_teof_n <= #(Tcq) 1;
|
| 843 |
|
|
trn_trem_n <= #(Tcq) 0;
|
| 844 |
|
|
trn_tsrc_rdy_n <= #(Tcq) 1;
|
| 845 |
|
|
|
| 846 |
|
|
end
|
| 847 |
|
|
endtask // TSK_TX_MEMORY_READ_64
|
| 848 |
|
|
|
| 849 |
|
|
/************************************************************
|
| 850 |
|
|
Task : TSK_TX_MEMORY_WRITE_32
|
| 851 |
|
|
Inputs : Tag, Length, Address, Last Byte En, First Byte En
|
| 852 |
|
|
Outputs : Transaction Tx Interface Signaling
|
| 853 |
|
|
Description : Generates a Memory Write 32 TLP
|
| 854 |
|
|
*************************************************************/
|
| 855 |
|
|
|
| 856 |
|
|
task TSK_TX_MEMORY_WRITE_32;
|
| 857 |
|
|
input [7:0] tag_;
|
| 858 |
|
|
input [2:0] tc_;
|
| 859 |
|
|
input [9:0] len_;
|
| 860 |
|
|
input [31:0] addr_;
|
| 861 |
|
|
input [3:0] last_dw_be_;
|
| 862 |
|
|
input [3:0] first_dw_be_;
|
| 863 |
|
|
input ep_;
|
| 864 |
|
|
reg [10:0] _len;
|
| 865 |
|
|
integer _j;
|
| 866 |
|
|
begin
|
| 867 |
|
|
|
| 868 |
|
|
if (len_ == 0)
|
| 869 |
|
|
|
| 870 |
|
|
_len = 1024;
|
| 871 |
|
|
|
| 872 |
|
|
else
|
| 873 |
|
|
|
| 874 |
|
|
_len = len_;
|
| 875 |
|
|
|
| 876 |
|
|
if (trn_lnk_up_n) begin
|
| 877 |
|
|
|
| 878 |
|
|
$display("[%t] : Trn interface is MIA", $realtime);
|
| 879 |
|
|
$finish(1);
|
| 880 |
|
|
|
| 881 |
|
|
end
|
| 882 |
|
|
|
| 883 |
|
|
TSK_TX_SYNCHRONIZE(0, 0);
|
| 884 |
|
|
|
| 885 |
|
|
trn_td <= #(Tcq) {
|
| 886 |
|
|
1'b0,
|
| 887 |
|
|
2'b10,
|
| 888 |
|
|
5'b00000,
|
| 889 |
|
|
1'b0,
|
| 890 |
|
|
tc_,
|
| 891 |
|
|
4'b0000,
|
| 892 |
|
|
1'b0,
|
| 893 |
|
|
1'b0,
|
| 894 |
|
|
2'b00,
|
| 895 |
|
|
2'b00,
|
| 896 |
|
|
len_, // 32
|
| 897 |
|
|
COMPLETER_ID_CFG,
|
| 898 |
|
|
tag_,
|
| 899 |
|
|
last_dw_be_,
|
| 900 |
|
|
first_dw_be_ // 64
|
| 901 |
|
|
};
|
| 902 |
|
|
trn_tsof_n <= #(Tcq) 0;
|
| 903 |
|
|
trn_teof_n <= #(Tcq) 1;
|
| 904 |
|
|
trn_trem_n <= #(Tcq) 0;
|
| 905 |
|
|
trn_tsrc_rdy_n <= #(Tcq) 0 ;
|
| 906 |
|
|
|
| 907 |
|
|
TSK_TX_SYNCHRONIZE(1, 0);
|
| 908 |
|
|
|
| 909 |
|
|
trn_td <= #(Tcq) {
|
| 910 |
|
|
addr_[31:2],
|
| 911 |
|
|
2'b00,
|
| 912 |
|
|
DATA_STORE[0],
|
| 913 |
|
|
DATA_STORE[1],
|
| 914 |
|
|
DATA_STORE[2],
|
| 915 |
|
|
DATA_STORE[3]
|
| 916 |
|
|
};
|
| 917 |
|
|
|
| 918 |
|
|
trn_tsof_n <= #(Tcq) 1;
|
| 919 |
|
|
|
| 920 |
|
|
if (_len != 1) begin
|
| 921 |
|
|
|
| 922 |
|
|
for (_j = 4; _j < (_len * 4); _j = _j + 8) begin
|
| 923 |
|
|
|
| 924 |
|
|
TSK_TX_SYNCHRONIZE(1, 0);
|
| 925 |
|
|
|
| 926 |
|
|
trn_td <= #(Tcq) {
|
| 927 |
|
|
DATA_STORE[_j + 0],
|
| 928 |
|
|
DATA_STORE[_j + 1],
|
| 929 |
|
|
DATA_STORE[_j + 2],
|
| 930 |
|
|
DATA_STORE[_j + 3],
|
| 931 |
|
|
DATA_STORE[_j + 4],
|
| 932 |
|
|
DATA_STORE[_j + 5],
|
| 933 |
|
|
DATA_STORE[_j + 6],
|
| 934 |
|
|
DATA_STORE[_j + 7]
|
| 935 |
|
|
};
|
| 936 |
|
|
|
| 937 |
|
|
|
| 938 |
|
|
if ((_j + 7) >= ((_len * 4) - 1)) begin
|
| 939 |
|
|
|
| 940 |
|
|
trn_teof_n <= #(Tcq) 0;
|
| 941 |
|
|
if (ep_)
|
| 942 |
|
|
trn_terrfwd_n <= #(Tcq) 0;
|
| 943 |
|
|
|
| 944 |
|
|
if (((_len - 1) % 2) == 0)
|
| 945 |
|
|
|
| 946 |
|
|
trn_trem_n <= #(Tcq) 8'h00;
|
| 947 |
|
|
|
| 948 |
|
|
else
|
| 949 |
|
|
|
| 950 |
|
|
trn_trem_n <= #(Tcq) 8'h0f;
|
| 951 |
|
|
|
| 952 |
|
|
end
|
| 953 |
|
|
|
| 954 |
|
|
end
|
| 955 |
|
|
|
| 956 |
|
|
end else begin
|
| 957 |
|
|
|
| 958 |
|
|
trn_teof_n <= #(Tcq) 0;
|
| 959 |
|
|
if (ep_)
|
| 960 |
|
|
trn_terrfwd_n <= #(Tcq) 0;
|
| 961 |
|
|
trn_trem_n <= #(Tcq) 8'h00;
|
| 962 |
|
|
|
| 963 |
|
|
end
|
| 964 |
|
|
|
| 965 |
|
|
TSK_TX_SYNCHRONIZE(1, 1);
|
| 966 |
|
|
|
| 967 |
|
|
trn_teof_n <= #(Tcq) 1;
|
| 968 |
|
|
trn_terrfwd_n <= #(Tcq) 1;
|
| 969 |
|
|
trn_trem_n <= #(Tcq) 0;
|
| 970 |
|
|
trn_tsrc_rdy_n <= #(Tcq) 1;
|
| 971 |
|
|
|
| 972 |
|
|
end
|
| 973 |
|
|
endtask // TSK_TX_MEMORY_WRITE_32
|
| 974 |
|
|
|
| 975 |
|
|
/************************************************************
|
| 976 |
|
|
Task : TSK_TX_MEMORY_WRITE_64
|
| 977 |
|
|
Inputs : Tag, Length, Address, Last Byte En, First Byte En
|
| 978 |
|
|
Outputs : Transaction Tx Interface Signaling
|
| 979 |
|
|
Description : Generates a Memory Write 64 TLP
|
| 980 |
|
|
*************************************************************/
|
| 981 |
|
|
|
| 982 |
|
|
task TSK_TX_MEMORY_WRITE_64;
|
| 983 |
|
|
input [7:0] tag_;
|
| 984 |
|
|
input [2:0] tc_;
|
| 985 |
|
|
input [9:0] len_;
|
| 986 |
|
|
input [63:0] addr_;
|
| 987 |
|
|
input [3:0] last_dw_be_;
|
| 988 |
|
|
input [3:0] first_dw_be_;
|
| 989 |
|
|
input ep_;
|
| 990 |
|
|
reg [10:0] _len;
|
| 991 |
|
|
integer _j;
|
| 992 |
|
|
begin
|
| 993 |
|
|
|
| 994 |
|
|
if (len_ == 0)
|
| 995 |
|
|
|
| 996 |
|
|
_len = 1024;
|
| 997 |
|
|
|
| 998 |
|
|
else
|
| 999 |
|
|
|
| 1000 |
|
|
_len = len_;
|
| 1001 |
|
|
|
| 1002 |
|
|
if (trn_lnk_up_n) begin
|
| 1003 |
|
|
|
| 1004 |
|
|
$display("[%t] : Trn interface is MIA", $realtime);
|
| 1005 |
|
|
$finish(1);
|
| 1006 |
|
|
|
| 1007 |
|
|
end
|
| 1008 |
|
|
|
| 1009 |
|
|
TSK_TX_SYNCHRONIZE(0, 0);
|
| 1010 |
|
|
|
| 1011 |
|
|
trn_td <= #(Tcq) {
|
| 1012 |
|
|
1'b0,
|
| 1013 |
|
|
2'b11,
|
| 1014 |
|
|
5'b00000,
|
| 1015 |
|
|
1'b0,
|
| 1016 |
|
|
tc_,
|
| 1017 |
|
|
4'b0000,
|
| 1018 |
|
|
1'b0,
|
| 1019 |
|
|
1'b0,
|
| 1020 |
|
|
2'b00,
|
| 1021 |
|
|
2'b00,
|
| 1022 |
|
|
len_, // 32
|
| 1023 |
|
|
COMPLETER_ID_CFG,
|
| 1024 |
|
|
tag_,
|
| 1025 |
|
|
last_dw_be_,
|
| 1026 |
|
|
first_dw_be_ // 64
|
| 1027 |
|
|
};
|
| 1028 |
|
|
trn_tsof_n <= #(Tcq) 0;
|
| 1029 |
|
|
trn_teof_n <= #(Tcq) 1;
|
| 1030 |
|
|
trn_trem_n <= #(Tcq) 0;
|
| 1031 |
|
|
trn_tsrc_rdy_n <= #(Tcq) 0 ;
|
| 1032 |
|
|
|
| 1033 |
|
|
TSK_TX_SYNCHRONIZE(1, 0);
|
| 1034 |
|
|
|
| 1035 |
|
|
trn_td <= #(Tcq) {
|
| 1036 |
|
|
addr_[63:2],
|
| 1037 |
|
|
2'b00
|
| 1038 |
|
|
};
|
| 1039 |
|
|
trn_tsof_n <= #(Tcq) 1;
|
| 1040 |
|
|
|
| 1041 |
|
|
for (_j = 0; _j < (_len * 4); _j = _j + 8) begin
|
| 1042 |
|
|
|
| 1043 |
|
|
TSK_TX_SYNCHRONIZE(1, 0);
|
| 1044 |
|
|
|
| 1045 |
|
|
trn_td <= #(Tcq) {
|
| 1046 |
|
|
DATA_STORE[_j + 0],
|
| 1047 |
|
|
DATA_STORE[_j + 1],
|
| 1048 |
|
|
DATA_STORE[_j + 2],
|
| 1049 |
|
|
DATA_STORE[_j + 3],
|
| 1050 |
|
|
DATA_STORE[_j + 4],
|
| 1051 |
|
|
DATA_STORE[_j + 5],
|
| 1052 |
|
|
DATA_STORE[_j + 6],
|
| 1053 |
|
|
DATA_STORE[_j + 7]
|
| 1054 |
|
|
};
|
| 1055 |
|
|
|
| 1056 |
|
|
|
| 1057 |
|
|
if ((_j + 7) >= ((_len * 4) - 1)) begin
|
| 1058 |
|
|
|
| 1059 |
|
|
trn_teof_n <= #(Tcq) 0;
|
| 1060 |
|
|
|
| 1061 |
|
|
if (ep_)
|
| 1062 |
|
|
trn_terrfwd_n <= #(Tcq) 0;
|
| 1063 |
|
|
|
| 1064 |
|
|
if ((_len % 2) == 0)
|
| 1065 |
|
|
|
| 1066 |
|
|
trn_trem_n <= #(Tcq) 8'h00;
|
| 1067 |
|
|
else
|
| 1068 |
|
|
|
| 1069 |
|
|
trn_trem_n <= #(Tcq) 8'h0f;
|
| 1070 |
|
|
end
|
| 1071 |
|
|
|
| 1072 |
|
|
end
|
| 1073 |
|
|
|
| 1074 |
|
|
TSK_TX_SYNCHRONIZE(1, 1);
|
| 1075 |
|
|
|
| 1076 |
|
|
trn_teof_n <= #(Tcq) 1;
|
| 1077 |
|
|
trn_terrfwd_n <= #(Tcq) 1;
|
| 1078 |
|
|
trn_trem_n <= #(Tcq) 0;
|
| 1079 |
|
|
trn_tsrc_rdy_n <= #(Tcq) 1;
|
| 1080 |
|
|
|
| 1081 |
|
|
end
|
| 1082 |
|
|
endtask // TSK_TX_MEMORY_WRITE_64
|
| 1083 |
|
|
|
| 1084 |
|
|
/************************************************************
|
| 1085 |
|
|
Task : TSK_TX_COMPLETION
|
| 1086 |
|
|
Inputs : Tag, TC, Length, Completion ID
|
| 1087 |
|
|
Outputs : Transaction Tx Interface Signaling
|
| 1088 |
|
|
Description : Generates a Completion TLP
|
| 1089 |
|
|
*************************************************************/
|
| 1090 |
|
|
|
| 1091 |
|
|
task TSK_TX_COMPLETION;
|
| 1092 |
|
|
input [7:0] tag_;
|
| 1093 |
|
|
input [2:0] tc_;
|
| 1094 |
|
|
input [9:0] len_;
|
| 1095 |
|
|
input [2:0] comp_status_;
|
| 1096 |
|
|
begin
|
| 1097 |
|
|
|
| 1098 |
|
|
if (trn_lnk_up_n) begin
|
| 1099 |
|
|
|
| 1100 |
|
|
$display("[%t] : Trn interface is MIA", $realtime);
|
| 1101 |
|
|
$finish(1);
|
| 1102 |
|
|
|
| 1103 |
|
|
end
|
| 1104 |
|
|
|
| 1105 |
|
|
TSK_TX_SYNCHRONIZE(0, 0);
|
| 1106 |
|
|
|
| 1107 |
|
|
trn_td <= #(Tcq) {
|
| 1108 |
|
|
1'b0,
|
| 1109 |
|
|
2'b00,
|
| 1110 |
|
|
5'b01010,
|
| 1111 |
|
|
1'b0,
|
| 1112 |
|
|
tc_,
|
| 1113 |
|
|
4'b0000,
|
| 1114 |
|
|
1'b0,
|
| 1115 |
|
|
1'b0,
|
| 1116 |
|
|
2'b00,
|
| 1117 |
|
|
2'b00,
|
| 1118 |
|
|
len_, // 32
|
| 1119 |
|
|
COMPLETER_ID_CFG,
|
| 1120 |
|
|
comp_status_,
|
| 1121 |
|
|
1'b0,
|
| 1122 |
|
|
12'b0
|
| 1123 |
|
|
};
|
| 1124 |
|
|
trn_tsof_n <= #(Tcq) 0;
|
| 1125 |
|
|
trn_teof_n <= #(Tcq) 1;
|
| 1126 |
|
|
trn_trem_n <= #(Tcq) 0;
|
| 1127 |
|
|
trn_tsrc_rdy_n <= #(Tcq) 0 ;
|
| 1128 |
|
|
|
| 1129 |
|
|
TSK_TX_SYNCHRONIZE(1, 0);
|
| 1130 |
|
|
|
| 1131 |
|
|
trn_td <= #(Tcq) {
|
| 1132 |
|
|
COMPLETER_ID_CFG,
|
| 1133 |
|
|
tag_,
|
| 1134 |
|
|
8'b00,
|
| 1135 |
|
|
32'b0
|
| 1136 |
|
|
};
|
| 1137 |
|
|
trn_tsof_n <= #(Tcq) 1;
|
| 1138 |
|
|
trn_teof_n <= #(Tcq) 0;
|
| 1139 |
|
|
trn_trem_n <= #(Tcq) 8'h0F;
|
| 1140 |
|
|
|
| 1141 |
|
|
TSK_TX_SYNCHRONIZE(1, 1);
|
| 1142 |
|
|
|
| 1143 |
|
|
trn_teof_n <= #(Tcq) 1;
|
| 1144 |
|
|
trn_trem_n <= #(Tcq) 0;
|
| 1145 |
|
|
trn_tsrc_rdy_n <= #(Tcq) 1;
|
| 1146 |
|
|
|
| 1147 |
|
|
end
|
| 1148 |
|
|
endtask // TSK_TX_COMPLETION
|
| 1149 |
|
|
|
| 1150 |
|
|
/************************************************************
|
| 1151 |
|
|
Task : TSK_TX_COMPLETION_DATA
|
| 1152 |
|
|
Inputs : Tag, TC, Length, Completion ID
|
| 1153 |
|
|
Outputs : Transaction Tx Interface Signaling
|
| 1154 |
|
|
Description : Generates a Completion TLP
|
| 1155 |
|
|
*************************************************************/
|
| 1156 |
|
|
|
| 1157 |
|
|
task TSK_TX_COMPLETION_DATA;
|
| 1158 |
|
|
input [7:0] tag_;
|
| 1159 |
|
|
input [2:0] tc_;
|
| 1160 |
|
|
input [9:0] len_;
|
| 1161 |
|
|
input [11:0] byte_count_;
|
| 1162 |
|
|
input [6:0] lower_addr_;
|
| 1163 |
|
|
input [2:0] comp_status_;
|
| 1164 |
|
|
input ep_;
|
| 1165 |
|
|
reg [10:0] _len;
|
| 1166 |
|
|
integer _j;
|
| 1167 |
|
|
begin
|
| 1168 |
|
|
if (len_ == 0)
|
| 1169 |
|
|
|
| 1170 |
|
|
_len = 1024;
|
| 1171 |
|
|
|
| 1172 |
|
|
else
|
| 1173 |
|
|
|
| 1174 |
|
|
_len = len_;
|
| 1175 |
|
|
|
| 1176 |
|
|
if (trn_lnk_up_n) begin
|
| 1177 |
|
|
|
| 1178 |
|
|
$display("[%t] : Trn interface is MIA", $realtime);
|
| 1179 |
|
|
$finish(1);
|
| 1180 |
|
|
|
| 1181 |
|
|
end
|
| 1182 |
|
|
|
| 1183 |
|
|
TSK_TX_SYNCHRONIZE(0, 0);
|
| 1184 |
|
|
|
| 1185 |
|
|
trn_td <= #(Tcq) {
|
| 1186 |
|
|
1'b0,
|
| 1187 |
|
|
2'b10,
|
| 1188 |
|
|
5'b01010,
|
| 1189 |
|
|
1'b0,
|
| 1190 |
|
|
tc_,
|
| 1191 |
|
|
4'b0000,
|
| 1192 |
|
|
1'b0,
|
| 1193 |
|
|
1'b0,
|
| 1194 |
|
|
2'b00,
|
| 1195 |
|
|
2'b00,
|
| 1196 |
|
|
len_, // 32
|
| 1197 |
|
|
COMPLETER_ID_CFG,
|
| 1198 |
|
|
comp_status_,
|
| 1199 |
|
|
1'b0,
|
| 1200 |
|
|
byte_count_ // 64
|
| 1201 |
|
|
};
|
| 1202 |
|
|
trn_tsof_n <= #(Tcq) 0;
|
| 1203 |
|
|
trn_teof_n <= #(Tcq) 1;
|
| 1204 |
|
|
trn_trem_n <= #(Tcq) 0;
|
| 1205 |
|
|
trn_tsrc_rdy_n <= #(Tcq) 0 ;
|
| 1206 |
|
|
|
| 1207 |
|
|
TSK_TX_SYNCHRONIZE(1, 0);
|
| 1208 |
|
|
|
| 1209 |
|
|
trn_td <= #(Tcq) {
|
| 1210 |
|
|
COMPLETER_ID_CFG,
|
| 1211 |
|
|
tag_,
|
| 1212 |
|
|
1'b0,
|
| 1213 |
|
|
lower_addr_,
|
| 1214 |
|
|
DATA_STORE[0],
|
| 1215 |
|
|
DATA_STORE[1],
|
| 1216 |
|
|
DATA_STORE[2],
|
| 1217 |
|
|
DATA_STORE[3]
|
| 1218 |
|
|
};
|
| 1219 |
|
|
trn_tsof_n <= #(Tcq) 1;
|
| 1220 |
|
|
|
| 1221 |
|
|
if (_len != 1) begin
|
| 1222 |
|
|
|
| 1223 |
|
|
for (_j = 4; _j < (_len * 4); _j = _j + 8) begin
|
| 1224 |
|
|
|
| 1225 |
|
|
TSK_TX_SYNCHRONIZE(1, 0);
|
| 1226 |
|
|
|
| 1227 |
|
|
trn_td <= #(Tcq) {
|
| 1228 |
|
|
DATA_STORE[_j + 0],
|
| 1229 |
|
|
DATA_STORE[_j + 1],
|
| 1230 |
|
|
DATA_STORE[_j + 2],
|
| 1231 |
|
|
DATA_STORE[_j + 3],
|
| 1232 |
|
|
DATA_STORE[_j + 4],
|
| 1233 |
|
|
DATA_STORE[_j + 5],
|
| 1234 |
|
|
DATA_STORE[_j + 6],
|
| 1235 |
|
|
DATA_STORE[_j + 7]
|
| 1236 |
|
|
};
|
| 1237 |
|
|
|
| 1238 |
|
|
|
| 1239 |
|
|
if ((_j + 7) >= ((_len * 4) - 1)) begin
|
| 1240 |
|
|
|
| 1241 |
|
|
trn_teof_n <= #(Tcq) 0;
|
| 1242 |
|
|
|
| 1243 |
|
|
if (ep_)
|
| 1244 |
|
|
trn_terrfwd_n <= #(Tcq) 0;
|
| 1245 |
|
|
|
| 1246 |
|
|
if (((_len - 1) % 2) == 0)
|
| 1247 |
|
|
|
| 1248 |
|
|
trn_trem_n <= #(Tcq) 8'h00;
|
| 1249 |
|
|
|
| 1250 |
|
|
else
|
| 1251 |
|
|
|
| 1252 |
|
|
trn_trem_n <= #(Tcq) 8'h0f;
|
| 1253 |
|
|
|
| 1254 |
|
|
end
|
| 1255 |
|
|
|
| 1256 |
|
|
end
|
| 1257 |
|
|
|
| 1258 |
|
|
end else begin
|
| 1259 |
|
|
|
| 1260 |
|
|
trn_teof_n <= #(Tcq) 0;
|
| 1261 |
|
|
trn_trem_n <= #(Tcq) 8'h00;
|
| 1262 |
|
|
|
| 1263 |
|
|
end
|
| 1264 |
|
|
|
| 1265 |
|
|
TSK_TX_SYNCHRONIZE(1, 1);
|
| 1266 |
|
|
|
| 1267 |
|
|
trn_teof_n <= #(Tcq) 1;
|
| 1268 |
|
|
trn_terrfwd_n <= #(Tcq) 1;
|
| 1269 |
|
|
trn_trem_n <= #(Tcq) 0;
|
| 1270 |
|
|
trn_tsrc_rdy_n <= #(Tcq) 1;
|
| 1271 |
|
|
|
| 1272 |
|
|
end
|
| 1273 |
|
|
endtask // TSK_TX_COMPLETION_DATA
|
| 1274 |
|
|
|
| 1275 |
|
|
/************************************************************
|
| 1276 |
|
|
Task : TSK_TX_MESSAGE
|
| 1277 |
|
|
Inputs : Tag, TC, Address, Message Routing, Message Code
|
| 1278 |
|
|
Outputs : Transaction Tx Interface Signaling
|
| 1279 |
|
|
Description : Generates a Message TLP
|
| 1280 |
|
|
*************************************************************/
|
| 1281 |
|
|
|
| 1282 |
|
|
task TSK_TX_MESSAGE;
|
| 1283 |
|
|
input [7:0] tag_;
|
| 1284 |
|
|
input [2:0] tc_;
|
| 1285 |
|
|
input [9:0] len_;
|
| 1286 |
|
|
input [63:0] data_;
|
| 1287 |
|
|
input [2:0] message_rtg_;
|
| 1288 |
|
|
input [7:0] message_code_;
|
| 1289 |
|
|
begin
|
| 1290 |
|
|
|
| 1291 |
|
|
if (trn_lnk_up_n) begin
|
| 1292 |
|
|
|
| 1293 |
|
|
$display("[%t] : Trn interface is MIA", $realtime);
|
| 1294 |
|
|
$finish(1);
|
| 1295 |
|
|
|
| 1296 |
|
|
end
|
| 1297 |
|
|
|
| 1298 |
|
|
TSK_TX_SYNCHRONIZE(0, 0);
|
| 1299 |
|
|
|
| 1300 |
|
|
trn_td <= #(Tcq) {
|
| 1301 |
|
|
1'b0,
|
| 1302 |
|
|
2'b01,
|
| 1303 |
|
|
{{2'b10}, {message_rtg_}},
|
| 1304 |
|
|
1'b0,
|
| 1305 |
|
|
tc_,
|
| 1306 |
|
|
4'b0000,
|
| 1307 |
|
|
1'b0,
|
| 1308 |
|
|
1'b0,
|
| 1309 |
|
|
2'b00,
|
| 1310 |
|
|
2'b00,
|
| 1311 |
|
|
10'b0, // 32
|
| 1312 |
|
|
COMPLETER_ID_CFG,
|
| 1313 |
|
|
tag_,
|
| 1314 |
|
|
message_code_ // 64
|
| 1315 |
|
|
};
|
| 1316 |
|
|
|
| 1317 |
|
|
trn_tsof_n <= #(Tcq) 0;
|
| 1318 |
|
|
trn_teof_n <= #(Tcq) 1;
|
| 1319 |
|
|
trn_trem_n <= #(Tcq) 0;
|
| 1320 |
|
|
trn_tsrc_rdy_n <= #(Tcq) 0 ;
|
| 1321 |
|
|
|
| 1322 |
|
|
TSK_TX_SYNCHRONIZE(1, 0);
|
| 1323 |
|
|
|
| 1324 |
|
|
trn_td <= #(Tcq) {
|
| 1325 |
|
|
data_
|
| 1326 |
|
|
};
|
| 1327 |
|
|
trn_tsof_n <= #(Tcq) 1;
|
| 1328 |
|
|
trn_teof_n <= #(Tcq) 0;
|
| 1329 |
|
|
trn_trem_n <= #(Tcq) 8'h00;
|
| 1330 |
|
|
|
| 1331 |
|
|
TSK_TX_SYNCHRONIZE(1, 1);
|
| 1332 |
|
|
|
| 1333 |
|
|
trn_teof_n <= #(Tcq) 1;
|
| 1334 |
|
|
trn_trem_n <= #(Tcq) 0;
|
| 1335 |
|
|
trn_tsrc_rdy_n <= #(Tcq) 1;
|
| 1336 |
|
|
|
| 1337 |
|
|
end
|
| 1338 |
|
|
endtask // TSK_TX_MESSAGE
|
| 1339 |
|
|
|
| 1340 |
|
|
/************************************************************
|
| 1341 |
|
|
Task : TSK_TX_MESSAGE_DATA
|
| 1342 |
|
|
Inputs : Tag, TC, Address, Message Routing, Message Code
|
| 1343 |
|
|
Outputs : Transaction Tx Interface Signaling
|
| 1344 |
|
|
Description : Generates a Message Data TLP
|
| 1345 |
|
|
*************************************************************/
|
| 1346 |
|
|
|
| 1347 |
|
|
task TSK_TX_MESSAGE_DATA;
|
| 1348 |
|
|
input [7:0] tag_;
|
| 1349 |
|
|
input [2:0] tc_;
|
| 1350 |
|
|
input [9:0] len_;
|
| 1351 |
|
|
input [63:0] data_;
|
| 1352 |
|
|
input [2:0] message_rtg_;
|
| 1353 |
|
|
input [7:0] message_code_;
|
| 1354 |
|
|
reg [10:0] _len;
|
| 1355 |
|
|
integer _j;
|
| 1356 |
|
|
begin
|
| 1357 |
|
|
|
| 1358 |
|
|
if (len_ == 0)
|
| 1359 |
|
|
|
| 1360 |
|
|
_len = 1024;
|
| 1361 |
|
|
|
| 1362 |
|
|
else
|
| 1363 |
|
|
|
| 1364 |
|
|
_len = len_;
|
| 1365 |
|
|
|
| 1366 |
|
|
if (trn_lnk_up_n) begin
|
| 1367 |
|
|
|
| 1368 |
|
|
$display("[%t] : Trn interface is MIA", $realtime);
|
| 1369 |
|
|
$finish(1);
|
| 1370 |
|
|
|
| 1371 |
|
|
end
|
| 1372 |
|
|
|
| 1373 |
|
|
TSK_TX_SYNCHRONIZE(0, 0);
|
| 1374 |
|
|
|
| 1375 |
|
|
trn_td <= #(Tcq) {
|
| 1376 |
|
|
1'b0,
|
| 1377 |
|
|
2'b11,
|
| 1378 |
|
|
{{2'b10}, {message_rtg_}},
|
| 1379 |
|
|
1'b0,
|
| 1380 |
|
|
tc_,
|
| 1381 |
|
|
4'b0000,
|
| 1382 |
|
|
1'b0,
|
| 1383 |
|
|
1'b0,
|
| 1384 |
|
|
2'b00,
|
| 1385 |
|
|
2'b00,
|
| 1386 |
|
|
len_, // 32
|
| 1387 |
|
|
COMPLETER_ID_CFG,
|
| 1388 |
|
|
tag_,
|
| 1389 |
|
|
message_code_ // 64
|
| 1390 |
|
|
};
|
| 1391 |
|
|
trn_tsof_n <= #(Tcq) 0;
|
| 1392 |
|
|
trn_teof_n <= #(Tcq) 1;
|
| 1393 |
|
|
trn_trem_n <= #(Tcq) 0;
|
| 1394 |
|
|
trn_tsrc_rdy_n <= #(Tcq) 0 ;
|
| 1395 |
|
|
|
| 1396 |
|
|
TSK_TX_SYNCHRONIZE(1, 0);
|
| 1397 |
|
|
|
| 1398 |
|
|
trn_td <= #(Tcq) {
|
| 1399 |
|
|
data_
|
| 1400 |
|
|
};
|
| 1401 |
|
|
trn_tsof_n <= #(Tcq) 1;
|
| 1402 |
|
|
|
| 1403 |
|
|
for (_j = 0; _j < (_len * 4); _j = _j + 8) begin
|
| 1404 |
|
|
|
| 1405 |
|
|
TSK_TX_SYNCHRONIZE(1, 0);
|
| 1406 |
|
|
|
| 1407 |
|
|
trn_td <= #(Tcq) {
|
| 1408 |
|
|
DATA_STORE[_j + 0],
|
| 1409 |
|
|
DATA_STORE[_j + 1],
|
| 1410 |
|
|
DATA_STORE[_j + 2],
|
| 1411 |
|
|
DATA_STORE[_j + 3],
|
| 1412 |
|
|
DATA_STORE[_j + 4],
|
| 1413 |
|
|
DATA_STORE[_j + 5],
|
| 1414 |
|
|
DATA_STORE[_j + 6],
|
| 1415 |
|
|
DATA_STORE[_j + 7]
|
| 1416 |
|
|
};
|
| 1417 |
|
|
|
| 1418 |
|
|
|
| 1419 |
|
|
if ((_j + 7) >= ((_len * 4) - 1)) begin
|
| 1420 |
|
|
|
| 1421 |
|
|
trn_teof_n <= #(Tcq) 0;
|
| 1422 |
|
|
|
| 1423 |
|
|
if ((_len % 2) == 0)
|
| 1424 |
|
|
|
| 1425 |
|
|
trn_trem_n <= #(Tcq) 8'h00;
|
| 1426 |
|
|
else
|
| 1427 |
|
|
|
| 1428 |
|
|
trn_trem_n <= #(Tcq) 8'h0f;
|
| 1429 |
|
|
end
|
| 1430 |
|
|
|
| 1431 |
|
|
end
|
| 1432 |
|
|
|
| 1433 |
|
|
TSK_TX_SYNCHRONIZE(1, 1);
|
| 1434 |
|
|
|
| 1435 |
|
|
trn_teof_n <= #(Tcq) 1;
|
| 1436 |
|
|
trn_trem_n <= #(Tcq) 0;
|
| 1437 |
|
|
trn_tsrc_rdy_n <= #(Tcq) 1;
|
| 1438 |
|
|
|
| 1439 |
|
|
end
|
| 1440 |
|
|
endtask // TSK_TX_MESSAGE_DATA
|
| 1441 |
|
|
|
| 1442 |
|
|
|
| 1443 |
|
|
/************************************************************
|
| 1444 |
|
|
Task : TSK_TX_IO_READ
|
| 1445 |
|
|
Inputs : Tag, Address
|
| 1446 |
|
|
Outputs : Transaction Tx Interface Signaling
|
| 1447 |
|
|
Description : Generates a IO Read TLP
|
| 1448 |
|
|
*************************************************************/
|
| 1449 |
|
|
|
| 1450 |
|
|
task TSK_TX_IO_READ;
|
| 1451 |
|
|
input [7:0] tag_;
|
| 1452 |
|
|
input [31:0] addr_;
|
| 1453 |
|
|
input [3:0] first_dw_be_;
|
| 1454 |
|
|
begin
|
| 1455 |
|
|
if (trn_lnk_up_n) begin
|
| 1456 |
|
|
|
| 1457 |
|
|
$display("[%t] : Trn interface is MIA", $realtime);
|
| 1458 |
|
|
$finish(1);
|
| 1459 |
|
|
|
| 1460 |
|
|
end
|
| 1461 |
|
|
|
| 1462 |
|
|
TSK_TX_SYNCHRONIZE(0, 0);
|
| 1463 |
|
|
|
| 1464 |
|
|
trn_td <= #(Tcq) {
|
| 1465 |
|
|
1'b0,
|
| 1466 |
|
|
2'b00,
|
| 1467 |
|
|
5'b00010,
|
| 1468 |
|
|
1'b0,
|
| 1469 |
|
|
3'b000,
|
| 1470 |
|
|
4'b0000,
|
| 1471 |
|
|
1'b0,
|
| 1472 |
|
|
1'b0,
|
| 1473 |
|
|
2'b00,
|
| 1474 |
|
|
2'b00,
|
| 1475 |
|
|
10'b1, // 32
|
| 1476 |
|
|
COMPLETER_ID_CFG,
|
| 1477 |
|
|
tag_,
|
| 1478 |
|
|
4'b0,
|
| 1479 |
|
|
first_dw_be_ // 64
|
| 1480 |
|
|
};
|
| 1481 |
|
|
trn_tsof_n <= #(Tcq) 0;
|
| 1482 |
|
|
trn_teof_n <= #(Tcq) 1;
|
| 1483 |
|
|
trn_trem_n <= #(Tcq) 0;
|
| 1484 |
|
|
trn_tsrc_rdy_n <= #(Tcq) 0 ;
|
| 1485 |
|
|
|
| 1486 |
|
|
TSK_TX_SYNCHRONIZE(1, 0);
|
| 1487 |
|
|
|
| 1488 |
|
|
trn_td <= #(Tcq) {
|
| 1489 |
|
|
addr_[31:2],
|
| 1490 |
|
|
2'b00,
|
| 1491 |
|
|
32'b0
|
| 1492 |
|
|
};
|
| 1493 |
|
|
trn_tsof_n <= #(Tcq) 1;
|
| 1494 |
|
|
trn_teof_n <= #(Tcq) 0;
|
| 1495 |
|
|
trn_trem_n <= #(Tcq) 8'h0F;
|
| 1496 |
|
|
trn_tsrc_rdy_n <= #(Tcq) 0 ;
|
| 1497 |
|
|
|
| 1498 |
|
|
TSK_TX_SYNCHRONIZE(1, 1);
|
| 1499 |
|
|
|
| 1500 |
|
|
trn_teof_n <= #(Tcq) 1;
|
| 1501 |
|
|
trn_trem_n <= #(Tcq) 0;
|
| 1502 |
|
|
trn_tsrc_rdy_n <= #(Tcq) 1;
|
| 1503 |
|
|
|
| 1504 |
|
|
end
|
| 1505 |
|
|
endtask // TSK_TX_IO_READ
|
| 1506 |
|
|
|
| 1507 |
|
|
/************************************************************
|
| 1508 |
|
|
Task : TSK_TX_IO_WRITE
|
| 1509 |
|
|
Inputs : Tag, Address, Data
|
| 1510 |
|
|
Outputs : Transaction Tx Interface Signaling
|
| 1511 |
|
|
Description : Generates a IO Read TLP
|
| 1512 |
|
|
*************************************************************/
|
| 1513 |
|
|
|
| 1514 |
|
|
task TSK_TX_IO_WRITE;
|
| 1515 |
|
|
input [7:0] tag_;
|
| 1516 |
|
|
input [31:0] addr_;
|
| 1517 |
|
|
input [3:0] first_dw_be_;
|
| 1518 |
|
|
input [31:0] data_;
|
| 1519 |
|
|
begin
|
| 1520 |
|
|
if (trn_lnk_up_n) begin
|
| 1521 |
|
|
|
| 1522 |
|
|
$display("[%t] : Trn interface is MIA", $realtime);
|
| 1523 |
|
|
$finish(1);
|
| 1524 |
|
|
|
| 1525 |
|
|
end
|
| 1526 |
|
|
|
| 1527 |
|
|
TSK_TX_SYNCHRONIZE(0, 0);
|
| 1528 |
|
|
|
| 1529 |
|
|
trn_td <= #(Tcq) {
|
| 1530 |
|
|
1'b0,
|
| 1531 |
|
|
2'b10,
|
| 1532 |
|
|
5'b00010,
|
| 1533 |
|
|
1'b0,
|
| 1534 |
|
|
3'b000,
|
| 1535 |
|
|
4'b0000,
|
| 1536 |
|
|
1'b0,
|
| 1537 |
|
|
1'b0,
|
| 1538 |
|
|
2'b00,
|
| 1539 |
|
|
2'b00,
|
| 1540 |
|
|
10'b1, // 32
|
| 1541 |
|
|
COMPLETER_ID_CFG,
|
| 1542 |
|
|
tag_,
|
| 1543 |
|
|
4'b0,
|
| 1544 |
|
|
first_dw_be_ // 64
|
| 1545 |
|
|
};
|
| 1546 |
|
|
trn_tsof_n <= #(Tcq) 0;
|
| 1547 |
|
|
trn_teof_n <= #(Tcq) 1;
|
| 1548 |
|
|
trn_trem_n <= #(Tcq) 0;
|
| 1549 |
|
|
trn_tsrc_rdy_n <= #(Tcq) 0 ;
|
| 1550 |
|
|
|
| 1551 |
|
|
TSK_TX_SYNCHRONIZE(1, 0);
|
| 1552 |
|
|
|
| 1553 |
|
|
trn_td <= #(Tcq) {
|
| 1554 |
|
|
addr_[31:2],
|
| 1555 |
|
|
2'b00,
|
| 1556 |
|
|
data_[7:0],
|
| 1557 |
|
|
data_[15:8],
|
| 1558 |
|
|
data_[23:16],
|
| 1559 |
|
|
data_[31:24]
|
| 1560 |
|
|
};
|
| 1561 |
|
|
trn_tsof_n <= #(Tcq) 1;
|
| 1562 |
|
|
trn_teof_n <= #(Tcq) 0;
|
| 1563 |
|
|
trn_trem_n <= #(Tcq) 8'h00;
|
| 1564 |
|
|
trn_tsrc_rdy_n <= #(Tcq) 0 ;
|
| 1565 |
|
|
|
| 1566 |
|
|
TSK_TX_SYNCHRONIZE(1, 1);
|
| 1567 |
|
|
|
| 1568 |
|
|
trn_teof_n <= #(Tcq) 1;
|
| 1569 |
|
|
trn_trem_n <= #(Tcq) 0;
|
| 1570 |
|
|
trn_tsrc_rdy_n <= #(Tcq) 1;
|
| 1571 |
|
|
|
| 1572 |
|
|
end
|
| 1573 |
|
|
endtask // TSK_TX_IO_WRITE
|
| 1574 |
|
|
|
| 1575 |
|
|
/************************************************************
|
| 1576 |
|
|
Task : TSK_TX_SYNCHRONIZE
|
| 1577 |
|
|
Inputs : None
|
| 1578 |
|
|
Outputs : None
|
| 1579 |
|
|
Description : Synchronize with tx clock and handshake signals
|
| 1580 |
|
|
*************************************************************/
|
| 1581 |
|
|
|
| 1582 |
|
|
task TSK_TX_SYNCHRONIZE;
|
| 1583 |
|
|
input first_;
|
| 1584 |
|
|
input last_call_;
|
| 1585 |
|
|
reg last_;
|
| 1586 |
|
|
begin
|
| 1587 |
|
|
if (trn_lnk_up_n) begin
|
| 1588 |
|
|
|
| 1589 |
|
|
$display("[%t] : Trn interface is MIA", $realtime);
|
| 1590 |
|
|
$finish(1);
|
| 1591 |
|
|
|
| 1592 |
|
|
end
|
| 1593 |
|
|
|
| 1594 |
|
|
@(posedge trn_clk);
|
| 1595 |
|
|
if ((trn_tdst_rdy_n == 1'b1) && (first_ == 1'b1)) begin
|
| 1596 |
|
|
|
| 1597 |
|
|
while (trn_tdst_rdy_n == 1'b1) begin
|
| 1598 |
|
|
|
| 1599 |
|
|
@(posedge trn_clk);
|
| 1600 |
|
|
|
| 1601 |
|
|
end
|
| 1602 |
|
|
end
|
| 1603 |
|
|
if (first_ == 1'b1) begin
|
| 1604 |
|
|
|
| 1605 |
|
|
last_ = (trn_trem_n == 8'h00) ? 0 : 1;
|
| 1606 |
|
|
|
| 1607 |
|
|
// read data driven into memory
|
| 1608 |
|
|
board.RP.com_usrapp.TSK_READ_DATA(last_,
|
| 1609 |
|
|
`TX_LOG,
|
| 1610 |
|
|
trn_td,
|
| 1611 |
|
|
trn_trem_n);
|
| 1612 |
|
|
end
|
| 1613 |
|
|
|
| 1614 |
|
|
|
| 1615 |
|
|
if (last_call_)
|
| 1616 |
|
|
|
| 1617 |
|
|
board.RP.com_usrapp.TSK_PARSE_FRAME(`TX_LOG);
|
| 1618 |
|
|
end
|
| 1619 |
|
|
endtask // TSK_TX_SYNCHRONIZE
|
| 1620 |
|
|
|
| 1621 |
|
|
|
| 1622 |
|
|
/************************************************************
|
| 1623 |
|
|
Task : TSK_USR_DATA_SETUP_SEQ
|
| 1624 |
|
|
Inputs : None
|
| 1625 |
|
|
Outputs : None
|
| 1626 |
|
|
Description : Populates scratch pad data area with known good data.
|
| 1627 |
|
|
*************************************************************/
|
| 1628 |
|
|
|
| 1629 |
|
|
task TSK_USR_DATA_SETUP_SEQ;
|
| 1630 |
|
|
integer i_;
|
| 1631 |
|
|
begin
|
| 1632 |
|
|
for (i_ = 0; i_ <= 4095; i_ = i_ + 1) begin
|
| 1633 |
|
|
DATA_STORE[i_] = i_;
|
| 1634 |
|
|
end
|
| 1635 |
|
|
end
|
| 1636 |
|
|
endtask // TSK_USR_DATA_SETUP_SEQ
|
| 1637 |
|
|
|
| 1638 |
|
|
/************************************************************
|
| 1639 |
|
|
Task : TSK_TX_CLK_EAT
|
| 1640 |
|
|
Inputs : None
|
| 1641 |
|
|
Outputs : None
|
| 1642 |
|
|
Description : Consume clocks.
|
| 1643 |
|
|
*************************************************************/
|
| 1644 |
|
|
|
| 1645 |
|
|
task TSK_TX_CLK_EAT;
|
| 1646 |
|
|
input [31:0] clock_count;
|
| 1647 |
|
|
integer i_;
|
| 1648 |
|
|
begin
|
| 1649 |
|
|
for (i_ = 0; i_ < clock_count; i_ = i_ + 1) begin
|
| 1650 |
|
|
|
| 1651 |
|
|
@(posedge trn_clk);
|
| 1652 |
|
|
|
| 1653 |
|
|
end
|
| 1654 |
|
|
end
|
| 1655 |
|
|
endtask // TSK_TX_CLK_EAT
|
| 1656 |
|
|
|
| 1657 |
|
|
/************************************************************
|
| 1658 |
|
|
Task: TSK_SIMULATION_TIMEOUT
|
| 1659 |
|
|
Description: Set simulation timeout value
|
| 1660 |
|
|
*************************************************************/
|
| 1661 |
|
|
task TSK_SIMULATION_TIMEOUT;
|
| 1662 |
|
|
input [31:0] timeout;
|
| 1663 |
|
|
begin
|
| 1664 |
|
|
force board.RP.rx_usrapp.sim_timeout = timeout;
|
| 1665 |
|
|
end
|
| 1666 |
|
|
endtask
|
| 1667 |
|
|
|
| 1668 |
|
|
|
| 1669 |
|
|
|
| 1670 |
|
|
/************************************************************
|
| 1671 |
|
|
Task : TSK_TX_BAR_READ
|
| 1672 |
|
|
Inputs : Tag, Length, Address, Last Byte En, First Byte En
|
| 1673 |
|
|
Outputs : Transaction Tx Interface Signaling
|
| 1674 |
|
|
Description : Generates a Memory Read 32,64 or IO Read TLP
|
| 1675 |
|
|
requesting 1 dword
|
| 1676 |
|
|
*************************************************************/
|
| 1677 |
|
|
|
| 1678 |
|
|
task TSK_TX_BAR_READ;
|
| 1679 |
|
|
|
| 1680 |
|
|
input [2:0] bar_index;
|
| 1681 |
|
|
input [31:0] byte_offset;
|
| 1682 |
|
|
input [7:0] tag_;
|
| 1683 |
|
|
input [2:0] tc_;
|
| 1684 |
|
|
|
| 1685 |
|
|
|
| 1686 |
|
|
begin
|
| 1687 |
|
|
|
| 1688 |
|
|
|
| 1689 |
|
|
case(BAR_INIT_P_BAR_ENABLED[bar_index])
|
| 1690 |
|
|
2'b01 : // IO SPACE
|
| 1691 |
|
|
begin
|
| 1692 |
|
|
if (verbose) $display("[%t] : IOREAD, address = %x", $realtime,
|
| 1693 |
|
|
BAR_INIT_P_BAR[bar_index][31:0]+(byte_offset));
|
| 1694 |
|
|
|
| 1695 |
|
|
TSK_TX_IO_READ(tag_, BAR_INIT_P_BAR[bar_index][31:0]+(byte_offset), 4'hF);
|
| 1696 |
|
|
end
|
| 1697 |
|
|
|
| 1698 |
|
|
2'b10 : // MEM 32 SPACE
|
| 1699 |
|
|
begin
|
| 1700 |
|
|
|
| 1701 |
|
|
if (verbose) $display("[%t] : MEMREAD32, address = %x", $realtime,
|
| 1702 |
|
|
BAR_INIT_P_BAR[bar_index][31:0]+(byte_offset));
|
| 1703 |
|
|
TSK_TX_MEMORY_READ_32(tag_, tc_, 10'd1,
|
| 1704 |
|
|
BAR_INIT_P_BAR[bar_index][31:0]+(byte_offset), 4'h0, 4'hF);
|
| 1705 |
|
|
end
|
| 1706 |
|
|
2'b11 : // MEM 64 SPACE
|
| 1707 |
|
|
begin
|
| 1708 |
|
|
if (verbose) $display("[%t] : MEMREAD64, address = %x", $realtime,
|
| 1709 |
|
|
BAR_INIT_P_BAR[bar_index][31:0]+(byte_offset));
|
| 1710 |
|
|
TSK_TX_MEMORY_READ_64(tag_, tc_, 10'd1, {BAR_INIT_P_BAR[ii+1][31:0],
|
| 1711 |
|
|
BAR_INIT_P_BAR[bar_index][31:0]+(byte_offset)}, 4'h0, 4'hF);
|
| 1712 |
|
|
|
| 1713 |
|
|
|
| 1714 |
|
|
end
|
| 1715 |
|
|
default : begin
|
| 1716 |
|
|
$display("Error case in task TSK_TX_BAR_READ");
|
| 1717 |
|
|
end
|
| 1718 |
|
|
endcase
|
| 1719 |
|
|
|
| 1720 |
|
|
end
|
| 1721 |
|
|
endtask // TSK_TX_BAR_READ
|
| 1722 |
|
|
|
| 1723 |
|
|
|
| 1724 |
|
|
|
| 1725 |
|
|
/************************************************************
|
| 1726 |
|
|
Task : TSK_TX_BAR_WRITE
|
| 1727 |
|
|
Inputs : Bar Index, Byte Offset, Tag, Tc, 32 bit Data
|
| 1728 |
|
|
Outputs : Transaction Tx Interface Signaling
|
| 1729 |
|
|
Description : Generates a Memory Write 32, 64, IO TLP with
|
| 1730 |
|
|
32 bit data
|
| 1731 |
|
|
*************************************************************/
|
| 1732 |
|
|
|
| 1733 |
|
|
task TSK_TX_BAR_WRITE;
|
| 1734 |
|
|
|
| 1735 |
|
|
input [2:0] bar_index;
|
| 1736 |
|
|
input [31:0] byte_offset;
|
| 1737 |
|
|
input [7:0] tag_;
|
| 1738 |
|
|
input [2:0] tc_;
|
| 1739 |
|
|
input [31:0] data_;
|
| 1740 |
|
|
|
| 1741 |
|
|
begin
|
| 1742 |
|
|
|
| 1743 |
|
|
case(BAR_INIT_P_BAR_ENABLED[bar_index])
|
| 1744 |
|
|
2'b01 : // IO SPACE
|
| 1745 |
|
|
begin
|
| 1746 |
|
|
|
| 1747 |
|
|
if (verbose) $display("[%t] : IOWRITE, address = %x, Write Data %x", $realtime,
|
| 1748 |
|
|
BAR_INIT_P_BAR[bar_index][31:0]+(byte_offset), data_);
|
| 1749 |
|
|
TSK_TX_IO_WRITE(tag_, BAR_INIT_P_BAR[bar_index][31:0]+(byte_offset), 4'hF, data_);
|
| 1750 |
|
|
|
| 1751 |
|
|
end
|
| 1752 |
|
|
|
| 1753 |
|
|
2'b10 : // MEM 32 SPACE
|
| 1754 |
|
|
begin
|
| 1755 |
|
|
|
| 1756 |
|
|
DATA_STORE[0] = data_[7:0];
|
| 1757 |
|
|
DATA_STORE[1] = data_[15:8];
|
| 1758 |
|
|
DATA_STORE[2] = data_[23:16];
|
| 1759 |
|
|
DATA_STORE[3] = data_[31:24];
|
| 1760 |
|
|
if (verbose) $display("[%t] : MEMWRITE32, address = %x, Write Data %x", $realtime,
|
| 1761 |
|
|
BAR_INIT_P_BAR[bar_index][31:0]+(byte_offset), data_);
|
| 1762 |
|
|
TSK_TX_MEMORY_WRITE_32(tag_, tc_, 10'd1,
|
| 1763 |
|
|
BAR_INIT_P_BAR[bar_index][31:0]+(byte_offset), 4'h0, 4'hF, 1'b0);
|
| 1764 |
|
|
|
| 1765 |
|
|
end
|
| 1766 |
|
|
2'b11 : // MEM 64 SPACE
|
| 1767 |
|
|
begin
|
| 1768 |
|
|
|
| 1769 |
|
|
DATA_STORE[0] = data_[7:0];
|
| 1770 |
|
|
DATA_STORE[1] = data_[15:8];
|
| 1771 |
|
|
DATA_STORE[2] = data_[23:16];
|
| 1772 |
|
|
DATA_STORE[3] = data_[31:24];
|
| 1773 |
|
|
if (verbose) $display("[%t] : MEMWRITE64, address = %x, Write Data %x", $realtime,
|
| 1774 |
|
|
BAR_INIT_P_BAR[bar_index][31:0]+(byte_offset), data_);
|
| 1775 |
|
|
TSK_TX_MEMORY_WRITE_64(tag_, tc_, 10'd1, {BAR_INIT_P_BAR[bar_index+1][31:0],
|
| 1776 |
|
|
BAR_INIT_P_BAR[bar_index][31:0]+(byte_offset)}, 4'h0, 4'hF, 1'b0);
|
| 1777 |
|
|
|
| 1778 |
|
|
|
| 1779 |
|
|
|
| 1780 |
|
|
end
|
| 1781 |
|
|
default : begin
|
| 1782 |
|
|
$display("Error case in task TSK_TX_BAR_WRITE");
|
| 1783 |
|
|
end
|
| 1784 |
|
|
endcase
|
| 1785 |
|
|
|
| 1786 |
|
|
|
| 1787 |
|
|
end
|
| 1788 |
|
|
endtask // TSK_TX_BAR_WRITE
|
| 1789 |
|
|
|
| 1790 |
|
|
|
| 1791 |
|
|
|
| 1792 |
|
|
|
| 1793 |
|
|
/************************************************************
|
| 1794 |
|
|
Task : TSK_SET_READ_DATA
|
| 1795 |
|
|
Inputs : Data
|
| 1796 |
|
|
Outputs : None
|
| 1797 |
|
|
Description : Called from common app. Common app hands read
|
| 1798 |
|
|
data to usrapp_tx.
|
| 1799 |
|
|
*************************************************************/
|
| 1800 |
|
|
|
| 1801 |
|
|
task TSK_SET_READ_DATA;
|
| 1802 |
|
|
|
| 1803 |
|
|
input [3:0] be_; // not implementing be's yet
|
| 1804 |
|
|
input [31:0] data_; // might need to change this to byte
|
| 1805 |
|
|
begin
|
| 1806 |
|
|
|
| 1807 |
|
|
P_READ_DATA = data_;
|
| 1808 |
|
|
p_read_data_valid = 1;
|
| 1809 |
|
|
|
| 1810 |
|
|
end
|
| 1811 |
|
|
endtask // TSK_SET_READ_DATA
|
| 1812 |
|
|
|
| 1813 |
|
|
|
| 1814 |
|
|
/************************************************************
|
| 1815 |
|
|
Task : TSK_WAIT_FOR_READ_DATA
|
| 1816 |
|
|
Inputs : None
|
| 1817 |
|
|
Outputs : Read data P_READ_DATA will be valid
|
| 1818 |
|
|
Description : Called from tx app. Common app hands read
|
| 1819 |
|
|
data to usrapp_tx. This task must be executed
|
| 1820 |
|
|
immediately following a call to
|
| 1821 |
|
|
TSK_TX_TYPE0_CONFIGURATION_READ in order for the
|
| 1822 |
|
|
read process to function correctly. Otherwise
|
| 1823 |
|
|
there is a potential race condition with
|
| 1824 |
|
|
p_read_data_valid.
|
| 1825 |
|
|
*************************************************************/
|
| 1826 |
|
|
|
| 1827 |
|
|
task TSK_WAIT_FOR_READ_DATA;
|
| 1828 |
|
|
|
| 1829 |
|
|
integer j;
|
| 1830 |
|
|
|
| 1831 |
|
|
begin
|
| 1832 |
|
|
j = 10;
|
| 1833 |
|
|
p_read_data_valid = 0;
|
| 1834 |
|
|
fork
|
| 1835 |
|
|
while ((!p_read_data_valid) && (cpld_to == 0)) @(posedge trn_clk);
|
| 1836 |
|
|
begin // second process
|
| 1837 |
|
|
while ((j > 0) && (!p_read_data_valid))
|
| 1838 |
|
|
begin
|
| 1839 |
|
|
TSK_TX_CLK_EAT(500);
|
| 1840 |
|
|
j = j - 1;
|
| 1841 |
|
|
end
|
| 1842 |
|
|
if (!p_read_data_valid) begin
|
| 1843 |
|
|
cpld_to = 1;
|
| 1844 |
|
|
if (cpld_to_finish == 1) begin
|
| 1845 |
|
|
$display("TIMEOUT ERROR in usrapp_tx:TSK_WAIT_FOR_READ_DATA. Completion data never received.");
|
| 1846 |
|
|
$finish;
|
| 1847 |
|
|
end
|
| 1848 |
|
|
else
|
| 1849 |
|
|
$display("TIMEOUT WARNING in usrapp_tx:TSK_WAIT_FOR_READ_DATA. Completion data never received.");
|
| 1850 |
|
|
|
| 1851 |
|
|
end
|
| 1852 |
|
|
end
|
| 1853 |
|
|
|
| 1854 |
|
|
join
|
| 1855 |
|
|
|
| 1856 |
|
|
end
|
| 1857 |
|
|
endtask // TSK_WAIT_FOR_READ_DATA
|
| 1858 |
|
|
|
| 1859 |
|
|
|
| 1860 |
|
|
|
| 1861 |
|
|
|
| 1862 |
|
|
/************************************************************
|
| 1863 |
|
|
Function : TSK_DISPLAY_PCIE_MAP
|
| 1864 |
|
|
Inputs : none
|
| 1865 |
|
|
Outputs : none
|
| 1866 |
|
|
Description : Displays the Memory Manager's P_MAP calculations
|
| 1867 |
|
|
based on range values read from PCI_E device.
|
| 1868 |
|
|
*************************************************************/
|
| 1869 |
|
|
|
| 1870 |
|
|
task TSK_DISPLAY_PCIE_MAP;
|
| 1871 |
|
|
|
| 1872 |
|
|
reg[2:0] ii;
|
| 1873 |
|
|
|
| 1874 |
|
|
begin
|
| 1875 |
|
|
|
| 1876 |
|
|
for (ii=0; ii <= 6; ii = ii + 1) begin
|
| 1877 |
|
|
if (ii !=6) begin
|
| 1878 |
|
|
|
| 1879 |
|
|
$display("\tBAR %x: VALUE = %x RANGE = %x TYPE = %s", ii, BAR_INIT_P_BAR[ii][31:0],
|
| 1880 |
|
|
BAR_INIT_P_BAR_RANGE[ii], BAR_INIT_MESSAGE[BAR_INIT_P_BAR_ENABLED[ii]]);
|
| 1881 |
|
|
|
| 1882 |
|
|
end
|
| 1883 |
|
|
else begin
|
| 1884 |
|
|
|
| 1885 |
|
|
$display("\tEROM : VALUE = %x RANGE = %x TYPE = %s", BAR_INIT_P_BAR[6][31:0],
|
| 1886 |
|
|
BAR_INIT_P_BAR_RANGE[6], BAR_INIT_MESSAGE[BAR_INIT_P_BAR_ENABLED[6]]);
|
| 1887 |
|
|
|
| 1888 |
|
|
end
|
| 1889 |
|
|
end
|
| 1890 |
|
|
|
| 1891 |
|
|
end
|
| 1892 |
|
|
|
| 1893 |
|
|
endtask
|
| 1894 |
|
|
|
| 1895 |
|
|
|
| 1896 |
|
|
|
| 1897 |
|
|
/************************************************************
|
| 1898 |
|
|
Task : TSK_BUILD_PCIE_MAP
|
| 1899 |
|
|
Inputs :
|
| 1900 |
|
|
Outputs :
|
| 1901 |
|
|
Description : Looks at range values read from config space and
|
| 1902 |
|
|
builds corresponding mem/io map
|
| 1903 |
|
|
*************************************************************/
|
| 1904 |
|
|
|
| 1905 |
|
|
task TSK_BUILD_PCIE_MAP;
|
| 1906 |
|
|
|
| 1907 |
|
|
integer ii;
|
| 1908 |
|
|
|
| 1909 |
|
|
begin
|
| 1910 |
|
|
|
| 1911 |
|
|
$display("[%t] PCI EXPRESS BAR MEMORY/IO MAPPING PROCESS BEGUN...",$realtime);
|
| 1912 |
|
|
|
| 1913 |
|
|
// handle bars 0-6 (including erom)
|
| 1914 |
|
|
for (ii = 0; ii <= 6; ii = ii + 1) begin
|
| 1915 |
|
|
|
| 1916 |
|
|
if (BAR_INIT_P_BAR_RANGE[ii] != 32'h0000_0000) begin
|
| 1917 |
|
|
|
| 1918 |
|
|
if ((ii != 6) && (BAR_INIT_P_BAR_RANGE[ii] & 32'h0000_0001)) begin // if not erom and io bit set
|
| 1919 |
|
|
|
| 1920 |
|
|
// bar is io mapped
|
| 1921 |
|
|
NUMBER_OF_IO_BARS = NUMBER_OF_IO_BARS + 1;
|
| 1922 |
|
|
|
| 1923 |
|
|
if (pio_check_design && (NUMBER_OF_IO_BARS > 1)) begin
|
| 1924 |
|
|
|
| 1925 |
|
|
$display("[%t] Warning: PIO design only supports 1 IO BAR. Testbench will disable BAR %x",$realtime, ii);
|
| 1926 |
|
|
BAR_INIT_P_BAR_ENABLED[ii] = 2'h0; // disable BAR
|
| 1927 |
|
|
|
| 1928 |
|
|
end
|
| 1929 |
|
|
|
| 1930 |
|
|
else BAR_INIT_P_BAR_ENABLED[ii] = 2'h1;
|
| 1931 |
|
|
|
| 1932 |
|
|
if (!OUT_OF_IO) begin
|
| 1933 |
|
|
|
| 1934 |
|
|
// We need to calculate where the next BAR should start based on the BAR's range
|
| 1935 |
|
|
BAR_INIT_TEMP = BAR_INIT_P_IO_START & {1'b1,(BAR_INIT_P_BAR_RANGE[ii] & 32'hffff_fff0)};
|
| 1936 |
|
|
|
| 1937 |
|
|
if (BAR_INIT_TEMP < BAR_INIT_P_IO_START) begin
|
| 1938 |
|
|
// Current BAR_INIT_P_IO_START is NOT correct start for new base
|
| 1939 |
|
|
BAR_INIT_P_BAR[ii] = BAR_INIT_TEMP + FNC_CONVERT_RANGE_TO_SIZE_32(ii);
|
| 1940 |
|
|
BAR_INIT_P_IO_START = BAR_INIT_P_BAR[ii] + FNC_CONVERT_RANGE_TO_SIZE_32(ii);
|
| 1941 |
|
|
|
| 1942 |
|
|
end
|
| 1943 |
|
|
else begin
|
| 1944 |
|
|
|
| 1945 |
|
|
// Initial BAR case and Current BAR_INIT_P_IO_START is correct start for new base
|
| 1946 |
|
|
BAR_INIT_P_BAR[ii] = BAR_INIT_P_IO_START;
|
| 1947 |
|
|
BAR_INIT_P_IO_START = BAR_INIT_P_IO_START + FNC_CONVERT_RANGE_TO_SIZE_32(ii);
|
| 1948 |
|
|
|
| 1949 |
|
|
end
|
| 1950 |
|
|
|
| 1951 |
|
|
OUT_OF_IO = BAR_INIT_P_BAR[ii][32];
|
| 1952 |
|
|
|
| 1953 |
|
|
if (OUT_OF_IO) begin
|
| 1954 |
|
|
|
| 1955 |
|
|
$display("\tOut of PCI EXPRESS IO SPACE due to BAR %x", ii);
|
| 1956 |
|
|
|
| 1957 |
|
|
end
|
| 1958 |
|
|
|
| 1959 |
|
|
end
|
| 1960 |
|
|
else begin
|
| 1961 |
|
|
|
| 1962 |
|
|
$display("\tOut of PCI EXPRESS IO SPACE due to BAR %x", ii);
|
| 1963 |
|
|
|
| 1964 |
|
|
end
|
| 1965 |
|
|
|
| 1966 |
|
|
|
| 1967 |
|
|
|
| 1968 |
|
|
end // bar is io mapped
|
| 1969 |
|
|
|
| 1970 |
|
|
else begin
|
| 1971 |
|
|
|
| 1972 |
|
|
// bar is mem mapped
|
| 1973 |
|
|
if ((ii != 5) && (BAR_INIT_P_BAR_RANGE[ii] & 32'h0000_0004)) begin
|
| 1974 |
|
|
|
| 1975 |
|
|
// bar is mem64 mapped - memManager is not handling out of 64bit memory
|
| 1976 |
|
|
NUMBER_OF_MEM64_BARS = NUMBER_OF_MEM64_BARS + 1;
|
| 1977 |
|
|
|
| 1978 |
|
|
if (pio_check_design && (NUMBER_OF_MEM64_BARS > 1)) begin
|
| 1979 |
|
|
|
| 1980 |
|
|
$display("[%t] Warning: PIO design only supports 1 MEM64 BAR. Testbench will disable BAR %x",$realtime, ii);
|
| 1981 |
|
|
BAR_INIT_P_BAR_ENABLED[ii] = 2'h0; // disable BAR
|
| 1982 |
|
|
|
| 1983 |
|
|
end
|
| 1984 |
|
|
|
| 1985 |
|
|
else BAR_INIT_P_BAR_ENABLED[ii] = 2'h3; // bar is mem64 mapped
|
| 1986 |
|
|
|
| 1987 |
|
|
|
| 1988 |
|
|
if ( (BAR_INIT_P_BAR_RANGE[ii] & 32'hFFFF_FFF0) == 32'h0000_0000) begin
|
| 1989 |
|
|
|
| 1990 |
|
|
// Mem64 space has range larger than 2 Gigabytes
|
| 1991 |
|
|
|
| 1992 |
|
|
// calculate where the next BAR should start based on the BAR's range
|
| 1993 |
|
|
BAR_INIT_TEMP = BAR_INIT_P_MEM64_HI_START & BAR_INIT_P_BAR_RANGE[ii+1];
|
| 1994 |
|
|
|
| 1995 |
|
|
if (BAR_INIT_TEMP < BAR_INIT_P_MEM64_HI_START) begin
|
| 1996 |
|
|
|
| 1997 |
|
|
// Current MEM32_START is NOT correct start for new base
|
| 1998 |
|
|
BAR_INIT_P_BAR[ii+1] = BAR_INIT_TEMP + FNC_CONVERT_RANGE_TO_SIZE_HI32(ii+1);
|
| 1999 |
|
|
BAR_INIT_P_BAR[ii] = 32'h0000_0000;
|
| 2000 |
|
|
BAR_INIT_P_MEM64_HI_START = BAR_INIT_P_BAR[ii+1] + FNC_CONVERT_RANGE_TO_SIZE_HI32(ii+1);
|
| 2001 |
|
|
BAR_INIT_P_MEM64_LO_START = 32'h0000_0000;
|
| 2002 |
|
|
|
| 2003 |
|
|
end
|
| 2004 |
|
|
else begin
|
| 2005 |
|
|
|
| 2006 |
|
|
// Initial BAR case and Current MEM32_START is correct start for new base
|
| 2007 |
|
|
BAR_INIT_P_BAR[ii] = 32'h0000_0000;
|
| 2008 |
|
|
BAR_INIT_P_BAR[ii+1] = BAR_INIT_P_MEM64_HI_START;
|
| 2009 |
|
|
BAR_INIT_P_MEM64_HI_START = BAR_INIT_P_MEM64_HI_START + FNC_CONVERT_RANGE_TO_SIZE_HI32(ii+1);
|
| 2010 |
|
|
|
| 2011 |
|
|
end
|
| 2012 |
|
|
|
| 2013 |
|
|
end
|
| 2014 |
|
|
else begin
|
| 2015 |
|
|
|
| 2016 |
|
|
// Mem64 space has range less than/equal 2 Gigabytes
|
| 2017 |
|
|
|
| 2018 |
|
|
// calculate where the next BAR should start based on the BAR's range
|
| 2019 |
|
|
BAR_INIT_TEMP = BAR_INIT_P_MEM64_LO_START & (BAR_INIT_P_BAR_RANGE[ii] & 32'hffff_fff0);
|
| 2020 |
|
|
|
| 2021 |
|
|
if (BAR_INIT_TEMP < BAR_INIT_P_MEM64_LO_START) begin
|
| 2022 |
|
|
|
| 2023 |
|
|
// Current MEM32_START is NOT correct start for new base
|
| 2024 |
|
|
BAR_INIT_P_BAR[ii] = BAR_INIT_TEMP + FNC_CONVERT_RANGE_TO_SIZE_32(ii);
|
| 2025 |
|
|
BAR_INIT_P_BAR[ii+1] = BAR_INIT_P_MEM64_HI_START;
|
| 2026 |
|
|
BAR_INIT_P_MEM64_LO_START = BAR_INIT_P_BAR[ii] + FNC_CONVERT_RANGE_TO_SIZE_32(ii);
|
| 2027 |
|
|
|
| 2028 |
|
|
end
|
| 2029 |
|
|
else begin
|
| 2030 |
|
|
|
| 2031 |
|
|
// Initial BAR case and Current MEM32_START is correct start for new base
|
| 2032 |
|
|
BAR_INIT_P_BAR[ii] = BAR_INIT_P_MEM64_LO_START;
|
| 2033 |
|
|
BAR_INIT_P_BAR[ii+1] = BAR_INIT_P_MEM64_HI_START;
|
| 2034 |
|
|
BAR_INIT_P_MEM64_LO_START = BAR_INIT_P_MEM64_LO_START + FNC_CONVERT_RANGE_TO_SIZE_32(ii);
|
| 2035 |
|
|
|
| 2036 |
|
|
end
|
| 2037 |
|
|
|
| 2038 |
|
|
end
|
| 2039 |
|
|
|
| 2040 |
|
|
// skip over the next bar since it is being used by the 64bit bar
|
| 2041 |
|
|
ii = ii + 1;
|
| 2042 |
|
|
|
| 2043 |
|
|
end
|
| 2044 |
|
|
else begin
|
| 2045 |
|
|
|
| 2046 |
|
|
if ( (ii != 6) || ((ii == 6) && (BAR_INIT_P_BAR_RANGE[ii] & 32'h0000_0001)) ) begin
|
| 2047 |
|
|
// handling general mem32 case and erom case
|
| 2048 |
|
|
|
| 2049 |
|
|
// bar is mem32 mapped
|
| 2050 |
|
|
if (ii != 6) begin
|
| 2051 |
|
|
|
| 2052 |
|
|
NUMBER_OF_MEM32_BARS = NUMBER_OF_MEM32_BARS + 1; // not counting erom space
|
| 2053 |
|
|
|
| 2054 |
|
|
if (pio_check_design && (NUMBER_OF_MEM32_BARS > 1)) begin
|
| 2055 |
|
|
|
| 2056 |
|
|
// PIO design only supports 1 general purpose MEM32 BAR (not including EROM).
|
| 2057 |
|
|
$display("[%t] Warning: PIO design only supports 1 MEM32 BAR. Testbench will disable BAR %x",$realtime, ii);
|
| 2058 |
|
|
BAR_INIT_P_BAR_ENABLED[ii] = 2'h0; // disable BAR
|
| 2059 |
|
|
|
| 2060 |
|
|
end
|
| 2061 |
|
|
|
| 2062 |
|
|
else BAR_INIT_P_BAR_ENABLED[ii] = 2'h2; // bar is mem32 mapped
|
| 2063 |
|
|
|
| 2064 |
|
|
end
|
| 2065 |
|
|
|
| 2066 |
|
|
else BAR_INIT_P_BAR_ENABLED[ii] = 2'h2; // erom bar is mem32 mapped
|
| 2067 |
|
|
|
| 2068 |
|
|
if (!OUT_OF_LO_MEM) begin
|
| 2069 |
|
|
|
| 2070 |
|
|
// We need to calculate where the next BAR should start based on the BAR's range
|
| 2071 |
|
|
BAR_INIT_TEMP = BAR_INIT_P_MEM32_START & {1'b1,(BAR_INIT_P_BAR_RANGE[ii] & 32'hffff_fff0)};
|
| 2072 |
|
|
|
| 2073 |
|
|
if (BAR_INIT_TEMP < BAR_INIT_P_MEM32_START) begin
|
| 2074 |
|
|
|
| 2075 |
|
|
// Current MEM32_START is NOT correct start for new base
|
| 2076 |
|
|
BAR_INIT_P_BAR[ii] = BAR_INIT_TEMP + FNC_CONVERT_RANGE_TO_SIZE_32(ii);
|
| 2077 |
|
|
BAR_INIT_P_MEM32_START = BAR_INIT_P_BAR[ii] + FNC_CONVERT_RANGE_TO_SIZE_32(ii);
|
| 2078 |
|
|
|
| 2079 |
|
|
end
|
| 2080 |
|
|
else begin
|
| 2081 |
|
|
|
| 2082 |
|
|
// Initial BAR case and Current MEM32_START is correct start for new base
|
| 2083 |
|
|
BAR_INIT_P_BAR[ii] = BAR_INIT_P_MEM32_START;
|
| 2084 |
|
|
BAR_INIT_P_MEM32_START = BAR_INIT_P_MEM32_START + FNC_CONVERT_RANGE_TO_SIZE_32(ii);
|
| 2085 |
|
|
|
| 2086 |
|
|
end
|
| 2087 |
|
|
|
| 2088 |
|
|
|
| 2089 |
|
|
if (ii == 6) begin
|
| 2090 |
|
|
|
| 2091 |
|
|
// make sure to set enable bit if we are mapping the erom space
|
| 2092 |
|
|
|
| 2093 |
|
|
BAR_INIT_P_BAR[ii] = BAR_INIT_P_BAR[ii] | 33'h1;
|
| 2094 |
|
|
|
| 2095 |
|
|
|
| 2096 |
|
|
end
|
| 2097 |
|
|
|
| 2098 |
|
|
|
| 2099 |
|
|
OUT_OF_LO_MEM = BAR_INIT_P_BAR[ii][32];
|
| 2100 |
|
|
|
| 2101 |
|
|
if (OUT_OF_LO_MEM) begin
|
| 2102 |
|
|
|
| 2103 |
|
|
$display("\tOut of PCI EXPRESS MEMORY 32 SPACE due to BAR %x", ii);
|
| 2104 |
|
|
|
| 2105 |
|
|
end
|
| 2106 |
|
|
|
| 2107 |
|
|
end
|
| 2108 |
|
|
else begin
|
| 2109 |
|
|
|
| 2110 |
|
|
$display("\tOut of PCI EXPRESS MEMORY 32 SPACE due to BAR %x", ii);
|
| 2111 |
|
|
|
| 2112 |
|
|
end
|
| 2113 |
|
|
|
| 2114 |
|
|
end
|
| 2115 |
|
|
|
| 2116 |
|
|
end
|
| 2117 |
|
|
|
| 2118 |
|
|
end
|
| 2119 |
|
|
|
| 2120 |
|
|
end
|
| 2121 |
|
|
|
| 2122 |
|
|
end
|
| 2123 |
|
|
|
| 2124 |
|
|
|
| 2125 |
|
|
if ( (OUT_OF_IO) | (OUT_OF_LO_MEM) | (OUT_OF_HI_MEM)) begin
|
| 2126 |
|
|
TSK_DISPLAY_PCIE_MAP;
|
| 2127 |
|
|
$display("ERROR: Ending simulation: Memory Manager is out of memory/IO to allocate to PCI Express device");
|
| 2128 |
|
|
$finish;
|
| 2129 |
|
|
|
| 2130 |
|
|
end
|
| 2131 |
|
|
|
| 2132 |
|
|
|
| 2133 |
|
|
end
|
| 2134 |
|
|
|
| 2135 |
|
|
endtask // TSK_BUILD_PCIE_MAP
|
| 2136 |
|
|
|
| 2137 |
|
|
|
| 2138 |
|
|
/************************************************************
|
| 2139 |
|
|
Task : TSK_BAR_SCAN
|
| 2140 |
|
|
Inputs : None
|
| 2141 |
|
|
Outputs : None
|
| 2142 |
|
|
Description : Scans PCI core's configuration registers.
|
| 2143 |
|
|
*************************************************************/
|
| 2144 |
|
|
|
| 2145 |
|
|
task TSK_BAR_SCAN;
|
| 2146 |
|
|
begin
|
| 2147 |
|
|
|
| 2148 |
|
|
//--------------------------------------------------------------------------
|
| 2149 |
|
|
// Write PCI_MASK to bar's space via PCIe fabric interface to find range
|
| 2150 |
|
|
//--------------------------------------------------------------------------
|
| 2151 |
|
|
|
| 2152 |
|
|
P_ADDRESS_MASK = 32'hffff_ffff;
|
| 2153 |
|
|
DEFAULT_TAG = 0;
|
| 2154 |
|
|
DEFAULT_TC = 0;
|
| 2155 |
|
|
|
| 2156 |
|
|
|
| 2157 |
|
|
$display("[%t] : Inspecting Core Configuration Space...", $realtime);
|
| 2158 |
|
|
|
| 2159 |
|
|
// Determine Range for BAR0
|
| 2160 |
|
|
|
| 2161 |
|
|
TSK_TX_TYPE0_CONFIGURATION_WRITE(DEFAULT_TAG, 12'h10, P_ADDRESS_MASK, 4'hF);
|
| 2162 |
|
|
DEFAULT_TAG = DEFAULT_TAG + 1;
|
| 2163 |
|
|
TSK_TX_CLK_EAT(100);
|
| 2164 |
|
|
|
| 2165 |
|
|
// Read BAR0 Range
|
| 2166 |
|
|
|
| 2167 |
|
|
TSK_TX_TYPE0_CONFIGURATION_READ(DEFAULT_TAG, 12'h10, 4'hF);
|
| 2168 |
|
|
DEFAULT_TAG = DEFAULT_TAG + 1;
|
| 2169 |
|
|
TSK_WAIT_FOR_READ_DATA;
|
| 2170 |
|
|
BAR_INIT_P_BAR_RANGE[0] = P_READ_DATA;
|
| 2171 |
|
|
|
| 2172 |
|
|
|
| 2173 |
|
|
// Determine Range for BAR1
|
| 2174 |
|
|
|
| 2175 |
|
|
TSK_TX_TYPE0_CONFIGURATION_WRITE(DEFAULT_TAG, 12'h14, P_ADDRESS_MASK, 4'hF);
|
| 2176 |
|
|
DEFAULT_TAG = DEFAULT_TAG + 1;
|
| 2177 |
|
|
TSK_TX_CLK_EAT(100);
|
| 2178 |
|
|
|
| 2179 |
|
|
// Read BAR1 Range
|
| 2180 |
|
|
|
| 2181 |
|
|
TSK_TX_TYPE0_CONFIGURATION_READ(DEFAULT_TAG, 12'h14, 4'hF);
|
| 2182 |
|
|
DEFAULT_TAG = DEFAULT_TAG + 1;
|
| 2183 |
|
|
TSK_WAIT_FOR_READ_DATA;
|
| 2184 |
|
|
BAR_INIT_P_BAR_RANGE[1] = P_READ_DATA;
|
| 2185 |
|
|
|
| 2186 |
|
|
|
| 2187 |
|
|
// Determine Range for BAR2
|
| 2188 |
|
|
|
| 2189 |
|
|
TSK_TX_TYPE0_CONFIGURATION_WRITE(DEFAULT_TAG, 12'h18, P_ADDRESS_MASK, 4'hF);
|
| 2190 |
|
|
DEFAULT_TAG = DEFAULT_TAG + 1;
|
| 2191 |
|
|
TSK_TX_CLK_EAT(100);
|
| 2192 |
|
|
|
| 2193 |
|
|
|
| 2194 |
|
|
// Read BAR2 Range
|
| 2195 |
|
|
|
| 2196 |
|
|
TSK_TX_TYPE0_CONFIGURATION_READ(DEFAULT_TAG, 12'h18, 4'hF);
|
| 2197 |
|
|
DEFAULT_TAG = DEFAULT_TAG + 1;
|
| 2198 |
|
|
TSK_WAIT_FOR_READ_DATA;
|
| 2199 |
|
|
BAR_INIT_P_BAR_RANGE[2] = P_READ_DATA;
|
| 2200 |
|
|
|
| 2201 |
|
|
|
| 2202 |
|
|
// Determine Range for BAR3
|
| 2203 |
|
|
|
| 2204 |
|
|
TSK_TX_TYPE0_CONFIGURATION_WRITE(DEFAULT_TAG, 12'h1C, P_ADDRESS_MASK, 4'hF);
|
| 2205 |
|
|
DEFAULT_TAG = DEFAULT_TAG + 1;
|
| 2206 |
|
|
TSK_TX_CLK_EAT(100);
|
| 2207 |
|
|
|
| 2208 |
|
|
// Read BAR3 Range
|
| 2209 |
|
|
|
| 2210 |
|
|
TSK_TX_TYPE0_CONFIGURATION_READ(DEFAULT_TAG, 12'h1C, 4'hF);
|
| 2211 |
|
|
DEFAULT_TAG = DEFAULT_TAG + 1;
|
| 2212 |
|
|
TSK_WAIT_FOR_READ_DATA;
|
| 2213 |
|
|
BAR_INIT_P_BAR_RANGE[3] = P_READ_DATA;
|
| 2214 |
|
|
|
| 2215 |
|
|
|
| 2216 |
|
|
// Determine Range for BAR4
|
| 2217 |
|
|
|
| 2218 |
|
|
TSK_TX_TYPE0_CONFIGURATION_WRITE(DEFAULT_TAG, 12'h20, P_ADDRESS_MASK, 4'hF);
|
| 2219 |
|
|
DEFAULT_TAG = DEFAULT_TAG + 1;
|
| 2220 |
|
|
TSK_TX_CLK_EAT(100);
|
| 2221 |
|
|
|
| 2222 |
|
|
// Read BAR4 Range
|
| 2223 |
|
|
|
| 2224 |
|
|
TSK_TX_TYPE0_CONFIGURATION_READ(DEFAULT_TAG, 12'h20, 4'hF);
|
| 2225 |
|
|
DEFAULT_TAG = DEFAULT_TAG + 1;
|
| 2226 |
|
|
TSK_WAIT_FOR_READ_DATA;
|
| 2227 |
|
|
BAR_INIT_P_BAR_RANGE[4] = P_READ_DATA;
|
| 2228 |
|
|
|
| 2229 |
|
|
|
| 2230 |
|
|
// Determine Range for BAR5
|
| 2231 |
|
|
|
| 2232 |
|
|
TSK_TX_TYPE0_CONFIGURATION_WRITE(DEFAULT_TAG, 12'h24, P_ADDRESS_MASK, 4'hF);
|
| 2233 |
|
|
DEFAULT_TAG = DEFAULT_TAG + 1;
|
| 2234 |
|
|
TSK_TX_CLK_EAT(100);
|
| 2235 |
|
|
|
| 2236 |
|
|
// Read BAR5 Range
|
| 2237 |
|
|
|
| 2238 |
|
|
TSK_TX_TYPE0_CONFIGURATION_READ(DEFAULT_TAG, 12'h24, 4'hF);
|
| 2239 |
|
|
DEFAULT_TAG = DEFAULT_TAG + 1;
|
| 2240 |
|
|
TSK_WAIT_FOR_READ_DATA;
|
| 2241 |
|
|
BAR_INIT_P_BAR_RANGE[5] = P_READ_DATA;
|
| 2242 |
|
|
|
| 2243 |
|
|
|
| 2244 |
|
|
// Determine Range for Expansion ROM BAR
|
| 2245 |
|
|
|
| 2246 |
|
|
TSK_TX_TYPE0_CONFIGURATION_WRITE(DEFAULT_TAG, 12'h30, P_ADDRESS_MASK, 4'hF);
|
| 2247 |
|
|
DEFAULT_TAG = DEFAULT_TAG + 1;
|
| 2248 |
|
|
TSK_TX_CLK_EAT(100);
|
| 2249 |
|
|
|
| 2250 |
|
|
// Read Expansion ROM BAR Range
|
| 2251 |
|
|
|
| 2252 |
|
|
TSK_TX_TYPE0_CONFIGURATION_READ(DEFAULT_TAG, 12'h30, 4'hF);
|
| 2253 |
|
|
DEFAULT_TAG = DEFAULT_TAG + 1;
|
| 2254 |
|
|
TSK_WAIT_FOR_READ_DATA;
|
| 2255 |
|
|
BAR_INIT_P_BAR_RANGE[6] = P_READ_DATA;
|
| 2256 |
|
|
|
| 2257 |
|
|
end
|
| 2258 |
|
|
endtask // TSK_BAR_SCAN
|
| 2259 |
|
|
|
| 2260 |
|
|
|
| 2261 |
|
|
/************************************************************
|
| 2262 |
|
|
Task : TSK_BAR_PROGRAM
|
| 2263 |
|
|
Inputs : None
|
| 2264 |
|
|
Outputs : None
|
| 2265 |
|
|
Description : Program's PCI core's configuration registers.
|
| 2266 |
|
|
*************************************************************/
|
| 2267 |
|
|
|
| 2268 |
|
|
task TSK_BAR_PROGRAM;
|
| 2269 |
|
|
begin
|
| 2270 |
|
|
|
| 2271 |
|
|
//--------------------------------------------------------------------------
|
| 2272 |
|
|
// Write core configuration space via PCIe fabric interface
|
| 2273 |
|
|
//--------------------------------------------------------------------------
|
| 2274 |
|
|
|
| 2275 |
|
|
DEFAULT_TAG = 0;
|
| 2276 |
|
|
P_DEV_BDF = 16'h00_0_0;
|
| 2277 |
|
|
|
| 2278 |
|
|
$display("[%t] : Setting Core Configuration Space...", $realtime);
|
| 2279 |
|
|
|
| 2280 |
|
|
// Program BAR0
|
| 2281 |
|
|
|
| 2282 |
|
|
TSK_TX_TYPE0_CONFIGURATION_WRITE(DEFAULT_TAG, 12'h10, BAR_INIT_P_BAR[0][31:0], 4'hF);
|
| 2283 |
|
|
DEFAULT_TAG = DEFAULT_TAG + 1;
|
| 2284 |
|
|
TSK_TX_CLK_EAT(100);
|
| 2285 |
|
|
|
| 2286 |
|
|
// Program BAR1
|
| 2287 |
|
|
|
| 2288 |
|
|
TSK_TX_TYPE0_CONFIGURATION_WRITE(DEFAULT_TAG, 12'h14, BAR_INIT_P_BAR[1][31:0], 4'hF);
|
| 2289 |
|
|
DEFAULT_TAG = DEFAULT_TAG + 1;
|
| 2290 |
|
|
TSK_TX_CLK_EAT(100);
|
| 2291 |
|
|
|
| 2292 |
|
|
// Program BAR2
|
| 2293 |
|
|
|
| 2294 |
|
|
TSK_TX_TYPE0_CONFIGURATION_WRITE(DEFAULT_TAG, 12'h18, BAR_INIT_P_BAR[2][31:0], 4'hF);
|
| 2295 |
|
|
DEFAULT_TAG = DEFAULT_TAG + 1;
|
| 2296 |
|
|
TSK_TX_CLK_EAT(100);
|
| 2297 |
|
|
|
| 2298 |
|
|
// Program BAR3
|
| 2299 |
|
|
|
| 2300 |
|
|
TSK_TX_TYPE0_CONFIGURATION_WRITE(DEFAULT_TAG, 12'h1C, BAR_INIT_P_BAR[3][31:0], 4'hF);
|
| 2301 |
|
|
DEFAULT_TAG = DEFAULT_TAG + 1;
|
| 2302 |
|
|
TSK_TX_CLK_EAT(100);
|
| 2303 |
|
|
|
| 2304 |
|
|
// Program BAR4
|
| 2305 |
|
|
|
| 2306 |
|
|
TSK_TX_TYPE0_CONFIGURATION_WRITE(DEFAULT_TAG, 12'h20, BAR_INIT_P_BAR[4][31:0], 4'hF);
|
| 2307 |
|
|
DEFAULT_TAG = DEFAULT_TAG + 1;
|
| 2308 |
|
|
TSK_TX_CLK_EAT(100);
|
| 2309 |
|
|
|
| 2310 |
|
|
// Program BAR5
|
| 2311 |
|
|
|
| 2312 |
|
|
TSK_TX_TYPE0_CONFIGURATION_WRITE(DEFAULT_TAG, 12'h24, BAR_INIT_P_BAR[5][31:0], 4'hF);
|
| 2313 |
|
|
DEFAULT_TAG = DEFAULT_TAG + 1;
|
| 2314 |
|
|
TSK_TX_CLK_EAT(100);
|
| 2315 |
|
|
|
| 2316 |
|
|
// Program Expansion ROM BAR
|
| 2317 |
|
|
|
| 2318 |
|
|
TSK_TX_TYPE0_CONFIGURATION_WRITE(DEFAULT_TAG, 12'h30, BAR_INIT_P_BAR[6][31:0], 4'hF);
|
| 2319 |
|
|
DEFAULT_TAG = DEFAULT_TAG + 1;
|
| 2320 |
|
|
TSK_TX_CLK_EAT(100);
|
| 2321 |
|
|
|
| 2322 |
|
|
// Program PCI Command Register
|
| 2323 |
|
|
|
| 2324 |
|
|
TSK_TX_TYPE0_CONFIGURATION_WRITE(DEFAULT_TAG, 12'h04, 32'h00000003, 4'h1);
|
| 2325 |
|
|
DEFAULT_TAG = DEFAULT_TAG + 1;
|
| 2326 |
|
|
TSK_TX_CLK_EAT(100);
|
| 2327 |
|
|
|
| 2328 |
|
|
// Program PCIe Device Control Register
|
| 2329 |
|
|
|
| 2330 |
|
|
TSK_TX_TYPE0_CONFIGURATION_WRITE(DEFAULT_TAG, 12'h60, 32'h0000005f, 4'h1);
|
| 2331 |
|
|
DEFAULT_TAG = DEFAULT_TAG + 1;
|
| 2332 |
|
|
TSK_TX_CLK_EAT(1000);
|
| 2333 |
|
|
|
| 2334 |
|
|
end
|
| 2335 |
|
|
endtask // TSK_BAR_PROGRAM
|
| 2336 |
|
|
|
| 2337 |
|
|
|
| 2338 |
|
|
/************************************************************
|
| 2339 |
|
|
Task : TSK_BAR_INIT
|
| 2340 |
|
|
Inputs : None
|
| 2341 |
|
|
Outputs : None
|
| 2342 |
|
|
Description : Initialize PCI core based on core's configuration.
|
| 2343 |
|
|
*************************************************************/
|
| 2344 |
|
|
|
| 2345 |
|
|
task TSK_BAR_INIT;
|
| 2346 |
|
|
begin
|
| 2347 |
|
|
|
| 2348 |
|
|
TSK_BAR_SCAN;
|
| 2349 |
|
|
|
| 2350 |
|
|
TSK_BUILD_PCIE_MAP;
|
| 2351 |
|
|
|
| 2352 |
|
|
TSK_DISPLAY_PCIE_MAP;
|
| 2353 |
|
|
|
| 2354 |
|
|
TSK_BAR_PROGRAM;
|
| 2355 |
|
|
|
| 2356 |
|
|
end
|
| 2357 |
|
|
endtask // TSK_BAR_INIT
|
| 2358 |
|
|
|
| 2359 |
|
|
|
| 2360 |
|
|
|
| 2361 |
|
|
/************************************************************
|
| 2362 |
|
|
Task : TSK_TX_READBACK_CONFIG
|
| 2363 |
|
|
Inputs : None
|
| 2364 |
|
|
Outputs : None
|
| 2365 |
|
|
Description : Read core configuration space via PCIe fabric interface
|
| 2366 |
|
|
*************************************************************/
|
| 2367 |
|
|
|
| 2368 |
|
|
task TSK_TX_READBACK_CONFIG;
|
| 2369 |
|
|
begin
|
| 2370 |
|
|
|
| 2371 |
|
|
|
| 2372 |
|
|
//--------------------------------------------------------------------------
|
| 2373 |
|
|
// Read core configuration space via PCIe fabric interface
|
| 2374 |
|
|
//--------------------------------------------------------------------------
|
| 2375 |
|
|
|
| 2376 |
|
|
$display("[%t] : Reading Core Configuration Space...", $realtime);
|
| 2377 |
|
|
|
| 2378 |
|
|
// Read BAR0
|
| 2379 |
|
|
|
| 2380 |
|
|
TSK_TX_TYPE0_CONFIGURATION_READ(DEFAULT_TAG, 12'h10, 4'hF);
|
| 2381 |
|
|
DEFAULT_TAG = DEFAULT_TAG + 1;
|
| 2382 |
|
|
TSK_TX_CLK_EAT(100);
|
| 2383 |
|
|
|
| 2384 |
|
|
// Read BAR1
|
| 2385 |
|
|
|
| 2386 |
|
|
TSK_TX_TYPE0_CONFIGURATION_READ(DEFAULT_TAG, 12'h14, 4'hF);
|
| 2387 |
|
|
DEFAULT_TAG = DEFAULT_TAG + 1;
|
| 2388 |
|
|
TSK_TX_CLK_EAT(100);
|
| 2389 |
|
|
|
| 2390 |
|
|
// Read BAR2
|
| 2391 |
|
|
|
| 2392 |
|
|
TSK_TX_TYPE0_CONFIGURATION_READ(DEFAULT_TAG, 12'h18, 4'hF);
|
| 2393 |
|
|
DEFAULT_TAG = DEFAULT_TAG + 1;
|
| 2394 |
|
|
TSK_TX_CLK_EAT(100);
|
| 2395 |
|
|
|
| 2396 |
|
|
// Read BAR3
|
| 2397 |
|
|
|
| 2398 |
|
|
TSK_TX_TYPE0_CONFIGURATION_READ(DEFAULT_TAG, 12'h1C, 4'hF);
|
| 2399 |
|
|
DEFAULT_TAG = DEFAULT_TAG + 1;
|
| 2400 |
|
|
TSK_TX_CLK_EAT(100);
|
| 2401 |
|
|
|
| 2402 |
|
|
// Read BAR4
|
| 2403 |
|
|
|
| 2404 |
|
|
TSK_TX_TYPE0_CONFIGURATION_READ(DEFAULT_TAG, 12'h20, 4'hF);
|
| 2405 |
|
|
DEFAULT_TAG = DEFAULT_TAG + 1;
|
| 2406 |
|
|
TSK_TX_CLK_EAT(100);
|
| 2407 |
|
|
|
| 2408 |
|
|
// Read BAR5
|
| 2409 |
|
|
|
| 2410 |
|
|
TSK_TX_TYPE0_CONFIGURATION_READ(DEFAULT_TAG, 12'h24, 4'hF);
|
| 2411 |
|
|
DEFAULT_TAG = DEFAULT_TAG + 1;
|
| 2412 |
|
|
TSK_TX_CLK_EAT(100);
|
| 2413 |
|
|
|
| 2414 |
|
|
// Read Expansion ROM BAR
|
| 2415 |
|
|
|
| 2416 |
|
|
TSK_TX_TYPE0_CONFIGURATION_READ(DEFAULT_TAG, 12'h30, 4'hF);
|
| 2417 |
|
|
DEFAULT_TAG = DEFAULT_TAG + 1;
|
| 2418 |
|
|
TSK_TX_CLK_EAT(100);
|
| 2419 |
|
|
|
| 2420 |
|
|
// Read PCI Command Register
|
| 2421 |
|
|
|
| 2422 |
|
|
TSK_TX_TYPE0_CONFIGURATION_READ(DEFAULT_TAG, 12'h04, 4'h1);
|
| 2423 |
|
|
DEFAULT_TAG = DEFAULT_TAG + 1;
|
| 2424 |
|
|
TSK_TX_CLK_EAT(100);
|
| 2425 |
|
|
|
| 2426 |
|
|
// Read PCIe Device Control Register
|
| 2427 |
|
|
|
| 2428 |
|
|
TSK_TX_TYPE0_CONFIGURATION_READ(DEFAULT_TAG, 12'h60, 4'h1);
|
| 2429 |
|
|
DEFAULT_TAG = DEFAULT_TAG + 1;
|
| 2430 |
|
|
TSK_TX_CLK_EAT(1000);
|
| 2431 |
|
|
|
| 2432 |
|
|
end
|
| 2433 |
|
|
endtask // TSK_TX_READBACK_CONFIG
|
| 2434 |
|
|
|
| 2435 |
|
|
|
| 2436 |
|
|
/************************************************************
|
| 2437 |
|
|
Task : TSK_CFG_READBACK_CONFIG
|
| 2438 |
|
|
Inputs : None
|
| 2439 |
|
|
Outputs : None
|
| 2440 |
|
|
Description : Read core configuration space via CFG interface
|
| 2441 |
|
|
*************************************************************/
|
| 2442 |
|
|
|
| 2443 |
|
|
task TSK_CFG_READBACK_CONFIG;
|
| 2444 |
|
|
begin
|
| 2445 |
|
|
|
| 2446 |
|
|
|
| 2447 |
|
|
//--------------------------------------------------------------------------
|
| 2448 |
|
|
// Read core configuration space via configuration (host) interface
|
| 2449 |
|
|
//--------------------------------------------------------------------------
|
| 2450 |
|
|
|
| 2451 |
|
|
$display("[%t] : Reading Local Configuration Space via CFG interface...", $realtime);
|
| 2452 |
|
|
|
| 2453 |
|
|
CFG_DWADDR = 10'h0;
|
| 2454 |
|
|
board.RP.cfg_usrapp.TSK_READ_CFG_DW(CFG_DWADDR);
|
| 2455 |
|
|
|
| 2456 |
|
|
CFG_DWADDR = 10'h4;
|
| 2457 |
|
|
board.RP.cfg_usrapp.TSK_READ_CFG_DW(CFG_DWADDR);
|
| 2458 |
|
|
|
| 2459 |
|
|
CFG_DWADDR = 10'h5;
|
| 2460 |
|
|
board.RP.cfg_usrapp.TSK_READ_CFG_DW(CFG_DWADDR);
|
| 2461 |
|
|
|
| 2462 |
|
|
CFG_DWADDR = 10'h6;
|
| 2463 |
|
|
board.RP.cfg_usrapp.TSK_READ_CFG_DW(CFG_DWADDR);
|
| 2464 |
|
|
|
| 2465 |
|
|
CFG_DWADDR = 10'h7;
|
| 2466 |
|
|
board.RP.cfg_usrapp.TSK_READ_CFG_DW(CFG_DWADDR);
|
| 2467 |
|
|
|
| 2468 |
|
|
CFG_DWADDR = 10'h8;
|
| 2469 |
|
|
board.RP.cfg_usrapp.TSK_READ_CFG_DW(CFG_DWADDR);
|
| 2470 |
|
|
|
| 2471 |
|
|
CFG_DWADDR = 10'h9;
|
| 2472 |
|
|
board.RP.cfg_usrapp.TSK_READ_CFG_DW(CFG_DWADDR);
|
| 2473 |
|
|
|
| 2474 |
|
|
CFG_DWADDR = 10'hc;
|
| 2475 |
|
|
board.RP.cfg_usrapp.TSK_READ_CFG_DW(CFG_DWADDR);
|
| 2476 |
|
|
|
| 2477 |
|
|
CFG_DWADDR = 10'h17;
|
| 2478 |
|
|
board.RP.cfg_usrapp.TSK_READ_CFG_DW(CFG_DWADDR);
|
| 2479 |
|
|
|
| 2480 |
|
|
CFG_DWADDR = 10'h18;
|
| 2481 |
|
|
board.RP.cfg_usrapp.TSK_READ_CFG_DW(CFG_DWADDR);
|
| 2482 |
|
|
|
| 2483 |
|
|
CFG_DWADDR = 10'h19;
|
| 2484 |
|
|
board.RP.cfg_usrapp.TSK_READ_CFG_DW(CFG_DWADDR);
|
| 2485 |
|
|
|
| 2486 |
|
|
CFG_DWADDR = 10'h1a;
|
| 2487 |
|
|
board.RP.cfg_usrapp.TSK_READ_CFG_DW(CFG_DWADDR);
|
| 2488 |
|
|
|
| 2489 |
|
|
end
|
| 2490 |
|
|
endtask // TSK_CFG_READBACK_CONFIG
|
| 2491 |
|
|
|
| 2492 |
|
|
|
| 2493 |
|
|
|
| 2494 |
|
|
/************************************************************
|
| 2495 |
|
|
Task : TSK_MEM_TEST_DATA_BUS
|
| 2496 |
|
|
Inputs : bar_index
|
| 2497 |
|
|
Outputs : None
|
| 2498 |
|
|
Description : Test the data bus wiring in a specific memory
|
| 2499 |
|
|
by executing a walking 1's test at a set address
|
| 2500 |
|
|
within that region.
|
| 2501 |
|
|
*************************************************************/
|
| 2502 |
|
|
|
| 2503 |
|
|
task TSK_MEM_TEST_DATA_BUS;
|
| 2504 |
|
|
input [2:0] bar_index;
|
| 2505 |
|
|
reg [31:0] pattern;
|
| 2506 |
|
|
reg success;
|
| 2507 |
|
|
begin
|
| 2508 |
|
|
|
| 2509 |
|
|
$display("[%t] : Performing Memory data test to address %x", $realtime, BAR_INIT_P_BAR[bar_index][31:0]);
|
| 2510 |
|
|
success = 1; // assume success
|
| 2511 |
|
|
// Perform a walking 1's test at the given address.
|
| 2512 |
|
|
for (pattern = 1; pattern != 0; pattern = pattern << 1)
|
| 2513 |
|
|
begin
|
| 2514 |
|
|
// Write the test pattern. *address = pattern;pio_memTestAddrBus_test1
|
| 2515 |
|
|
|
| 2516 |
|
|
TSK_TX_BAR_WRITE(bar_index, 32'h0, DEFAULT_TAG, DEFAULT_TC, pattern);
|
| 2517 |
|
|
TSK_TX_CLK_EAT(10);
|
| 2518 |
|
|
DEFAULT_TAG = DEFAULT_TAG + 1;
|
| 2519 |
|
|
TSK_TX_BAR_READ(bar_index, 32'h0, DEFAULT_TAG, DEFAULT_TC);
|
| 2520 |
|
|
|
| 2521 |
|
|
|
| 2522 |
|
|
TSK_WAIT_FOR_READ_DATA;
|
| 2523 |
|
|
if (P_READ_DATA != pattern)
|
| 2524 |
|
|
begin
|
| 2525 |
|
|
$display("[%t] : Data Error Mismatch, Address: %x Write Data %x != Read Data %x", $realtime,
|
| 2526 |
|
|
BAR_INIT_P_BAR[bar_index][31:0], pattern, P_READ_DATA);
|
| 2527 |
|
|
success = 0;
|
| 2528 |
|
|
$finish;
|
| 2529 |
|
|
end
|
| 2530 |
|
|
else
|
| 2531 |
|
|
begin
|
| 2532 |
|
|
$display("[%t] : Address: %x Write Data: %x successfully received", $realtime,
|
| 2533 |
|
|
BAR_INIT_P_BAR[bar_index][31:0], P_READ_DATA);
|
| 2534 |
|
|
end
|
| 2535 |
|
|
TSK_TX_CLK_EAT(10);
|
| 2536 |
|
|
DEFAULT_TAG = DEFAULT_TAG + 1;
|
| 2537 |
|
|
|
| 2538 |
|
|
end // for loop
|
| 2539 |
|
|
if (success == 1)
|
| 2540 |
|
|
$display("[%t] : TSK_MEM_TEST_DATA_BUS successfully completed", $realtime);
|
| 2541 |
|
|
else
|
| 2542 |
|
|
$display("[%t] : TSK_MEM_TEST_DATA_BUS completed with errors", $realtime);
|
| 2543 |
|
|
|
| 2544 |
|
|
end
|
| 2545 |
|
|
|
| 2546 |
|
|
endtask // TSK_MEM_TEST_DATA_BUS
|
| 2547 |
|
|
|
| 2548 |
|
|
|
| 2549 |
|
|
|
| 2550 |
|
|
/************************************************************
|
| 2551 |
|
|
Task : TSK_MEM_TEST_ADDR_BUS
|
| 2552 |
|
|
Inputs : bar_index, nBytes
|
| 2553 |
|
|
Outputs : None
|
| 2554 |
|
|
Description : Test the address bus wiring in a specific memory by
|
| 2555 |
|
|
performing a walking 1's test on the relevant bits
|
| 2556 |
|
|
of the address and checking for multiple writes/aliasing.
|
| 2557 |
|
|
This test will find single-bit address failures such as stuck
|
| 2558 |
|
|
-high, stuck-low, and shorted pins.
|
| 2559 |
|
|
|
| 2560 |
|
|
*************************************************************/
|
| 2561 |
|
|
|
| 2562 |
|
|
task TSK_MEM_TEST_ADDR_BUS;
|
| 2563 |
|
|
input [2:0] bar_index;
|
| 2564 |
|
|
input [31:0] nBytes;
|
| 2565 |
|
|
reg [31:0] pattern;
|
| 2566 |
|
|
reg [31:0] antipattern;
|
| 2567 |
|
|
reg [31:0] addressMask;
|
| 2568 |
|
|
reg [31:0] offset;
|
| 2569 |
|
|
reg [31:0] testOffset;
|
| 2570 |
|
|
reg success;
|
| 2571 |
|
|
reg stuckHi_success;
|
| 2572 |
|
|
reg stuckLo_success;
|
| 2573 |
|
|
begin
|
| 2574 |
|
|
|
| 2575 |
|
|
$display("[%t] : Performing Memory address test to address %x", $realtime, BAR_INIT_P_BAR[bar_index][31:0]);
|
| 2576 |
|
|
success = 1; // assume success
|
| 2577 |
|
|
stuckHi_success = 1;
|
| 2578 |
|
|
stuckLo_success = 1;
|
| 2579 |
|
|
|
| 2580 |
|
|
pattern = 32'hAAAAAAAA;
|
| 2581 |
|
|
antipattern = 32'h55555555;
|
| 2582 |
|
|
|
| 2583 |
|
|
// divide by 4 because the block RAMS we are testing are 32bit wide
|
| 2584 |
|
|
// and therefore the low two bits are not meaningful for addressing purposes
|
| 2585 |
|
|
// for this test.
|
| 2586 |
|
|
addressMask = (nBytes/4 - 1);
|
| 2587 |
|
|
|
| 2588 |
|
|
$display("[%t] : Checking for address bits stuck high", $realtime);
|
| 2589 |
|
|
// Write the default pattern at each of the power-of-two offsets.
|
| 2590 |
|
|
for (offset = 1; (offset & addressMask) != 0; offset = offset << 1)
|
| 2591 |
|
|
begin
|
| 2592 |
|
|
|
| 2593 |
|
|
verbose = 1;
|
| 2594 |
|
|
|
| 2595 |
|
|
// baseAddress[offset] = pattern
|
| 2596 |
|
|
TSK_TX_BAR_WRITE(bar_index, 4*offset, DEFAULT_TAG, DEFAULT_TC, pattern);
|
| 2597 |
|
|
|
| 2598 |
|
|
TSK_TX_CLK_EAT(10);
|
| 2599 |
|
|
DEFAULT_TAG = DEFAULT_TAG + 1;
|
| 2600 |
|
|
end
|
| 2601 |
|
|
|
| 2602 |
|
|
|
| 2603 |
|
|
|
| 2604 |
|
|
// Check for address bits stuck high.
|
| 2605 |
|
|
// It should be noted that since the write address and read address pins are different
|
| 2606 |
|
|
// for the block RAMs used in the PIO design, the stuck high test will only catch an error if both
|
| 2607 |
|
|
// read and write addresses are both stuck hi. Otherwise the remaining portion of the tests
|
| 2608 |
|
|
// will catch if only one of the addresses are stuck hi.
|
| 2609 |
|
|
|
| 2610 |
|
|
testOffset = 0;
|
| 2611 |
|
|
|
| 2612 |
|
|
// baseAddress[testOffset] = antipattern;
|
| 2613 |
|
|
TSK_TX_BAR_WRITE(bar_index, 4*testOffset, DEFAULT_TAG, DEFAULT_TC, antipattern);
|
| 2614 |
|
|
|
| 2615 |
|
|
|
| 2616 |
|
|
TSK_TX_CLK_EAT(10);
|
| 2617 |
|
|
DEFAULT_TAG = DEFAULT_TAG + 1;
|
| 2618 |
|
|
|
| 2619 |
|
|
|
| 2620 |
|
|
for (offset = 1; (offset & addressMask) != 0; offset = offset << 1)
|
| 2621 |
|
|
begin
|
| 2622 |
|
|
|
| 2623 |
|
|
|
| 2624 |
|
|
TSK_TX_BAR_READ(bar_index, 4*offset, DEFAULT_TAG, DEFAULT_TC);
|
| 2625 |
|
|
|
| 2626 |
|
|
TSK_WAIT_FOR_READ_DATA;
|
| 2627 |
|
|
if (P_READ_DATA != pattern)
|
| 2628 |
|
|
begin
|
| 2629 |
|
|
$display("[%t] : Error: Pattern Mismatch, Address = %x, Write Data %x != Read Data %x",
|
| 2630 |
|
|
$realtime, BAR_INIT_P_BAR[bar_index][31:0]+(4*offset), pattern, P_READ_DATA);
|
| 2631 |
|
|
stuckHi_success = 0;
|
| 2632 |
|
|
success = 0;
|
| 2633 |
|
|
$finish;
|
| 2634 |
|
|
end
|
| 2635 |
|
|
else
|
| 2636 |
|
|
begin
|
| 2637 |
|
|
$display("[%t] : Pattern Match: Address %x Data: %x successfully received",
|
| 2638 |
|
|
$realtime, BAR_INIT_P_BAR[bar_index][31:0]+(4*offset), P_READ_DATA);
|
| 2639 |
|
|
end
|
| 2640 |
|
|
TSK_TX_CLK_EAT(10);
|
| 2641 |
|
|
DEFAULT_TAG = DEFAULT_TAG + 1;
|
| 2642 |
|
|
|
| 2643 |
|
|
end
|
| 2644 |
|
|
|
| 2645 |
|
|
|
| 2646 |
|
|
if (stuckHi_success == 1)
|
| 2647 |
|
|
$display("[%t] : Stuck Hi Address Test successfully completed", $realtime);
|
| 2648 |
|
|
else
|
| 2649 |
|
|
$display("[%t] : Error: Stuck Hi Address Test failed", $realtime);
|
| 2650 |
|
|
|
| 2651 |
|
|
|
| 2652 |
|
|
$display("[%t] : Checking for address bits stuck low or shorted", $realtime);
|
| 2653 |
|
|
|
| 2654 |
|
|
//baseAddress[testOffset] = pattern;
|
| 2655 |
|
|
|
| 2656 |
|
|
TSK_TX_BAR_WRITE(bar_index, 4*testOffset, DEFAULT_TAG, DEFAULT_TC, pattern);
|
| 2657 |
|
|
|
| 2658 |
|
|
|
| 2659 |
|
|
TSK_TX_CLK_EAT(10);
|
| 2660 |
|
|
DEFAULT_TAG = DEFAULT_TAG + 1;
|
| 2661 |
|
|
|
| 2662 |
|
|
// Check for address bits stuck low or shorted.
|
| 2663 |
|
|
for (testOffset = 1; (testOffset & addressMask) != 0; testOffset = testOffset << 1)
|
| 2664 |
|
|
begin
|
| 2665 |
|
|
|
| 2666 |
|
|
//baseAddress[testOffset] = antipattern;
|
| 2667 |
|
|
TSK_TX_BAR_WRITE(bar_index, 4*testOffset, DEFAULT_TAG, DEFAULT_TC, antipattern);
|
| 2668 |
|
|
|
| 2669 |
|
|
TSK_TX_CLK_EAT(10);
|
| 2670 |
|
|
DEFAULT_TAG = DEFAULT_TAG + 1;
|
| 2671 |
|
|
|
| 2672 |
|
|
TSK_TX_BAR_READ(bar_index, 32'h0, DEFAULT_TAG, DEFAULT_TC);
|
| 2673 |
|
|
|
| 2674 |
|
|
TSK_WAIT_FOR_READ_DATA;
|
| 2675 |
|
|
if (P_READ_DATA != pattern) // if (baseAddress[0] != pattern)
|
| 2676 |
|
|
|
| 2677 |
|
|
begin
|
| 2678 |
|
|
$display("[%t] : Error: Pattern Mismatch, Address = %x, Write Data %x != Read Data %x",
|
| 2679 |
|
|
$realtime, BAR_INIT_P_BAR[bar_index][31:0]+(4*0), pattern, P_READ_DATA);
|
| 2680 |
|
|
stuckLo_success = 0;
|
| 2681 |
|
|
success = 0;
|
| 2682 |
|
|
$finish;
|
| 2683 |
|
|
end
|
| 2684 |
|
|
else
|
| 2685 |
|
|
begin
|
| 2686 |
|
|
$display("[%t] : Pattern Match: Address %x Data: %x successfully received",
|
| 2687 |
|
|
$realtime, BAR_INIT_P_BAR[bar_index][31:0]+(4*offset), P_READ_DATA);
|
| 2688 |
|
|
end
|
| 2689 |
|
|
TSK_TX_CLK_EAT(10);
|
| 2690 |
|
|
DEFAULT_TAG = DEFAULT_TAG + 1;
|
| 2691 |
|
|
|
| 2692 |
|
|
|
| 2693 |
|
|
for (offset = 1; (offset & addressMask) != 0; offset = offset << 1)
|
| 2694 |
|
|
begin
|
| 2695 |
|
|
|
| 2696 |
|
|
TSK_TX_BAR_READ(bar_index, 4*offset, DEFAULT_TAG, DEFAULT_TC);
|
| 2697 |
|
|
|
| 2698 |
|
|
TSK_WAIT_FOR_READ_DATA;
|
| 2699 |
|
|
// if ((baseAddress[offset] != pattern) && (offset != testOffset))
|
| 2700 |
|
|
if ((P_READ_DATA != pattern) && (offset != testOffset))
|
| 2701 |
|
|
begin
|
| 2702 |
|
|
$display("[%t] : Error: Pattern Mismatch, Address = %x, Write Data %x != Read Data %x",
|
| 2703 |
|
|
$realtime, BAR_INIT_P_BAR[bar_index][31:0]+(4*offset),
|
| 2704 |
|
|
pattern, P_READ_DATA);
|
| 2705 |
|
|
stuckLo_success = 0;
|
| 2706 |
|
|
success = 0;
|
| 2707 |
|
|
$finish;
|
| 2708 |
|
|
end
|
| 2709 |
|
|
else
|
| 2710 |
|
|
begin
|
| 2711 |
|
|
$display("[%t] : Pattern Match: Address %x Data: %x successfully received",
|
| 2712 |
|
|
$realtime, BAR_INIT_P_BAR[bar_index][31:0]+(4*offset),
|
| 2713 |
|
|
P_READ_DATA);
|
| 2714 |
|
|
end
|
| 2715 |
|
|
TSK_TX_CLK_EAT(10);
|
| 2716 |
|
|
DEFAULT_TAG = DEFAULT_TAG + 1;
|
| 2717 |
|
|
|
| 2718 |
|
|
end
|
| 2719 |
|
|
|
| 2720 |
|
|
// baseAddress[testOffset] = pattern;
|
| 2721 |
|
|
|
| 2722 |
|
|
|
| 2723 |
|
|
TSK_TX_BAR_WRITE(bar_index, 4*testOffset, DEFAULT_TAG, DEFAULT_TC, pattern);
|
| 2724 |
|
|
|
| 2725 |
|
|
|
| 2726 |
|
|
TSK_TX_CLK_EAT(10);
|
| 2727 |
|
|
DEFAULT_TAG = DEFAULT_TAG + 1;
|
| 2728 |
|
|
|
| 2729 |
|
|
end
|
| 2730 |
|
|
|
| 2731 |
|
|
if (stuckLo_success == 1)
|
| 2732 |
|
|
$display("[%t] : Stuck Low Address Test successfully completed", $realtime);
|
| 2733 |
|
|
else
|
| 2734 |
|
|
$display("[%t] : Error: Stuck Low Address Test failed", $realtime);
|
| 2735 |
|
|
|
| 2736 |
|
|
|
| 2737 |
|
|
if (success == 1)
|
| 2738 |
|
|
$display("[%t] : TSK_MEM_TEST_ADDR_BUS successfully completed", $realtime);
|
| 2739 |
|
|
else
|
| 2740 |
|
|
$display("[%t] : TSK_MEM_TEST_ADDR_BUS completed with errors", $realtime);
|
| 2741 |
|
|
|
| 2742 |
|
|
end
|
| 2743 |
|
|
|
| 2744 |
|
|
endtask // TSK_MEM_TEST_ADDR_BUS
|
| 2745 |
|
|
|
| 2746 |
|
|
|
| 2747 |
|
|
|
| 2748 |
|
|
/************************************************************
|
| 2749 |
|
|
Task : TSK_MEM_TEST_DEVICE
|
| 2750 |
|
|
Inputs : bar_index, nBytes
|
| 2751 |
|
|
Outputs : None
|
| 2752 |
|
|
* Description: Test the integrity of a physical memory device by
|
| 2753 |
|
|
* performing an increment/decrement test over the
|
| 2754 |
|
|
* entire region. In the process every storage bit
|
| 2755 |
|
|
* in the device is tested as a zero and a one. The
|
| 2756 |
|
|
* bar_index and the size of the region are
|
| 2757 |
|
|
* selected by the caller.
|
| 2758 |
|
|
*************************************************************/
|
| 2759 |
|
|
|
| 2760 |
|
|
task TSK_MEM_TEST_DEVICE;
|
| 2761 |
|
|
input [2:0] bar_index;
|
| 2762 |
|
|
input [31:0] nBytes;
|
| 2763 |
|
|
reg [31:0] pattern;
|
| 2764 |
|
|
reg [31:0] antipattern;
|
| 2765 |
|
|
reg [31:0] offset;
|
| 2766 |
|
|
reg [31:0] nWords;
|
| 2767 |
|
|
reg success;
|
| 2768 |
|
|
begin
|
| 2769 |
|
|
|
| 2770 |
|
|
$display("[%t] : Performing Memory device test to address %x", $realtime, BAR_INIT_P_BAR[bar_index][31:0]);
|
| 2771 |
|
|
success = 1; // assume success
|
| 2772 |
|
|
|
| 2773 |
|
|
nWords = nBytes / 4;
|
| 2774 |
|
|
|
| 2775 |
|
|
pattern = 1;
|
| 2776 |
|
|
// Fill memory with a known pattern.
|
| 2777 |
|
|
for (offset = 0; offset < nWords; offset = offset + 1)
|
| 2778 |
|
|
begin
|
| 2779 |
|
|
|
| 2780 |
|
|
verbose = 1;
|
| 2781 |
|
|
|
| 2782 |
|
|
//baseAddress[offset] = pattern;
|
| 2783 |
|
|
TSK_TX_BAR_WRITE(bar_index, 4*offset, DEFAULT_TAG, DEFAULT_TC, pattern);
|
| 2784 |
|
|
|
| 2785 |
|
|
TSK_TX_CLK_EAT(10);
|
| 2786 |
|
|
DEFAULT_TAG = DEFAULT_TAG + 1;
|
| 2787 |
|
|
pattern = pattern + 1;
|
| 2788 |
|
|
end
|
| 2789 |
|
|
|
| 2790 |
|
|
|
| 2791 |
|
|
pattern = 1;
|
| 2792 |
|
|
// Check each location and invert it for the second pass.
|
| 2793 |
|
|
for (offset = 0; offset < nWords; offset = offset + 1)
|
| 2794 |
|
|
begin
|
| 2795 |
|
|
|
| 2796 |
|
|
|
| 2797 |
|
|
TSK_TX_BAR_READ(bar_index, 4*offset, DEFAULT_TAG, DEFAULT_TC);
|
| 2798 |
|
|
|
| 2799 |
|
|
TSK_WAIT_FOR_READ_DATA;
|
| 2800 |
|
|
DEFAULT_TAG = DEFAULT_TAG + 1;
|
| 2801 |
|
|
//if (baseAddress[offset] != pattern)
|
| 2802 |
|
|
if (P_READ_DATA != pattern)
|
| 2803 |
|
|
begin
|
| 2804 |
|
|
$display("[%t] : Error: Pattern Mismatch, Address = %x, Write Data %x != Read Data %x", $realtime,
|
| 2805 |
|
|
BAR_INIT_P_BAR[bar_index][31:0]+(4*offset), pattern, P_READ_DATA);
|
| 2806 |
|
|
success = 0;
|
| 2807 |
|
|
$finish;
|
| 2808 |
|
|
end
|
| 2809 |
|
|
|
| 2810 |
|
|
|
| 2811 |
|
|
antipattern = ~pattern;
|
| 2812 |
|
|
|
| 2813 |
|
|
//baseAddress[offset] = antipattern;
|
| 2814 |
|
|
TSK_TX_BAR_WRITE(bar_index, 4*offset, DEFAULT_TAG, DEFAULT_TC, antipattern);
|
| 2815 |
|
|
|
| 2816 |
|
|
TSK_TX_CLK_EAT(10);
|
| 2817 |
|
|
DEFAULT_TAG = DEFAULT_TAG + 1;
|
| 2818 |
|
|
|
| 2819 |
|
|
|
| 2820 |
|
|
pattern = pattern + 1;
|
| 2821 |
|
|
end
|
| 2822 |
|
|
|
| 2823 |
|
|
pattern = 1;
|
| 2824 |
|
|
// Check each location for the inverted pattern
|
| 2825 |
|
|
for (offset = 0; offset < nWords; offset = offset + 1)
|
| 2826 |
|
|
begin
|
| 2827 |
|
|
antipattern = ~pattern;
|
| 2828 |
|
|
|
| 2829 |
|
|
TSK_TX_BAR_READ(bar_index, 4*offset, DEFAULT_TAG, DEFAULT_TC);
|
| 2830 |
|
|
|
| 2831 |
|
|
TSK_WAIT_FOR_READ_DATA;
|
| 2832 |
|
|
DEFAULT_TAG = DEFAULT_TAG + 1;
|
| 2833 |
|
|
//if (baseAddress[offset] != pattern)
|
| 2834 |
|
|
if (P_READ_DATA != antipattern)
|
| 2835 |
|
|
|
| 2836 |
|
|
begin
|
| 2837 |
|
|
$display("[%t] : Error: Pattern Mismatch, Address = %x, Write Data %x != Read Data %x", $realtime,
|
| 2838 |
|
|
BAR_INIT_P_BAR[bar_index][31:0]+(4*offset), pattern, P_READ_DATA);
|
| 2839 |
|
|
success = 0;
|
| 2840 |
|
|
$finish;
|
| 2841 |
|
|
end
|
| 2842 |
|
|
pattern = pattern + 1;
|
| 2843 |
|
|
end
|
| 2844 |
|
|
|
| 2845 |
|
|
if (success == 1)
|
| 2846 |
|
|
$display("[%t] : TSK_MEM_TEST_DEVICE successfully completed", $realtime);
|
| 2847 |
|
|
else
|
| 2848 |
|
|
$display("[%t] : TSK_MEM_TEST_DEVICE completed with errors", $realtime);
|
| 2849 |
|
|
|
| 2850 |
|
|
end
|
| 2851 |
|
|
|
| 2852 |
|
|
endtask // TSK_MEM_TEST_DEVICE
|
| 2853 |
|
|
|
| 2854 |
|
|
|
| 2855 |
|
|
|
| 2856 |
|
|
|
| 2857 |
|
|
/************************************************************
|
| 2858 |
|
|
Function : FNC_CONVERT_RANGE_TO_SIZE_32
|
| 2859 |
|
|
Inputs : BAR index for 32 bit BAR
|
| 2860 |
|
|
Outputs : 32 bit BAR size
|
| 2861 |
|
|
Description : Called from tx app. Note that the smallest range
|
| 2862 |
|
|
supported by this function is 16 bytes.
|
| 2863 |
|
|
*************************************************************/
|
| 2864 |
|
|
|
| 2865 |
|
|
function [31:0] FNC_CONVERT_RANGE_TO_SIZE_32;
|
| 2866 |
|
|
input [31:0] bar_index;
|
| 2867 |
|
|
reg [32:0] return_value;
|
| 2868 |
|
|
begin
|
| 2869 |
|
|
case (BAR_INIT_P_BAR_RANGE[bar_index] & 32'hFFFF_FFF0) // AND off control bits
|
| 2870 |
|
|
32'hFFFF_FFF0 : return_value = 33'h0000_0010;
|
| 2871 |
|
|
32'hFFFF_FFE0 : return_value = 33'h0000_0020;
|
| 2872 |
|
|
32'hFFFF_FFC0 : return_value = 33'h0000_0040;
|
| 2873 |
|
|
32'hFFFF_FF80 : return_value = 33'h0000_0080;
|
| 2874 |
|
|
32'hFFFF_FF00 : return_value = 33'h0000_0100;
|
| 2875 |
|
|
32'hFFFF_FE00 : return_value = 33'h0000_0200;
|
| 2876 |
|
|
32'hFFFF_FC00 : return_value = 33'h0000_0400;
|
| 2877 |
|
|
32'hFFFF_F800 : return_value = 33'h0000_0800;
|
| 2878 |
|
|
32'hFFFF_F000 : return_value = 33'h0000_1000;
|
| 2879 |
|
|
32'hFFFF_E000 : return_value = 33'h0000_2000;
|
| 2880 |
|
|
32'hFFFF_C000 : return_value = 33'h0000_4000;
|
| 2881 |
|
|
32'hFFFF_8000 : return_value = 33'h0000_8000;
|
| 2882 |
|
|
32'hFFFF_0000 : return_value = 33'h0001_0000;
|
| 2883 |
|
|
32'hFFFE_0000 : return_value = 33'h0002_0000;
|
| 2884 |
|
|
32'hFFFC_0000 : return_value = 33'h0004_0000;
|
| 2885 |
|
|
32'hFFF8_0000 : return_value = 33'h0008_0000;
|
| 2886 |
|
|
32'hFFF0_0000 : return_value = 33'h0010_0000;
|
| 2887 |
|
|
32'hFFE0_0000 : return_value = 33'h0020_0000;
|
| 2888 |
|
|
32'hFFC0_0000 : return_value = 33'h0040_0000;
|
| 2889 |
|
|
32'hFF80_0000 : return_value = 33'h0080_0000;
|
| 2890 |
|
|
32'hFF00_0000 : return_value = 33'h0100_0000;
|
| 2891 |
|
|
32'hFE00_0000 : return_value = 33'h0200_0000;
|
| 2892 |
|
|
32'hFC00_0000 : return_value = 33'h0400_0000;
|
| 2893 |
|
|
32'hF800_0000 : return_value = 33'h0800_0000;
|
| 2894 |
|
|
32'hF000_0000 : return_value = 33'h1000_0000;
|
| 2895 |
|
|
32'hE000_0000 : return_value = 33'h2000_0000;
|
| 2896 |
|
|
32'hC000_0000 : return_value = 33'h4000_0000;
|
| 2897 |
|
|
32'h8000_0000 : return_value = 33'h8000_0000;
|
| 2898 |
|
|
default : return_value = 33'h0000_0000;
|
| 2899 |
|
|
endcase
|
| 2900 |
|
|
|
| 2901 |
|
|
FNC_CONVERT_RANGE_TO_SIZE_32 = return_value;
|
| 2902 |
|
|
end
|
| 2903 |
|
|
endfunction // FNC_CONVERT_RANGE_TO_SIZE_32
|
| 2904 |
|
|
|
| 2905 |
|
|
|
| 2906 |
|
|
|
| 2907 |
|
|
/************************************************************
|
| 2908 |
|
|
Function : FNC_CONVERT_RANGE_TO_SIZE_HI32
|
| 2909 |
|
|
Inputs : BAR index for upper 32 bit BAR of 64 bit address
|
| 2910 |
|
|
Outputs : upper 32 bit BAR size
|
| 2911 |
|
|
Description : Called from tx app.
|
| 2912 |
|
|
*************************************************************/
|
| 2913 |
|
|
|
| 2914 |
|
|
function [31:0] FNC_CONVERT_RANGE_TO_SIZE_HI32;
|
| 2915 |
|
|
input [31:0] bar_index;
|
| 2916 |
|
|
reg [32:0] return_value;
|
| 2917 |
|
|
begin
|
| 2918 |
|
|
case (BAR_INIT_P_BAR_RANGE[bar_index])
|
| 2919 |
|
|
32'hFFFF_FFFF : return_value = 33'h00000_0001;
|
| 2920 |
|
|
32'hFFFF_FFFE : return_value = 33'h00000_0002;
|
| 2921 |
|
|
32'hFFFF_FFFC : return_value = 33'h00000_0004;
|
| 2922 |
|
|
32'hFFFF_FFF8 : return_value = 33'h00000_0008;
|
| 2923 |
|
|
32'hFFFF_FFF0 : return_value = 33'h00000_0010;
|
| 2924 |
|
|
32'hFFFF_FFE0 : return_value = 33'h00000_0020;
|
| 2925 |
|
|
32'hFFFF_FFC0 : return_value = 33'h00000_0040;
|
| 2926 |
|
|
32'hFFFF_FF80 : return_value = 33'h00000_0080;
|
| 2927 |
|
|
32'hFFFF_FF00 : return_value = 33'h00000_0100;
|
| 2928 |
|
|
32'hFFFF_FE00 : return_value = 33'h00000_0200;
|
| 2929 |
|
|
32'hFFFF_FC00 : return_value = 33'h00000_0400;
|
| 2930 |
|
|
32'hFFFF_F800 : return_value = 33'h00000_0800;
|
| 2931 |
|
|
32'hFFFF_F000 : return_value = 33'h00000_1000;
|
| 2932 |
|
|
32'hFFFF_E000 : return_value = 33'h00000_2000;
|
| 2933 |
|
|
32'hFFFF_C000 : return_value = 33'h00000_4000;
|
| 2934 |
|
|
32'hFFFF_8000 : return_value = 33'h00000_8000;
|
| 2935 |
|
|
32'hFFFF_0000 : return_value = 33'h00001_0000;
|
| 2936 |
|
|
32'hFFFE_0000 : return_value = 33'h00002_0000;
|
| 2937 |
|
|
32'hFFFC_0000 : return_value = 33'h00004_0000;
|
| 2938 |
|
|
32'hFFF8_0000 : return_value = 33'h00008_0000;
|
| 2939 |
|
|
32'hFFF0_0000 : return_value = 33'h00010_0000;
|
| 2940 |
|
|
32'hFFE0_0000 : return_value = 33'h00020_0000;
|
| 2941 |
|
|
32'hFFC0_0000 : return_value = 33'h00040_0000;
|
| 2942 |
|
|
32'hFF80_0000 : return_value = 33'h00080_0000;
|
| 2943 |
|
|
32'hFF00_0000 : return_value = 33'h00100_0000;
|
| 2944 |
|
|
32'hFE00_0000 : return_value = 33'h00200_0000;
|
| 2945 |
|
|
32'hFC00_0000 : return_value = 33'h00400_0000;
|
| 2946 |
|
|
32'hF800_0000 : return_value = 33'h00800_0000;
|
| 2947 |
|
|
32'hF000_0000 : return_value = 33'h01000_0000;
|
| 2948 |
|
|
32'hE000_0000 : return_value = 33'h02000_0000;
|
| 2949 |
|
|
32'hC000_0000 : return_value = 33'h04000_0000;
|
| 2950 |
|
|
32'h8000_0000 : return_value = 33'h08000_0000;
|
| 2951 |
|
|
default : return_value = 33'h00000_0000;
|
| 2952 |
|
|
endcase
|
| 2953 |
|
|
|
| 2954 |
|
|
FNC_CONVERT_RANGE_TO_SIZE_HI32 = return_value;
|
| 2955 |
|
|
end
|
| 2956 |
|
|
endfunction // FNC_CONVERT_RANGE_TO_SIZE_HI32
|
| 2957 |
|
|
|
| 2958 |
|
|
|
| 2959 |
|
|
|
| 2960 |
|
|
|
| 2961 |
|
|
endmodule // pci_exp_usrapp_tx
|
