1 |
13 |
barabba |
|
2 |
|
|
else if(testname == "sample_smoke_test0")
|
3 |
|
|
begin
|
4 |
|
|
|
5 |
|
|
|
6 |
|
|
TSK_SIMULATION_TIMEOUT(5050);
|
7 |
|
|
|
8 |
|
|
//System Initialization
|
9 |
|
|
TSK_SYSTEM_INITIALIZATION;
|
10 |
|
|
|
11 |
|
|
|
12 |
|
|
|
13 |
|
|
|
14 |
|
|
|
15 |
|
|
$display("[%t] : Expected Device/Vendor ID = %x", $realtime, DEV_VEN_ID);
|
16 |
|
|
|
17 |
|
|
//--------------------------------------------------------------------------
|
18 |
|
|
// Read core configuration space via PCIe fabric interface
|
19 |
|
|
//--------------------------------------------------------------------------
|
20 |
|
|
|
21 |
|
|
$display("[%t] : Reading from PCI/PCI-Express Configuration Register 0x00", $realtime);
|
22 |
|
|
|
23 |
|
|
TSK_TX_TYPE0_CONFIGURATION_READ(DEFAULT_TAG, 12'h0, 4'hF);
|
24 |
|
|
TSK_WAIT_FOR_READ_DATA;
|
25 |
|
|
if (P_READ_DATA != DEV_VEN_ID) begin
|
26 |
|
|
$display("[%t] : TEST FAILED --- Data Error Mismatch, Write Data %x != Read Data %x", $realtime,
|
27 |
|
|
DEV_VEN_ID, P_READ_DATA);
|
28 |
|
|
end
|
29 |
|
|
else begin
|
30 |
|
|
$display("[%t] : TEST PASSED --- Device/Vendor ID %x successfully received", $realtime, P_READ_DATA);
|
31 |
|
|
end
|
32 |
|
|
|
33 |
|
|
//--------------------------------------------------------------------------
|
34 |
|
|
// Direct Root Port to allow upstream traffic by enabling Mem, I/O and
|
35 |
|
|
// BusMstr in the command register
|
36 |
|
|
//--------------------------------------------------------------------------
|
37 |
|
|
|
38 |
|
|
board.RP.cfg_usrapp.TSK_READ_CFG_DW(32'h00000001);
|
39 |
|
|
board.RP.cfg_usrapp.TSK_WRITE_CFG_DW(32'h00000001, 32'h00000007, 4'b1110);
|
40 |
|
|
board.RP.cfg_usrapp.TSK_READ_CFG_DW(32'h00000001);
|
41 |
|
|
|
42 |
|
|
$finish;
|
43 |
|
|
end
|
44 |
|
|
|
45 |
|
|
|
46 |
|
|
else if(testname == "sample_smoke_test1")
|
47 |
|
|
begin
|
48 |
|
|
|
49 |
|
|
// This test use tlp expectation tasks.
|
50 |
|
|
|
51 |
|
|
TSK_SIMULATION_TIMEOUT(5050);
|
52 |
|
|
|
53 |
|
|
//System Initialization
|
54 |
|
|
TSK_SYSTEM_INITIALIZATION;
|
55 |
|
|
|
56 |
|
|
fork
|
57 |
|
|
begin
|
58 |
|
|
//--------------------------------------------------------------------------
|
59 |
|
|
// Read core configuration space via PCIe fabric interface
|
60 |
|
|
//--------------------------------------------------------------------------
|
61 |
|
|
|
62 |
|
|
$display("[%t] : Reading from PCI/PCI-Express Configuration Register 0x00", $realtime);
|
63 |
|
|
|
64 |
|
|
TSK_TX_TYPE0_CONFIGURATION_READ(DEFAULT_TAG, 12'h0, 4'hF);
|
65 |
|
|
DEFAULT_TAG = DEFAULT_TAG + 1;
|
66 |
|
|
TSK_TX_CLK_EAT(100);
|
67 |
|
|
end
|
68 |
|
|
//---------------------------------------------------------------------------
|
69 |
|
|
// List Rx TLP expections
|
70 |
|
|
//---------------------------------------------------------------------------
|
71 |
|
|
begin
|
72 |
|
|
test_vars[0] = 0;
|
73 |
|
|
|
74 |
|
|
$display("[%t] : Expected Device/Vendor ID = %x", $realtime, DEV_VEN_ID);
|
75 |
|
|
|
76 |
|
|
expect_cpld_payload[0] = DEV_VEN_ID[7:0];
|
77 |
|
|
expect_cpld_payload[1] = DEV_VEN_ID[15:8];
|
78 |
|
|
expect_cpld_payload[2] = DEV_VEN_ID[23:16];
|
79 |
|
|
expect_cpld_payload[3] = DEV_VEN_ID[31:24];
|
80 |
|
|
board.RP.com_usrapp.TSK_EXPECT_CPLD(
|
81 |
|
|
3'h0, //traffic_class;
|
82 |
|
|
1'b0, //td;
|
83 |
|
|
1'b0, //ep;
|
84 |
|
|
2'h0, //attr;
|
85 |
|
|
10'h1, //length;
|
86 |
|
|
16'h0000, //completer_id;
|
87 |
|
|
3'h0, //completion_status;
|
88 |
|
|
1'b0, //bcm;
|
89 |
|
|
12'h4, //byte_count;
|
90 |
|
|
16'h01a0, //requester_id;
|
91 |
|
|
8'h0, //tag;
|
92 |
|
|
7'b0, //address_low;
|
93 |
|
|
expect_status //expect_status;
|
94 |
|
|
);
|
95 |
|
|
|
96 |
|
|
if (expect_status)
|
97 |
|
|
test_vars[0] = test_vars[0] + 1;
|
98 |
|
|
end
|
99 |
|
|
join
|
100 |
|
|
|
101 |
|
|
expect_finish_check = 1;
|
102 |
|
|
|
103 |
|
|
if (test_vars[0] == 1)
|
104 |
|
|
$display("[%t] : TEST PASSED --- Finished transmission of PCI-Express TLPs", $realtime);
|
105 |
|
|
else begin
|
106 |
|
|
$display("[%t] : TEST FAILED --- Haven't Received All Expected TLPs", $realtime);
|
107 |
|
|
|
108 |
|
|
//--------------------------------------------------------------------------
|
109 |
|
|
// Direct Root Port to allow upstream traffic by enabling Mem, I/O and
|
110 |
|
|
// BusMstr in the command register
|
111 |
|
|
//--------------------------------------------------------------------------
|
112 |
|
|
|
113 |
|
|
board.RP.cfg_usrapp.TSK_READ_CFG_DW(32'h00000001);
|
114 |
|
|
board.RP.cfg_usrapp.TSK_WRITE_CFG_DW(32'h00000001, 32'h00000007, 4'b1110);
|
115 |
|
|
board.RP.cfg_usrapp.TSK_READ_CFG_DW(32'h00000001);
|
116 |
|
|
|
117 |
|
|
end
|
118 |
|
|
|
119 |
|
|
$finish;
|
120 |
|
|
end
|
121 |
|
|
|
122 |
|
|
else if(testname == "pio_writeReadBack_test0")
|
123 |
|
|
begin
|
124 |
|
|
|
125 |
|
|
// This test performs a 32 bit write to a 32 bit Memory space and performs a read back
|
126 |
|
|
|
127 |
|
|
board.RP.tx_usrapp.TSK_SIMULATION_TIMEOUT(10050);
|
128 |
|
|
|
129 |
|
|
board.RP.tx_usrapp.TSK_SYSTEM_INITIALIZATION;
|
130 |
|
|
|
131 |
|
|
board.RP.tx_usrapp.TSK_BAR_INIT;
|
132 |
|
|
|
133 |
|
|
//--------------------------------------------------------------------------
|
134 |
|
|
// Event : Testing BARs
|
135 |
|
|
//--------------------------------------------------------------------------
|
136 |
|
|
|
137 |
|
|
for (board.RP.tx_usrapp.ii = 0; board.RP.tx_usrapp.ii <= 6; board.RP.tx_usrapp.ii =
|
138 |
|
|
board.RP.tx_usrapp.ii + 1) begin
|
139 |
|
|
if (board.RP.tx_usrapp.BAR_INIT_P_BAR_ENABLED[board.RP.tx_usrapp.ii] > 2'b00) // bar is enabled
|
140 |
|
|
case(board.RP.tx_usrapp.BAR_INIT_P_BAR_ENABLED[board.RP.tx_usrapp.ii])
|
141 |
|
|
2'b01 : // IO SPACE
|
142 |
|
|
begin
|
143 |
|
|
|
144 |
|
|
$display("[%t] : Transmitting TLPs to IO Space BAR %x", $realtime, board.RP.tx_usrapp.ii);
|
145 |
|
|
|
146 |
|
|
//--------------------------------------------------------------------------
|
147 |
|
|
// Event : IO Write bit TLP
|
148 |
|
|
//--------------------------------------------------------------------------
|
149 |
|
|
|
150 |
|
|
|
151 |
|
|
|
152 |
|
|
board.RP.tx_usrapp.TSK_TX_IO_WRITE(board.RP.tx_usrapp.DEFAULT_TAG,
|
153 |
|
|
board.RP.tx_usrapp.BAR_INIT_P_BAR[board.RP.tx_usrapp.ii][31:0], 4'hF, 32'hdead_beef);
|
154 |
|
|
|
155 |
|
|
board.RP.com_usrapp.TSK_EXPECT_CPL(3'h0, 1'b0, 1'b0, 2'b0,
|
156 |
|
|
board.RP.tx_usrapp.COMPLETER_ID_CFG, 3'h0, 1'b0, 12'h4,
|
157 |
|
|
board.RP.tx_usrapp.COMPLETER_ID_CFG, board.RP.tx_usrapp.DEFAULT_TAG,
|
158 |
|
|
board.RP.tx_usrapp.BAR_INIT_P_BAR[board.RP.tx_usrapp.ii][31:0], test_vars[0]);
|
159 |
|
|
|
160 |
|
|
board.RP.tx_usrapp.TSK_TX_CLK_EAT(10);
|
161 |
|
|
board.RP.tx_usrapp.DEFAULT_TAG = board.RP.tx_usrapp.DEFAULT_TAG + 1;
|
162 |
|
|
|
163 |
|
|
//--------------------------------------------------------------------------
|
164 |
|
|
// Event : IO Read bit TLP
|
165 |
|
|
//--------------------------------------------------------------------------
|
166 |
|
|
|
167 |
|
|
|
168 |
|
|
// make sure P_READ_DATA has known initial value
|
169 |
|
|
board.RP.tx_usrapp.P_READ_DATA = 32'hffff_ffff;
|
170 |
|
|
fork
|
171 |
|
|
board.RP.tx_usrapp.TSK_TX_IO_READ(board.RP.tx_usrapp.DEFAULT_TAG,
|
172 |
|
|
board.RP.tx_usrapp.BAR_INIT_P_BAR[board.RP.tx_usrapp.ii][31:0], 4'hF);
|
173 |
|
|
board.RP.tx_usrapp.TSK_WAIT_FOR_READ_DATA;
|
174 |
|
|
join
|
175 |
|
|
if (board.RP.tx_usrapp.P_READ_DATA != 32'hdead_beef)
|
176 |
|
|
begin
|
177 |
|
|
$display("[%t] : Test FAILED --- Data Error Mismatch, Write Data %x != Read Data %x",
|
178 |
|
|
$realtime, 32'hdead_beef, board.RP.tx_usrapp.P_READ_DATA);
|
179 |
|
|
end
|
180 |
|
|
else
|
181 |
|
|
begin
|
182 |
|
|
$display("[%t] : Test PASSED --- Write Data: %x successfully received",
|
183 |
|
|
$realtime, board.RP.tx_usrapp.P_READ_DATA);
|
184 |
|
|
end
|
185 |
|
|
|
186 |
|
|
|
187 |
|
|
board.RP.tx_usrapp.TSK_TX_CLK_EAT(10);
|
188 |
|
|
board.RP.tx_usrapp.DEFAULT_TAG = board.RP.tx_usrapp.DEFAULT_TAG + 1;
|
189 |
|
|
|
190 |
|
|
|
191 |
|
|
end
|
192 |
|
|
|
193 |
|
|
2'b10 : // MEM 32 SPACE
|
194 |
|
|
begin
|
195 |
|
|
|
196 |
|
|
|
197 |
|
|
$display("[%t] : Transmitting TLPs to Memory 32 Space BAR %x", $realtime,
|
198 |
|
|
board.RP.tx_usrapp.ii);
|
199 |
|
|
|
200 |
|
|
//--------------------------------------------------------------------------
|
201 |
|
|
// Event : Memory Write 32 bit TLP
|
202 |
|
|
//--------------------------------------------------------------------------
|
203 |
|
|
|
204 |
|
|
board.RP.tx_usrapp.DATA_STORE[0] = 8'h04;
|
205 |
|
|
board.RP.tx_usrapp.DATA_STORE[1] = 8'h03;
|
206 |
|
|
board.RP.tx_usrapp.DATA_STORE[2] = 8'h02;
|
207 |
|
|
board.RP.tx_usrapp.DATA_STORE[3] = 8'h01;
|
208 |
|
|
|
209 |
|
|
board.RP.tx_usrapp.TSK_TX_MEMORY_WRITE_32(board.RP.tx_usrapp.DEFAULT_TAG,
|
210 |
|
|
board.RP.tx_usrapp.DEFAULT_TC, 10'd1,
|
211 |
|
|
board.RP.tx_usrapp.BAR_INIT_P_BAR[board.RP.tx_usrapp.ii][31:0]+8'h10, 4'h0, 4'hF, 1'b0);
|
212 |
|
|
board.RP.tx_usrapp.TSK_TX_CLK_EAT(10);
|
213 |
|
|
board.RP.tx_usrapp.DEFAULT_TAG = board.RP.tx_usrapp.DEFAULT_TAG + 1;
|
214 |
|
|
|
215 |
|
|
//--------------------------------------------------------------------------
|
216 |
|
|
// Event : Memory Read 32 bit TLP
|
217 |
|
|
//--------------------------------------------------------------------------
|
218 |
|
|
|
219 |
|
|
|
220 |
|
|
// make sure P_READ_DATA has known initial value
|
221 |
|
|
board.RP.tx_usrapp.P_READ_DATA = 32'hffff_ffff;
|
222 |
|
|
fork
|
223 |
|
|
board.RP.tx_usrapp.TSK_TX_MEMORY_READ_32(board.RP.tx_usrapp.DEFAULT_TAG,
|
224 |
|
|
board.RP.tx_usrapp.DEFAULT_TC, 10'd1,
|
225 |
|
|
board.RP.tx_usrapp.BAR_INIT_P_BAR[board.RP.tx_usrapp.ii][31:0]+8'h10, 4'h0, 4'hF);
|
226 |
|
|
board.RP.tx_usrapp.TSK_WAIT_FOR_READ_DATA;
|
227 |
|
|
join
|
228 |
|
|
if (board.RP.tx_usrapp.P_READ_DATA != {board.RP.tx_usrapp.DATA_STORE[3],
|
229 |
|
|
board.RP.tx_usrapp.DATA_STORE[2], board.RP.tx_usrapp.DATA_STORE[1],
|
230 |
|
|
board.RP.tx_usrapp.DATA_STORE[0] })
|
231 |
|
|
begin
|
232 |
|
|
$display("[%t] : Test FAILED --- Data Error Mismatch, Write Data %x != Read Data %x",
|
233 |
|
|
$realtime, {board.RP.tx_usrapp.DATA_STORE[3],board.RP.tx_usrapp.DATA_STORE[2],
|
234 |
|
|
board.RP.tx_usrapp.DATA_STORE[1],board.RP.tx_usrapp.DATA_STORE[0]},
|
235 |
|
|
board.RP.tx_usrapp.P_READ_DATA);
|
236 |
|
|
|
237 |
|
|
end
|
238 |
|
|
else
|
239 |
|
|
begin
|
240 |
|
|
$display("[%t] : Test PASSED --- Write Data: %x successfully received",
|
241 |
|
|
$realtime, board.RP.tx_usrapp.P_READ_DATA);
|
242 |
|
|
end
|
243 |
|
|
|
244 |
|
|
|
245 |
|
|
board.RP.tx_usrapp.TSK_TX_CLK_EAT(10);
|
246 |
|
|
board.RP.tx_usrapp.DEFAULT_TAG = board.RP.tx_usrapp.DEFAULT_TAG + 1;
|
247 |
|
|
|
248 |
|
|
end
|
249 |
|
|
2'b11 : // MEM 64 SPACE
|
250 |
|
|
begin
|
251 |
|
|
|
252 |
|
|
|
253 |
|
|
$display("[%t] : Transmitting TLPs to Memory 64 Space BAR %x", $realtime,
|
254 |
|
|
board.RP.tx_usrapp.ii);
|
255 |
|
|
|
256 |
|
|
|
257 |
|
|
//--------------------------------------------------------------------------
|
258 |
|
|
// Event : Memory Write 64 bit TLP
|
259 |
|
|
//--------------------------------------------------------------------------
|
260 |
|
|
|
261 |
|
|
board.RP.tx_usrapp.DATA_STORE[0] = 8'h64;
|
262 |
|
|
board.RP.tx_usrapp.DATA_STORE[1] = 8'h63;
|
263 |
|
|
board.RP.tx_usrapp.DATA_STORE[2] = 8'h62;
|
264 |
|
|
board.RP.tx_usrapp.DATA_STORE[3] = 8'h61;
|
265 |
|
|
|
266 |
|
|
board.RP.tx_usrapp.TSK_TX_MEMORY_WRITE_64(board.RP.tx_usrapp.DEFAULT_TAG,
|
267 |
|
|
board.RP.tx_usrapp.DEFAULT_TC, 10'd1,
|
268 |
|
|
{board.RP.tx_usrapp.BAR_INIT_P_BAR[board.RP.tx_usrapp.ii+1][31:0],
|
269 |
|
|
board.RP.tx_usrapp.BAR_INIT_P_BAR[board.RP.tx_usrapp.ii][31:0]+8'h20}, 4'h0, 4'hF, 1'b0);
|
270 |
|
|
board.RP.tx_usrapp.TSK_TX_CLK_EAT(10);
|
271 |
|
|
board.RP.tx_usrapp.DEFAULT_TAG = board.RP.tx_usrapp.DEFAULT_TAG + 1;
|
272 |
|
|
|
273 |
|
|
//--------------------------------------------------------------------------
|
274 |
|
|
// Event : Memory Read 64 bit TLP
|
275 |
|
|
//--------------------------------------------------------------------------
|
276 |
|
|
|
277 |
|
|
|
278 |
|
|
// make sure P_READ_DATA has known initial value
|
279 |
|
|
board.RP.tx_usrapp.P_READ_DATA = 32'hffff_ffff;
|
280 |
|
|
fork
|
281 |
|
|
board.RP.tx_usrapp.TSK_TX_MEMORY_READ_64(board.RP.tx_usrapp.DEFAULT_TAG,
|
282 |
|
|
board.RP.tx_usrapp.DEFAULT_TC, 10'd1,
|
283 |
|
|
{board.RP.tx_usrapp.BAR_INIT_P_BAR[board.RP.tx_usrapp.ii+1][31:0],
|
284 |
|
|
board.RP.tx_usrapp.BAR_INIT_P_BAR[board.RP.tx_usrapp.ii][31:0]+8'h20}, 4'h0, 4'hF);
|
285 |
|
|
board.RP.tx_usrapp.TSK_WAIT_FOR_READ_DATA;
|
286 |
|
|
join
|
287 |
|
|
if (board.RP.tx_usrapp.P_READ_DATA != {board.RP.tx_usrapp.DATA_STORE[3],
|
288 |
|
|
board.RP.tx_usrapp.DATA_STORE[2], board.RP.tx_usrapp.DATA_STORE[1],
|
289 |
|
|
board.RP.tx_usrapp.DATA_STORE[0] })
|
290 |
|
|
|
291 |
|
|
begin
|
292 |
|
|
$display("[%t] : Test FAILED --- Data Error Mismatch, Write Data %x != Read Data %x",
|
293 |
|
|
$realtime, {board.RP.tx_usrapp.DATA_STORE[3],
|
294 |
|
|
board.RP.tx_usrapp.DATA_STORE[2], board.RP.tx_usrapp.DATA_STORE[1],
|
295 |
|
|
board.RP.tx_usrapp.DATA_STORE[0]}, board.RP.tx_usrapp.P_READ_DATA);
|
296 |
|
|
|
297 |
|
|
end
|
298 |
|
|
else
|
299 |
|
|
begin
|
300 |
|
|
$display("[%t] : Test PASSED --- Write Data: %x successfully received",
|
301 |
|
|
$realtime, board.RP.tx_usrapp.P_READ_DATA);
|
302 |
|
|
end
|
303 |
|
|
|
304 |
|
|
|
305 |
|
|
board.RP.tx_usrapp.TSK_TX_CLK_EAT(10);
|
306 |
|
|
board.RP.tx_usrapp.DEFAULT_TAG = board.RP.tx_usrapp.DEFAULT_TAG + 1;
|
307 |
|
|
|
308 |
|
|
|
309 |
|
|
end
|
310 |
|
|
default : $display("Error case in usrapp_tx\n");
|
311 |
|
|
endcase
|
312 |
|
|
|
313 |
|
|
end
|
314 |
|
|
|
315 |
|
|
|
316 |
|
|
$display("[%t] : Finished transmission of PCI-Express TLPs", $realtime);
|
317 |
|
|
$finish;
|
318 |
|
|
end
|