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//-----------------------------------------------------------------------------
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//
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// (c) Copyright 2009-2011 Xilinx, Inc. All rights reserved.
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//
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// This file contains confidential and proprietary information
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// of Xilinx, Inc. and is protected under U.S. and
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// international copyright and other intellectual property
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// laws.
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//
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// DISCLAIMER
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// This disclaimer is not a license and does not grant any
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// rights to the materials distributed herewith. Except as
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// otherwise provided in a valid license issued to you by
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// Xilinx, and to the maximum extent permitted by applicable
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// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
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// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
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// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
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// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
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// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
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// (2) Xilinx shall not be liable (whether in contract or tort,
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// including negligence, or under any other theory of
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// liability) for any loss or damage of any kind or nature
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// related to, arising under or in connection with these
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// materials, including for any direct, or any indirect,
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// special, incidental, or consequential loss or damage
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// (including loss of data, profits, goodwill, or any type of
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// loss or damage suffered as a result of any action brought
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// by a third party) even if such damage or loss was
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// reasonably foreseeable or Xilinx had been advised of the
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// possibility of the same.
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//
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// CRITICAL APPLICATIONS
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// Xilinx products are not designed or intended to be fail-
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// safe, or for use in any application requiring fail-safe
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// performance, such as life-support or safety devices or
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// systems, Class III medical devices, nuclear facilities,
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// applications related to the deployment of airbags, or any
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// other applications that could lead to death, personal
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// injury, or severe property or environmental damage
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// (individually and collectively, "Critical
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// Applications"). Customer assumes the sole risk and
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// liability of any use of Xilinx products in Critical
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// Applications, subject only to applicable laws and
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// regulations governing limitations on product liability.
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//
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// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
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// PART OF THIS FILE AT ALL TIMES.
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//
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//-----------------------------------------------------------------------------
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// Project : Virtex-6 Integrated Block for PCI Express
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// File : pcie_clocking_v6.v
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// Version : 1.7
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//-- Description: Clocking module for Virtex6 PCIe Block
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//--
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//--
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//--
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//--------------------------------------------------------------------------------
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`timescale 1ns/1ns
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module pcie_clocking_v6 # (
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parameter IS_ENDPOINT = "TRUE",
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parameter CAP_LINK_WIDTH = 8, // 1 - x1 , 2 - x2 , 4 - x4 , 8 - x8
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parameter CAP_LINK_SPEED = 4'h1, // 1 - Gen1 , 2 - Gen2
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parameter REF_CLK_FREQ = 0, // 0 - 100 MHz , 1 - 125 MHz , 2 - 250 MHz
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parameter USER_CLK_FREQ = 3 // 0 - 31.25 MHz , 1 - 62.5 MHz , 2 - 125 MHz , 3 - 250 MHz , 4 - 500Mhz
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)
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(
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input wire sys_clk,
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input wire gt_pll_lock,
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input wire sel_lnk_rate,
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input wire [1:0] sel_lnk_width,
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output wire sys_clk_bufg,
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output wire pipe_clk,
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output wire user_clk,
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output wire block_clk,
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output wire drp_clk,
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output wire clock_locked
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);
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parameter TCQ = 1;
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wire mmcm_locked;
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wire mmcm_clkfbin;
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wire mmcm_clkfbout;
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wire mmcm_reset;
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wire clk_500;
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wire clk_250;
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wire clk_125;
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wire user_clk_prebuf;
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wire sel_lnk_rate_d;
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reg [1:0] reg_clock_locked = 2'b11;
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// MMCM Configuration
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localparam mmcm_clockin_period = (REF_CLK_FREQ == 0) ? 10 :
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(REF_CLK_FREQ == 1) ? 8 :
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(REF_CLK_FREQ == 2) ? 4 : 0;
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localparam mmcm_clockfb_mult = (REF_CLK_FREQ == 0) ? 10 :
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(REF_CLK_FREQ == 1) ? 8 :
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(REF_CLK_FREQ == 2) ? 8 : 0;
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localparam mmcm_divclk_divide = (REF_CLK_FREQ == 0) ? 1 :
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(REF_CLK_FREQ == 1) ? 1 :
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(REF_CLK_FREQ == 2) ? 2 : 0;
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localparam mmcm_clock0_div = 4;
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localparam mmcm_clock1_div = 8;
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localparam mmcm_clock2_div = ((CAP_LINK_WIDTH == 6'h01) && (CAP_LINK_SPEED == 4'h1) && (USER_CLK_FREQ == 0)) ? 32 :
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((CAP_LINK_WIDTH == 6'h01) && (CAP_LINK_SPEED == 4'h1) && (USER_CLK_FREQ == 1)) ? 16 :
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((CAP_LINK_WIDTH == 6'h01) && (CAP_LINK_SPEED == 4'h2) && (USER_CLK_FREQ == 1)) ? 16 :
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((CAP_LINK_WIDTH == 6'h02) && (CAP_LINK_SPEED == 4'h1) && (USER_CLK_FREQ == 1)) ? 16 : 2;
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localparam mmcm_clock3_div = 2;
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// MMCM Reset
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assign mmcm_reset = 1'b0;
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generate
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// PIPE Clock BUFG.
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if (CAP_LINK_SPEED == 4'h1) begin : GEN1_LINK
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BUFG pipe_clk_bufg (.O(pipe_clk),.I(clk_125));
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end else if (CAP_LINK_SPEED == 4'h2) begin : GEN2_LINK
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SRL16E #(.INIT(0)) sel_lnk_rate_delay (.Q(sel_lnk_rate_d),
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.D(sel_lnk_rate), .CLK(pipe_clk),.CE(clock_locked), .A3(1'b1),.A2(1'b1),.A1(1'b1),.A0(1'b1));
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BUFGMUX pipe_clk_bufgmux (.O(pipe_clk), .I0(clk_125),.I1(clk_250),.S(sel_lnk_rate_d));
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end else begin : ILLEGAL_LINK_SPEED
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//$display("Confiuration Error : CAP_LINK_SPEED = %d, must be either 1 or 2.", CAP_LINK_SPEED);
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//$finish;
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end
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// User Clock BUFG.
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if ((CAP_LINK_WIDTH == 6'h01) && (CAP_LINK_SPEED == 4'h1) && (USER_CLK_FREQ == 0)) begin : x1_GEN1_31_25
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BUFG user_clk_bufg (.O(user_clk),.I(user_clk_prebuf));
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end else if ((CAP_LINK_WIDTH == 6'h01) && (CAP_LINK_SPEED == 4'h1) && (USER_CLK_FREQ == 1)) begin : x1_GEN1_62_50
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BUFG user_clk_bufg (.O(user_clk),.I(user_clk_prebuf));
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end else if ((CAP_LINK_WIDTH == 6'h01) && (CAP_LINK_SPEED == 4'h1) && (USER_CLK_FREQ == 2)) begin : x1_GEN1_125_00
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BUFG user_clk_bufg (.O(user_clk),.I(clk_125));
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end else if ((CAP_LINK_WIDTH == 6'h01) && (CAP_LINK_SPEED == 4'h1) && (USER_CLK_FREQ == 3)) begin : x1_GEN1_250_00
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BUFG user_clk_bufg (.O(user_clk),.I(clk_250));
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end else if ((CAP_LINK_WIDTH == 6'h01) && (CAP_LINK_SPEED == 4'h2) && (USER_CLK_FREQ == 1)) begin : x1_GEN2_62_50
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BUFG user_clk_bufg (.O(user_clk),.I(user_clk_prebuf));
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end else if ((CAP_LINK_WIDTH == 6'h01) && (CAP_LINK_SPEED == 4'h2) && (USER_CLK_FREQ == 2)) begin : x1_GEN2_125_00
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BUFG user_clk_bufg (.O(user_clk),.I(clk_125));
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end else if ((CAP_LINK_WIDTH == 6'h01) && (CAP_LINK_SPEED == 4'h2) && (USER_CLK_FREQ == 3)) begin : x1_GEN2_250_00
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BUFG user_clk_bufg (.O(user_clk),.I(clk_250));
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end else if ((CAP_LINK_WIDTH == 6'h02) && (CAP_LINK_SPEED == 4'h1) && (USER_CLK_FREQ == 1)) begin : x2_GEN1_62_50
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BUFG user_clk_bufg (.O(user_clk),.I(user_clk_prebuf));
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end else if ((CAP_LINK_WIDTH == 6'h02) && (CAP_LINK_SPEED == 4'h1) && (USER_CLK_FREQ == 2)) begin : x2_GEN1_125_00
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BUFG user_clk_bufg (.O(user_clk),.I(clk_125));
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end else if ((CAP_LINK_WIDTH == 6'h02) && (CAP_LINK_SPEED == 4'h1) && (USER_CLK_FREQ == 3)) begin : x2_GEN1_250_00
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BUFG user_clk_bufg (.O(user_clk),.I(clk_250));
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end else if ((CAP_LINK_WIDTH == 6'h02) && (CAP_LINK_SPEED == 4'h2) && (USER_CLK_FREQ == 2)) begin : x2_GEN2_125_00
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BUFG user_clk_bufg (.O(user_clk),.I(clk_125));
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end else if ((CAP_LINK_WIDTH == 6'h02) && (CAP_LINK_SPEED == 4'h2) && (USER_CLK_FREQ == 3)) begin : x2_GEN2_250_00
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BUFG user_clk_bufg (.O(user_clk),.I(clk_250));
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end else if ((CAP_LINK_WIDTH == 6'h04) && (CAP_LINK_SPEED == 4'h1) && (USER_CLK_FREQ == 2)) begin : x4_GEN1_125_00
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BUFG user_clk_bufg (.O(user_clk),.I(clk_125));
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end else if ((CAP_LINK_WIDTH == 6'h04) && (CAP_LINK_SPEED == 4'h1) && (USER_CLK_FREQ == 3)) begin : x4_GEN1_250_00
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BUFG user_clk_bufg (.O(user_clk),.I(clk_250));
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end else if ((CAP_LINK_WIDTH == 6'h04) && (CAP_LINK_SPEED == 4'h2) && (USER_CLK_FREQ == 3)) begin : x4_GEN2_250_00
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BUFG user_clk_bufg (.O(user_clk),.I(clk_250));
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end else if ((CAP_LINK_WIDTH == 6'h08) && (CAP_LINK_SPEED == 4'h1) && (USER_CLK_FREQ == 3)) begin : x8_GEN1_250_00
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BUFG user_clk_bufg (.O(user_clk),.I(clk_250));
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end else if ((CAP_LINK_WIDTH == 6'h08) && (CAP_LINK_SPEED == 4'h2) && (USER_CLK_FREQ == 4)) begin : x8_GEN2_250_00
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BUFG user_clk_bufg (.O(user_clk),.I(clk_250));
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BUFG block_clk_bufg (.O(block_clk),.I(clk_500));
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end else begin : ILLEGAL_CONFIGURATION
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//$display("Confiuration Error : Unsupported Link Width, Link Speed and User Clock Frequency Combination");
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//$finish;
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end
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endgenerate
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// DRP clk
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BUFG drp_clk_bufg_i (.O(drp_clk), .I(clk_125));
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// Feedback BUFG. Required for Temp Compensation
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BUFG clkfbin_bufg_i (.O(mmcm_clkfbin), .I(mmcm_clkfbout));
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// sys_clk BUFG.
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BUFG sys_clk_bufg_i (.O(sys_clk_bufg), .I(sys_clk));
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MMCM_ADV # (
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// 5 for 100 MHz , 4 for 125 MHz , 2 for 250 MHz
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.CLKFBOUT_MULT_F (mmcm_clockfb_mult),
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.DIVCLK_DIVIDE (mmcm_divclk_divide),
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.CLKFBOUT_PHASE(0),
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// 10 for 100 MHz, 4 for 250 MHz
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.CLKIN1_PERIOD (mmcm_clockin_period),
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.CLKIN2_PERIOD (mmcm_clockin_period),
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// 500 MHz / mmcm_clockx_div
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.CLKOUT0_DIVIDE_F (mmcm_clock0_div),
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.CLKOUT0_PHASE (0),
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.CLKOUT1_DIVIDE (mmcm_clock1_div),
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.CLKOUT1_PHASE (0),
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.CLKOUT2_DIVIDE (mmcm_clock2_div),
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.CLKOUT2_PHASE (0),
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.CLKOUT3_DIVIDE (mmcm_clock3_div),
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.CLKOUT3_PHASE (0)
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) mmcm_adv_i (
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.CLKFBOUT (mmcm_clkfbout),
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.CLKOUT0 (clk_250), // 250 MHz for pipe_clk
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.CLKOUT1 (clk_125), // 125 MHz for pipe_clk
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.CLKOUT2 (user_clk_prebuf), // user clk
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.CLKOUT3 (clk_500),
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.CLKOUT4 (),
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.CLKOUT5 (),
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.CLKOUT6 (),
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.DO (),
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.DRDY (),
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.CLKFBOUTB (),
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.CLKFBSTOPPED (),
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.CLKINSTOPPED (),
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.CLKOUT0B (),
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.CLKOUT1B (),
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.CLKOUT2B (),
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.CLKOUT3B (),
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.PSDONE (),
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.LOCKED (mmcm_locked),
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.CLKFBIN (mmcm_clkfbin),
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.CLKIN1 (sys_clk),
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.CLKIN2 (1'b0),
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.CLKINSEL (1'b1),
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.DADDR (7'b0),
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.DCLK (1'b0),
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.DEN (1'b0),
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.DI (16'b0),
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.DWE (1'b0),
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.PSEN (1'b0),
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.PSINCDEC (1'b0),
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.PWRDWN (1'b0),
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.PSCLK (1'b0),
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.RST (mmcm_reset)
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);
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// Synchronize MMCM locked output
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always @ (posedge pipe_clk or negedge gt_pll_lock) begin
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if (!gt_pll_lock)
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reg_clock_locked[1:0] <= #TCQ 2'b11;
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else
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reg_clock_locked[1:0] <= #TCQ {reg_clock_locked[0], 1'b0};
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end
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assign clock_locked = !reg_clock_locked[1] & mmcm_locked;
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endmodule
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