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-------------------------------------------------------------------------------
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--
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-- (c) Copyright 2009-2011 Xilinx, Inc. All rights reserved.
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--
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-- This file contains confidential and proprietary information
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-- of Xilinx, Inc. and is protected under U.S. and
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-- international copyright and other intellectual property
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-- laws.
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--
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-- DISCLAIMER
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-- This disclaimer is not a license and does not grant any
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-- rights to the materials distributed herewith. Except as
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-- otherwise provided in a valid license issued to you by
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-- Xilinx, and to the maximum extent permitted by applicable
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-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
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-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
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-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
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-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
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-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
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-- (2) Xilinx shall not be liable (whether in contract or tort,
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-- including negligence, or under any other theory of
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-- liability) for any loss or damage of any kind or nature
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-- related to, arising under or in connection with these
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-- materials, including for any direct, or any indirect,
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-- special, incidental, or consequential loss or damage
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-- (including loss of data, profits, goodwill, or any type of
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-- loss or damage suffered as a result of any action brought
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-- by a third party) even if such damage or loss was
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-- reasonably foreseeable or Xilinx had been advised of the
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-- possibility of the same.
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--
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-- CRITICAL APPLICATIONS
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-- Xilinx products are not designed or intended to be fail-
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-- safe, or for use in any application requiring fail-safe
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-- performance, such as life-support or safety devices or
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-- systems, Class III medical devices, nuclear facilities,
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-- applications related to the deployment of airbags, or any
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-- other applications that could lead to death, personal
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-- injury, or severe property or environmental damage
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-- (individually and collectively, "Critical
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-- Applications"). Customer assumes the sole risk and
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-- liability of any use of Xilinx products in Critical
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-- Applications, subject only to applicable laws and
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-- regulations governing limitations on product liability.
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--
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-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
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-- PART OF THIS FILE AT ALL TIMES.
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--
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-------------------------------------------------------------------------------
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-- Project : Virtex-6 Integrated Block for PCI Express
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-- File : pcie_app_v6.vhd
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-- Version : 1.7
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--
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-- Description: PCI Express Endpoint Core sample application design.
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--
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------------------------------------------------------------------------------
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library ieee;
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use ieee.std_logic_1164.all;
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library work;
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entity pcie_app_v6 is
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port (
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-- Common
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trn_clk : in std_logic;
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trn_reset_n : in std_logic;
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trn_lnk_up_n : in std_logic;
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-- Tx
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trn_td : out std_logic_vector(63 downto 0);
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trn_trem_n : out std_logic;
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trn_tsof_n : out std_logic;
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trn_teof_n : out std_logic;
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trn_tsrc_rdy_n : out std_logic;
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trn_tdst_rdy_n : in std_logic;
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trn_tsrc_dsc_n : out std_logic;
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trn_terrfwd_n : out std_logic;
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trn_tcfg_req_n : in std_logic;
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trn_tcfg_gnt_n : out std_logic;
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trn_terr_drop_n : in std_logic;
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trn_tbuf_av : in std_logic_vector(5 downto 0);
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trn_tstr_n : out std_logic;
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-- Rx
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trn_rd : in std_logic_vector(63 downto 0);
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trn_rrem_n : in std_logic;
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trn_rsof_n : in std_logic;
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trn_reof_n : in std_logic;
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trn_rsrc_rdy_n : in std_logic;
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trn_rsrc_dsc_n : in std_logic;
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trn_rdst_rdy_n : out std_logic;
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trn_rerrfwd_n : in std_logic;
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trn_rnp_ok_n : out std_logic;
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trn_rbar_hit_n : in std_logic_vector(6 downto 0);
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trn_fc_nph : in std_logic_vector(7 downto 0);
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trn_fc_npd : in std_logic_vector(11 downto 0);
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trn_fc_ph : in std_logic_vector(7 downto 0);
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trn_fc_pd : in std_logic_vector(11 downto 0);
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trn_fc_cplh : in std_logic_vector(7 downto 0);
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trn_fc_cpld : in std_logic_vector(11 downto 0);
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trn_fc_sel : out std_logic_vector(2 downto 0);
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-- Host (CFG) Interface
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cfg_do : in std_logic_vector(31 downto 0);
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cfg_di : out std_logic_vector(31 downto 0);
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cfg_byte_en_n : out std_logic_vector(3 downto 0);
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cfg_dwaddr : out std_logic_vector(9 downto 0);
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cfg_rd_wr_done_n : in std_logic;
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cfg_wr_en_n : out std_logic;
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cfg_rd_en_n : out std_logic;
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cfg_err_cor_n : out std_logic;
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cfg_err_ur_n : out std_logic;
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cfg_err_cpl_rdy_n : in std_logic;
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cfg_err_ecrc_n : out std_logic;
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cfg_err_cpl_timeout_n : out std_logic;
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cfg_err_cpl_abort_n : out std_logic;
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cfg_err_cpl_unexpect_n : out std_logic;
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cfg_err_posted_n : out std_logic;
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cfg_err_locked_n : out std_logic;
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cfg_interrupt_n : out std_logic;
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cfg_interrupt_rdy_n : in std_logic;
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cfg_interrupt_assert_n : out std_logic;
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cfg_interrupt_di : out std_logic_vector(7 downto 0);
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cfg_interrupt_do : in std_logic_vector(7 downto 0);
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cfg_interrupt_mmenable : in std_logic_vector(2 downto 0);
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cfg_interrupt_msienable : in std_logic;
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cfg_interrupt_msixenable : in std_logic;
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cfg_interrupt_msixfm : in std_logic;
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cfg_turnoff_ok_n : out std_logic;
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cfg_to_turnoff_n : in std_logic;
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cfg_pm_wake_n : out std_logic;
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cfg_pcie_link_state_n : in std_logic_vector(2 downto 0);
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cfg_trn_pending_n : out std_logic;
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cfg_err_tlp_cpl_header : out std_logic_vector(47 downto 0);
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cfg_bus_number : in std_logic_vector(7 downto 0);
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cfg_device_number : in std_logic_vector(4 downto 0);
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cfg_function_number : in std_logic_vector(2 downto 0);
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cfg_status : in std_logic_vector(15 downto 0);
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cfg_command : in std_logic_vector(15 downto 0);
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cfg_dstatus : in std_logic_vector(15 downto 0);
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cfg_dcommand : in std_logic_vector(15 downto 0);
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cfg_lstatus : in std_logic_vector(15 downto 0);
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cfg_lcommand : in std_logic_vector(15 downto 0);
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cfg_dcommand2 : in std_logic_vector(15 downto 0);
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pl_directed_link_change : out std_logic_vector(1 downto 0);
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pl_ltssm_state : in std_logic_vector(5 downto 0);
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pl_directed_link_width : out std_logic_vector(1 downto 0);
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pl_directed_link_speed : out std_logic;
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pl_directed_link_auton : out std_logic;
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pl_upstream_prefer_deemph : out std_logic;
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pl_sel_link_width : in std_logic_vector(1 downto 0);
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pl_sel_link_rate : in std_logic;
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pl_link_gen2_capable : in std_logic;
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pl_link_partner_gen2_supported : in std_logic;
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pl_initial_link_width : in std_logic_vector(2 downto 0);
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pl_link_upcfg_capable : in std_logic;
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pl_lane_reversal_mode : in std_logic_vector(1 downto 0);
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pl_received_hot_rst : in std_logic;
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cfg_dsn : out std_logic_vector(63 downto 0)
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);
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end pcie_app_v6;
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architecture v6_pcie of pcie_app_v6 is
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component PIO
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port (
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trn_clk : in std_logic;
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trn_reset_n : in std_logic;
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trn_lnk_up_n : in std_logic;
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trn_td : out std_logic_vector(63 downto 0);
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trn_trem_n : out std_logic_vector(7 downto 0);
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trn_tsof_n : out std_logic;
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trn_teof_n : out std_logic;
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trn_tsrc_rdy_n : out std_logic;
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trn_tsrc_dsc_n : out std_logic;
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trn_tdst_rdy_n : in std_logic;
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trn_tdst_dsc_n : in std_logic;
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trn_rd : in std_logic_vector(63 downto 0);
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trn_rrem_n : in std_logic_vector(7 downto 0);
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trn_rsof_n : in std_logic;
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trn_reof_n : in std_logic;
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trn_rsrc_rdy_n : in std_logic;
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trn_rsrc_dsc_n : in std_logic;
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trn_rbar_hit_n : in std_logic_vector(6 downto 0);
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trn_rdst_rdy_n : out std_logic;
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cfg_to_turnoff_n : in std_logic;
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cfg_turnoff_ok_n : out std_logic;
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cfg_completer_id : in std_logic_vector(15 downto 0);
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cfg_bus_mstr_enable : in std_logic);
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end component;
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-- Local wires
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signal cfg_completer_id : std_logic_vector(15 downto 0);
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signal cfg_bus_mstr_enable : std_logic;
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signal trn_trem_n_out : std_logic_vector(7 downto 0);
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signal trn_rrem_n_in : std_logic_vector(7 downto 0);
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begin
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-- Core input tie-offs
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trn_rnp_ok_n <= '0';
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trn_terrfwd_n <= '1';
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trn_fc_sel <= "000";
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trn_tcfg_gnt_n <= '0';
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trn_tstr_n <= '0';
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pl_directed_link_change <= "00";
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pl_directed_link_width <= "00";
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pl_directed_link_speed <= '0';
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pl_directed_link_auton <= '0';
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pl_upstream_prefer_deemph <= '1';
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cfg_err_cor_n <= '1';
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cfg_err_ur_n <= '1';
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cfg_err_ecrc_n <= '1';
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cfg_err_cpl_timeout_n <= '1';
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cfg_err_cpl_abort_n <= '1';
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cfg_err_cpl_unexpect_n <= '1';
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cfg_err_posted_n <= '0';
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cfg_err_locked_n <= '1';
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cfg_interrupt_n <= '1';
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cfg_interrupt_assert_n <= '0';
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cfg_interrupt_di <= X"00";
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cfg_pm_wake_n <= '1';
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cfg_trn_pending_n <= '1';
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cfg_dwaddr <= (others => '0');
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cfg_err_tlp_cpl_header <= (others => '0');
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cfg_di <= (others => '0');
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cfg_byte_en_n <= X"F"; -- 4-bit bus
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cfg_wr_en_n <= '1';
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cfg_rd_en_n <= '1';
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cfg_dsn <= X"0000000101000A35";
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cfg_completer_id <= (cfg_bus_number &
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cfg_device_number &
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cfg_function_number);
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cfg_bus_mstr_enable <= cfg_command(2);
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trn_trem_n <= '1' when (trn_trem_n_out = X"0F") else
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'0';
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trn_rrem_n_in <= X"0F" when (trn_rrem_n = '1') else
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X"00";
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-- Programmable I/O Module
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PIO_interface : PIO
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port map (
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trn_clk => trn_clk, -- I
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trn_reset_n => trn_reset_n, -- I
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trn_lnk_up_n => trn_lnk_up_n, -- I
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trn_td => trn_td, -- O (63:0)
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trn_tsof_n => trn_tsof_n,
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trn_trem_n => trn_trem_n_out,
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trn_teof_n => trn_teof_n, -- O
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trn_tsrc_rdy_n => trn_tsrc_rdy_n, -- O
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trn_tsrc_dsc_n => trn_tsrc_dsc_n, -- O
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trn_tdst_rdy_n => trn_tdst_rdy_n, -- I
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trn_tdst_dsc_n => '1', -- I
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trn_rd => trn_rd , -- I (63:0)
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trn_rrem_n => trn_rrem_n_in,
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trn_rsof_n => trn_rsof_n, -- I
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trn_reof_n => trn_reof_n, -- I
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trn_rsrc_rdy_n => trn_rsrc_rdy_n, -- I
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trn_rsrc_dsc_n => trn_rsrc_dsc_n, -- I
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trn_rbar_hit_n => trn_rbar_hit_n, -- I (6:0)
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trn_rdst_rdy_n => trn_rdst_rdy_n, -- O
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cfg_to_turnoff_n => cfg_to_turnoff_n, -- I
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cfg_turnoff_ok_n => cfg_turnoff_ok_n, -- O
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cfg_completer_id => cfg_completer_id, -- I (15:0)
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cfg_bus_mstr_enable => cfg_bus_mstr_enable -- I
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);
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end; -- pcie_app_v6
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