1 |
13 |
barabba |
-------------------------------------------------------------------------------
|
2 |
|
|
--
|
3 |
|
|
-- (c) Copyright 2009-2011 Xilinx, Inc. All rights reserved.
|
4 |
|
|
--
|
5 |
|
|
-- This file contains confidential and proprietary information
|
6 |
|
|
-- of Xilinx, Inc. and is protected under U.S. and
|
7 |
|
|
-- international copyright and other intellectual property
|
8 |
|
|
-- laws.
|
9 |
|
|
--
|
10 |
|
|
-- DISCLAIMER
|
11 |
|
|
-- This disclaimer is not a license and does not grant any
|
12 |
|
|
-- rights to the materials distributed herewith. Except as
|
13 |
|
|
-- otherwise provided in a valid license issued to you by
|
14 |
|
|
-- Xilinx, and to the maximum extent permitted by applicable
|
15 |
|
|
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
16 |
|
|
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
17 |
|
|
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
18 |
|
|
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
19 |
|
|
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
20 |
|
|
-- (2) Xilinx shall not be liable (whether in contract or tort,
|
21 |
|
|
-- including negligence, or under any other theory of
|
22 |
|
|
-- liability) for any loss or damage of any kind or nature
|
23 |
|
|
-- related to, arising under or in connection with these
|
24 |
|
|
-- materials, including for any direct, or any indirect,
|
25 |
|
|
-- special, incidental, or consequential loss or damage
|
26 |
|
|
-- (including loss of data, profits, goodwill, or any type of
|
27 |
|
|
-- loss or damage suffered as a result of any action brought
|
28 |
|
|
-- by a third party) even if such damage or loss was
|
29 |
|
|
-- reasonably foreseeable or Xilinx had been advised of the
|
30 |
|
|
-- possibility of the same.
|
31 |
|
|
--
|
32 |
|
|
-- CRITICAL APPLICATIONS
|
33 |
|
|
-- Xilinx products are not designed or intended to be fail-
|
34 |
|
|
-- safe, or for use in any application requiring fail-safe
|
35 |
|
|
-- performance, such as life-support or safety devices or
|
36 |
|
|
-- systems, Class III medical devices, nuclear facilities,
|
37 |
|
|
-- applications related to the deployment of airbags, or any
|
38 |
|
|
-- other applications that could lead to death, personal
|
39 |
|
|
-- injury, or severe property or environmental damage
|
40 |
|
|
-- (individually and collectively, "Critical
|
41 |
|
|
-- Applications"). Customer assumes the sole risk and
|
42 |
|
|
-- liability of any use of Xilinx products in Critical
|
43 |
|
|
-- Applications, subject only to applicable laws and
|
44 |
|
|
-- regulations governing limitations on product liability.
|
45 |
|
|
--
|
46 |
|
|
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
47 |
|
|
-- PART OF THIS FILE AT ALL TIMES.
|
48 |
|
|
--
|
49 |
|
|
-------------------------------------------------------------------------------
|
50 |
|
|
-- Project : Virtex-6 Integrated Block for PCI Express
|
51 |
|
|
-- File : pci_exp_usrapp_cfg.vhd
|
52 |
|
|
-- Version : 1.7
|
53 |
|
|
--
|
54 |
|
|
--------------------------------------------------------------------------------
|
55 |
|
|
|
56 |
|
|
library ieee;
|
57 |
|
|
use ieee.std_logic_1164.all;
|
58 |
|
|
use work.test_interface.all;
|
59 |
|
|
|
60 |
|
|
entity pci_exp_usrapp_cfg is
|
61 |
|
|
|
62 |
|
|
port (
|
63 |
|
|
|
64 |
|
|
cfg_do : in std_logic_vector((32 - 1) downto 0);
|
65 |
|
|
cfg_di : out std_logic_vector((32 - 1) downto 0);
|
66 |
|
|
cfg_byte_en_n : out std_logic_vector(((32/8) - 1) downto 0);
|
67 |
|
|
cfg_dwaddr : out std_logic_vector((10 - 1) downto 0);
|
68 |
|
|
cfg_wr_en_n : out std_logic;
|
69 |
|
|
cfg_rd_en_n : out std_logic;
|
70 |
|
|
cfg_rd_wr_done_n : in std_logic;
|
71 |
|
|
cfg_err_cor_n : out std_logic;
|
72 |
|
|
cfg_err_ur_n : out std_logic;
|
73 |
|
|
cfg_err_ecrc_n : out std_logic;
|
74 |
|
|
cfg_err_cpl_timeout_n : out std_logic;
|
75 |
|
|
cfg_err_cpl_abort_n : out std_logic;
|
76 |
|
|
cfg_err_cpl_unexpect_n : out std_logic;
|
77 |
|
|
cfg_err_posted_n : out std_logic;
|
78 |
|
|
cfg_err_tlp_cpl_header : out std_logic_vector(( 48 - 1) downto 0);
|
79 |
|
|
cfg_interrupt_n : out std_logic;
|
80 |
|
|
cfg_interrupt_rdy_n : in std_logic;
|
81 |
|
|
cfg_turnoff_ok_n : out std_logic;
|
82 |
|
|
cfg_to_turnoff_n : in std_logic;
|
83 |
|
|
cfg_pm_wake_n : out std_logic;
|
84 |
|
|
cfg_bus_number : in std_logic_vector((8 -1) downto 0);
|
85 |
|
|
cfg_device_number : in std_logic_vector((5 - 1) downto 0);
|
86 |
|
|
cfg_function_number : in std_logic_vector((3 - 1) downto 0);
|
87 |
|
|
cfg_status : in std_logic_vector((16 - 1) downto 0);
|
88 |
|
|
cfg_command : in std_logic_vector((16 - 1) downto 0);
|
89 |
|
|
cfg_dstatus : in std_logic_vector((16 - 1) downto 0);
|
90 |
|
|
cfg_dcommand : in std_logic_vector((16 - 1) downto 0);
|
91 |
|
|
cfg_lstatus : in std_logic_vector((16 - 1) downto 0);
|
92 |
|
|
cfg_lcommand : in std_logic_vector((16 - 1) downto 0);
|
93 |
|
|
cfg_pcie_link_state_n : in std_logic_vector((3 - 1) downto 0);
|
94 |
|
|
cfg_trn_pending_n : out std_logic;
|
95 |
|
|
|
96 |
|
|
trn_clk : in std_logic;
|
97 |
|
|
trn_reset_n : in std_logic
|
98 |
|
|
|
99 |
|
|
);
|
100 |
|
|
|
101 |
|
|
|
102 |
|
|
end pci_exp_usrapp_cfg;
|
103 |
|
|
|
104 |
|
|
architecture rtl of pci_exp_usrapp_cfg is
|
105 |
|
|
|
106 |
|
|
begin
|
107 |
|
|
|
108 |
|
|
-- Signals not used by testbench at this point
|
109 |
|
|
cfg_err_cor_n <= '1';
|
110 |
|
|
cfg_err_ur_n <= '1';
|
111 |
|
|
cfg_err_ecrc_n <= '1';
|
112 |
|
|
cfg_err_cpl_timeout_n <= '1';
|
113 |
|
|
cfg_err_cpl_abort_n <= '1';
|
114 |
|
|
cfg_err_cpl_unexpect_n <= '1';
|
115 |
|
|
cfg_err_posted_n <= '0';
|
116 |
|
|
cfg_interrupt_n <= '1';
|
117 |
|
|
cfg_turnoff_ok_n <= '1';
|
118 |
|
|
cfg_err_tlp_cpl_header <= (others => '0');
|
119 |
|
|
cfg_pm_wake_n <= '1';
|
120 |
|
|
cfg_trn_pending_n <= '0';
|
121 |
|
|
|
122 |
|
|
------------------
|
123 |
|
|
-- The following signals are driven by processes defined in
|
124 |
|
|
-- test_package and called from tests.vhd
|
125 |
|
|
------------------
|
126 |
|
|
|
127 |
|
|
-- Inputs to CFG procecces / Outputs of core
|
128 |
|
|
cfg_rdwr_int.trn_clk <= trn_clk;
|
129 |
|
|
cfg_rdwr_int.trn_reset_n <= trn_reset_n;
|
130 |
|
|
cfg_rdwr_int.cfg_rd_wr_done_n <= cfg_rd_wr_done_n;
|
131 |
|
|
cfg_rdwr_int.cfg_do <= cfg_do;
|
132 |
|
|
|
133 |
|
|
-- Outputs of CFG processes / Inputs to core
|
134 |
|
|
cfg_dwaddr <= cfg_rdwr_int.cfg_dwaddr;
|
135 |
|
|
cfg_di <= cfg_rdwr_int.cfg_di;
|
136 |
|
|
cfg_byte_en_n <= cfg_rdwr_int.cfg_byte_en_n;
|
137 |
|
|
cfg_wr_en_n <= cfg_rdwr_int.cfg_wr_en_n;
|
138 |
|
|
cfg_rd_en_n <= cfg_rdwr_int.cfg_rd_en_n;
|
139 |
|
|
|
140 |
|
|
end; -- pci_exp_usrapp_cfg
|