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//-----------------------------------------------------------------------------
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//
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// (c) Copyright 2009-2011 Xilinx, Inc. All rights reserved.
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//
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// This file contains confidential and proprietary information
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// of Xilinx, Inc. and is protected under U.S. and
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// international copyright and other intellectual property
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// laws.
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//
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// DISCLAIMER
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// This disclaimer is not a license and does not grant any
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// rights to the materials distributed herewith. Except as
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// otherwise provided in a valid license issued to you by
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// Xilinx, and to the maximum extent permitted by applicable
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// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
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// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
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// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
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// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
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// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
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// (2) Xilinx shall not be liable (whether in contract or tort,
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// including negligence, or under any other theory of
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// liability) for any loss or damage of any kind or nature
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// related to, arising under or in connection with these
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// materials, including for any direct, or any indirect,
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// special, incidental, or consequential loss or damage
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// (including loss of data, profits, goodwill, or any type of
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// loss or damage suffered as a result of any action brought
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// by a third party) even if such damage or loss was
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// reasonably foreseeable or Xilinx had been advised of the
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// possibility of the same.
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//
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// CRITICAL APPLICATIONS
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// Xilinx products are not designed or intended to be fail-
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// safe, or for use in any application requiring fail-safe
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// performance, such as life-support or safety devices or
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// systems, Class III medical devices, nuclear facilities,
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// applications related to the deployment of airbags, or any
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// other applications that could lead to death, personal
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// injury, or severe property or environmental damage
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// (individually and collectively, "Critical
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// Applications"). Customer assumes the sole risk and
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// liability of any use of Xilinx products in Critical
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// Applications, subject only to applicable laws and
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// regulations governing limitations on product liability.
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//
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// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
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// PART OF THIS FILE AT ALL TIMES.
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//
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//-----------------------------------------------------------------------------
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// Project : Virtex-6 Integrated Block for PCI Express
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// File : board_common.v
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// Version : 1.7
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//--
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//--------------------------------------------------------------------------------
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`timescale 1ns/1ns
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`define IO_TRUE 1
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`define IO_FALSE 0
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`define TX_TASKS board.RP.tx_usrapp
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// Endpoint Sys clock clock frequency 100 MHz -> half clock -> 5000 pS
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`define SYS_CLK_COR_HALF_CLK_PERIOD 5000
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// Downstrean Port Sys clock clock frequency 250 MHz -> half clock -> 2000 pS
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`define SYS_CLK_DSPORT_HALF_CLK_PERIOD 2000
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`define RX_LOG 0
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`define TX_LOG 1
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// PCI Express TLP Types constants
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`define PCI_EXP_MEM_READ32 7'b0000000
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`define PCI_EXP_IO_READ 7'b0000010
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`define PCI_EXP_CFG_READ0 7'b0000100
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`define PCI_EXP_COMPLETION_WO_DATA 7'b0001010
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`define PCI_EXP_MEM_READ64 7'b0100000
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`define PCI_EXP_MSG_NODATA 7'b0110xxx
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`define PCI_EXP_MEM_WRITE32 7'b1000000
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`define PCI_EXP_IO_WRITE 7'b1000010
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`define PCI_EXP_CFG_WRITE0 7'b1000100
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`define PCI_EXP_COMPLETION_DATA 7'b1001010
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`define PCI_EXP_MEM_WRITE64 7'b1100000
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`define PCI_EXP_MSG_DATA 7'b1110xxx
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`define TRN_RX_TIMEOUT 5000
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