1 |
13 |
barabba |
|
2 |
|
|
-------------------------------------------------------------------------------
|
3 |
|
|
--
|
4 |
|
|
-- (c) Copyright 2009-2011 Xilinx, Inc. All rights reserved.
|
5 |
|
|
--
|
6 |
|
|
-- This file contains confidential and proprietary information
|
7 |
|
|
-- of Xilinx, Inc. and is protected under U.S. and
|
8 |
|
|
-- international copyright and other intellectual property
|
9 |
|
|
-- laws.
|
10 |
|
|
--
|
11 |
|
|
-- DISCLAIMER
|
12 |
|
|
-- This disclaimer is not a license and does not grant any
|
13 |
|
|
-- rights to the materials distributed herewith. Except as
|
14 |
|
|
-- otherwise provided in a valid license issued to you by
|
15 |
|
|
-- Xilinx, and to the maximum extent permitted by applicable
|
16 |
|
|
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
17 |
|
|
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
18 |
|
|
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
19 |
|
|
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
20 |
|
|
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
21 |
|
|
-- (2) Xilinx shall not be liable (whether in contract or tort,
|
22 |
|
|
-- including negligence, or under any other theory of
|
23 |
|
|
-- liability) for any loss or damage of any kind or nature
|
24 |
|
|
-- related to, arising under or in connection with these
|
25 |
|
|
-- materials, including for any direct, or any indirect,
|
26 |
|
|
-- special, incidental, or consequential loss or damage
|
27 |
|
|
-- (including loss of data, profits, goodwill, or any type of
|
28 |
|
|
-- loss or damage suffered as a result of any action brought
|
29 |
|
|
-- by a third party) even if such damage or loss was
|
30 |
|
|
-- reasonably foreseeable or Xilinx had been advised of the
|
31 |
|
|
-- possibility of the same.
|
32 |
|
|
--
|
33 |
|
|
-- CRITICAL APPLICATIONS
|
34 |
|
|
-- Xilinx products are not designed or intended to be fail-
|
35 |
|
|
-- safe, or for use in any application requiring fail-safe
|
36 |
|
|
-- performance, such as life-support or safety devices or
|
37 |
|
|
-- systems, Class III medical devices, nuclear facilities,
|
38 |
|
|
-- applications related to the deployment of airbags, or any
|
39 |
|
|
-- other applications that could lead to death, personal
|
40 |
|
|
-- injury, or severe property or environmental damage
|
41 |
|
|
-- (individually and collectively, "Critical
|
42 |
|
|
-- Applications"). Customer assumes the sole risk and
|
43 |
|
|
-- liability of any use of Xilinx products in Critical
|
44 |
|
|
-- Applications, subject only to applicable laws and
|
45 |
|
|
-- regulations governing limitations on product liability.
|
46 |
|
|
--
|
47 |
|
|
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
48 |
|
|
-- PART OF THIS FILE AT ALL TIMES.
|
49 |
|
|
--
|
50 |
|
|
-------------------------------------------------------------------------------
|
51 |
|
|
-- Project : Virtex-6 Integrated Block for PCI Express
|
52 |
|
|
-- File : gtx_drp_chanalign_fix_3752_v6.vhd
|
53 |
|
|
-- Version : 1.7
|
54 |
|
|
---- Description: Virtex6 Workaround for deadlock due lane-lane skew Bug
|
55 |
|
|
----
|
56 |
|
|
----
|
57 |
|
|
----
|
58 |
|
|
----------------------------------------------------------------------------------
|
59 |
|
|
|
60 |
|
|
library ieee;
|
61 |
|
|
use ieee.std_logic_1164.all;
|
62 |
|
|
use ieee.std_logic_unsigned.all;
|
63 |
|
|
|
64 |
|
|
entity GTX_DRP_CHANALIGN_FIX_3752_V6 is
|
65 |
|
|
generic (
|
66 |
|
|
C_SIMULATION : integer := 0 -- Set to 1 for simulation
|
67 |
|
|
|
68 |
|
|
);
|
69 |
|
|
port (
|
70 |
|
|
dwe : out std_logic;
|
71 |
|
|
din : out std_logic_vector(15 downto 0); --THIS IS THE INPUT TO THE DRP
|
72 |
|
|
den : out std_logic;
|
73 |
|
|
daddr : out std_logic_vector(7 downto 0);
|
74 |
|
|
drpstate : out std_logic_vector(3 downto 0); --DEBUG
|
75 |
|
|
write_ts1 : in std_logic;
|
76 |
|
|
write_fts : in std_logic;
|
77 |
|
|
dout : in std_logic_vector(15 downto 0); --THIS IS THE OUTPUT OF THE DRP
|
78 |
|
|
drdy : in std_logic;
|
79 |
|
|
Reset_n : in std_logic;
|
80 |
|
|
drp_clk : in std_logic
|
81 |
|
|
);
|
82 |
|
|
end GTX_DRP_CHANALIGN_FIX_3752_V6;
|
83 |
|
|
|
84 |
|
|
architecture v6_pcie of GTX_DRP_CHANALIGN_FIX_3752_V6 is
|
85 |
|
|
|
86 |
|
|
constant TCQ : integer := 1;
|
87 |
|
|
constant DRP_IDLE_FTS : std_logic_vector(3 downto 0) := "0001";
|
88 |
|
|
constant DRP_IDLE_TS1 : std_logic_vector(3 downto 0) := "0010";
|
89 |
|
|
constant DRP_RESET : std_logic_vector(3 downto 0) := "0011";
|
90 |
|
|
constant DRP_WRITE_FTS : std_logic_vector(3 downto 0) := "0110";
|
91 |
|
|
constant DRP_WRITE_DONE_FTS : std_logic_vector(3 downto 0) := "0111";
|
92 |
|
|
constant DRP_WRITE_TS1 : std_logic_vector(3 downto 0) := "1000";
|
93 |
|
|
constant DRP_WRITE_DONE_TS1 : std_logic_vector(3 downto 0) := "1001";
|
94 |
|
|
constant DRP_COM : std_logic_vector(9 downto 0) := "0110111100";
|
95 |
|
|
constant DRP_FTS : std_logic_vector(9 downto 0) := "0100111100";
|
96 |
|
|
constant DRP_TS1 : std_logic_vector(9 downto 0) := "0001001010";
|
97 |
|
|
|
98 |
|
|
signal next_daddr : std_logic_vector(7 downto 0);
|
99 |
|
|
signal next_drpstate : std_logic_vector(3 downto 0);
|
100 |
|
|
signal write_ts1_gated : std_logic;
|
101 |
|
|
signal write_fts_gated : std_logic;
|
102 |
|
|
|
103 |
|
|
-- Declare intermediate signals for referenced outputs
|
104 |
|
|
signal daddr_v6pcie : std_logic_vector(7 downto 0);
|
105 |
|
|
signal drpstate_v6pcie : std_logic_vector(3 downto 0);
|
106 |
|
|
|
107 |
|
|
begin
|
108 |
|
|
-- Drive referenced outputs
|
109 |
|
|
daddr <= daddr_v6pcie;
|
110 |
|
|
drpstate <= drpstate_v6pcie;
|
111 |
|
|
|
112 |
|
|
process (drp_clk)
|
113 |
|
|
begin
|
114 |
|
|
if (drp_clk'event and drp_clk = '1') then
|
115 |
|
|
|
116 |
|
|
if ((not(Reset_n)) = '1') then
|
117 |
|
|
|
118 |
|
|
daddr_v6pcie <= X"08" after (TCQ)*1 ps;
|
119 |
|
|
drpstate_v6pcie <= DRP_RESET after (TCQ)*1 ps;
|
120 |
|
|
|
121 |
|
|
write_ts1_gated <= '0' after (TCQ)*1 ps;
|
122 |
|
|
write_fts_gated <= '0' after (TCQ)*1 ps;
|
123 |
|
|
|
124 |
|
|
else
|
125 |
|
|
|
126 |
|
|
daddr_v6pcie <= next_daddr after (TCQ)*1 ps;
|
127 |
|
|
drpstate_v6pcie <= next_drpstate after (TCQ)*1 ps;
|
128 |
|
|
|
129 |
|
|
write_ts1_gated <= write_ts1 after (TCQ)*1 ps;
|
130 |
|
|
write_fts_gated <= write_fts after (TCQ)*1 ps;
|
131 |
|
|
|
132 |
|
|
end if;
|
133 |
|
|
|
134 |
|
|
end if;
|
135 |
|
|
|
136 |
|
|
end process;
|
137 |
|
|
|
138 |
|
|
|
139 |
|
|
process (drpstate_v6pcie, daddr_v6pcie, drdy, write_ts1_gated, write_fts_gated)
|
140 |
|
|
begin
|
141 |
|
|
|
142 |
|
|
-- DEFAULT CONDITIONS
|
143 |
|
|
next_drpstate <= drpstate_v6pcie;
|
144 |
|
|
next_daddr <= daddr_v6pcie;
|
145 |
|
|
den <= '0';
|
146 |
|
|
din <= (others => '0');
|
147 |
|
|
dwe <= '0';
|
148 |
|
|
|
149 |
|
|
case drpstate_v6pcie is
|
150 |
|
|
|
151 |
|
|
-- RESET CONDITION, WE NEED TO READ THE TOP 6 BITS OF THE DRP REGISTER WHEN WE GET THE WRITE FTS TRIGGER
|
152 |
|
|
when DRP_RESET =>
|
153 |
|
|
next_drpstate <= DRP_WRITE_TS1;
|
154 |
|
|
next_daddr <= X"08";
|
155 |
|
|
|
156 |
|
|
-- WRITE FTS SEQUENCE
|
157 |
|
|
when DRP_WRITE_FTS =>
|
158 |
|
|
den <= '1';
|
159 |
|
|
dwe <= '1';
|
160 |
|
|
if (daddr_v6pcie = X"08") then
|
161 |
|
|
din <= X"FD3C";
|
162 |
|
|
elsif (daddr_v6pcie = X"09") then
|
163 |
|
|
din <= X"C53C";
|
164 |
|
|
elsif (daddr_v6pcie = X"0A") then
|
165 |
|
|
din <= X"FDBC";
|
166 |
|
|
elsif (daddr_v6pcie = X"0B") then
|
167 |
|
|
din <= X"853C";
|
168 |
|
|
end if;
|
169 |
|
|
next_drpstate <= DRP_WRITE_DONE_FTS;
|
170 |
|
|
|
171 |
|
|
-- WAIT FOR FTS SEQUENCE WRITE TO FINISH, ONCE WE FINISH ALL WRITES GO TO FTS IDLE
|
172 |
|
|
when DRP_WRITE_DONE_FTS =>
|
173 |
|
|
if (drdy = '1') then
|
174 |
|
|
if (daddr_v6pcie = X"0B") then
|
175 |
|
|
next_drpstate <= DRP_IDLE_FTS;
|
176 |
|
|
next_daddr <= X"08";
|
177 |
|
|
else
|
178 |
|
|
next_drpstate <= DRP_WRITE_FTS;
|
179 |
|
|
next_daddr <= daddr_v6pcie + X"01";
|
180 |
|
|
end if;
|
181 |
|
|
end if;
|
182 |
|
|
|
183 |
|
|
-- FTS IDLE: WAIT HERE UNTIL WE NEED TO WRITE TS1
|
184 |
|
|
when DRP_IDLE_FTS =>
|
185 |
|
|
if (write_ts1_gated = '1') then
|
186 |
|
|
next_drpstate <= DRP_WRITE_TS1;
|
187 |
|
|
next_daddr <= X"08";
|
188 |
|
|
end if;
|
189 |
|
|
|
190 |
|
|
-- WRITE TS1 SEQUENCE
|
191 |
|
|
when DRP_WRITE_TS1 =>
|
192 |
|
|
den <= '1';
|
193 |
|
|
dwe <= '1';
|
194 |
|
|
if (daddr_v6pcie = X"08") then
|
195 |
|
|
din <= X"FC4A";
|
196 |
|
|
elsif (daddr_v6pcie = X"09") then
|
197 |
|
|
din <= X"DC4A";
|
198 |
|
|
elsif (daddr_v6pcie = X"0A") then
|
199 |
|
|
din <= X"C04A";
|
200 |
|
|
elsif (daddr_v6pcie = X"0B") then
|
201 |
|
|
din <= X"85BC";
|
202 |
|
|
end if;
|
203 |
|
|
next_drpstate <= DRP_WRITE_DONE_TS1;
|
204 |
|
|
|
205 |
|
|
-- WAIT FOR TS1 SEQUENCE WRITE TO FINISH, ONCE WE FINISH ALL WRITES GO TO TS1 IDLE
|
206 |
|
|
when DRP_WRITE_DONE_TS1 =>
|
207 |
|
|
if (drdy = '1') then
|
208 |
|
|
if (daddr_v6pcie = X"0B") then
|
209 |
|
|
next_drpstate <= DRP_IDLE_TS1;
|
210 |
|
|
next_daddr <= X"08";
|
211 |
|
|
else
|
212 |
|
|
next_drpstate <= DRP_WRITE_TS1;
|
213 |
|
|
next_daddr <= daddr_v6pcie + X"01";
|
214 |
|
|
end if;
|
215 |
|
|
end if;
|
216 |
|
|
|
217 |
|
|
-- TS1 IDLE: WAIT HERE UNTIL WE NEED TO WRITE FTS
|
218 |
|
|
when DRP_IDLE_TS1 =>
|
219 |
|
|
if (write_fts_gated = '1') then
|
220 |
|
|
next_drpstate <= DRP_WRITE_FTS;
|
221 |
|
|
next_daddr <= X"08";
|
222 |
|
|
end if;
|
223 |
|
|
when others =>
|
224 |
|
|
next_drpstate <= DRP_RESET;
|
225 |
|
|
next_daddr <= X"00";
|
226 |
|
|
end case;
|
227 |
|
|
end process;
|
228 |
|
|
|
229 |
|
|
|
230 |
|
|
end v6_pcie;
|
231 |
|
|
|
232 |
|
|
|
233 |
|
|
|