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//-----------------------------------------------------------------------------
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//
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// (c) Copyright 2009-2011 Xilinx, Inc. All rights reserved.
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//
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// This file contains confidential and proprietary information
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// of Xilinx, Inc. and is protected under U.S. and
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// international copyright and other intellectual property
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// laws.
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//
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// DISCLAIMER
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// This disclaimer is not a license and does not grant any
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// rights to the materials distributed herewith. Except as
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// otherwise provided in a valid license issued to you by
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// Xilinx, and to the maximum extent permitted by applicable
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// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
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// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
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// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
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// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
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// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
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// (2) Xilinx shall not be liable (whether in contract or tort,
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// including negligence, or under any other theory of
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// liability) for any loss or damage of any kind or nature
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// related to, arising under or in connection with these
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// materials, including for any direct, or any indirect,
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// special, incidental, or consequential loss or damage
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// (including loss of data, profits, goodwill, or any type of
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// loss or damage suffered as a result of any action brought
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// by a third party) even if such damage or loss was
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// reasonably foreseeable or Xilinx had been advised of the
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// possibility of the same.
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//
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// CRITICAL APPLICATIONS
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// Xilinx products are not designed or intended to be fail-
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// safe, or for use in any application requiring fail-safe
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// performance, such as life-support or safety devices or
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// systems, Class III medical devices, nuclear facilities,
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// applications related to the deployment of airbags, or any
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// other applications that could lead to death, personal
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// injury, or severe property or environmental damage
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// (individually and collectively, "Critical
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// Applications"). Customer assumes the sole risk and
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// liability of any use of Xilinx products in Critical
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// Applications, subject only to applicable laws and
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// regulations governing limitations on product liability.
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//
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// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
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// PART OF THIS FILE AT ALL TIMES.
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//
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//-----------------------------------------------------------------------------
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// Project : Virtex-6 Integrated Block for PCI Express
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// File : pcie_bram_top_v6.v
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// Version : 1.7
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//--
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//-- Description: BlockRAM top level module for Virtex6 PCIe Block
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//--
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//--
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//--
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//--------------------------------------------------------------------------------
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`timescale 1ns/1ns
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module pcie_bram_top_v6
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#(
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parameter DEV_CAP_MAX_PAYLOAD_SUPPORTED = 0,
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parameter VC0_TX_LASTPACKET = 31,
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parameter TLM_TX_OVERHEAD = 24,
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parameter TL_TX_RAM_RADDR_LATENCY = 1,
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parameter TL_TX_RAM_RDATA_LATENCY = 2,
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parameter TL_TX_RAM_WRITE_LATENCY = 1,
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parameter VC0_RX_LIMIT = 'h1FFF,
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parameter TL_RX_RAM_RADDR_LATENCY = 1,
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parameter TL_RX_RAM_RDATA_LATENCY = 2,
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parameter TL_RX_RAM_WRITE_LATENCY = 1
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)
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(
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input user_clk_i,
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input reset_i,
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input mim_tx_wen,
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input [12:0] mim_tx_waddr,
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input [71:0] mim_tx_wdata,
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input mim_tx_ren,
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input mim_tx_rce,
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input [12:0] mim_tx_raddr,
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output [71:0] mim_tx_rdata,
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input mim_rx_wen,
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input [12:0] mim_rx_waddr,
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input [71:0] mim_rx_wdata,
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input mim_rx_ren,
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input mim_rx_rce,
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input [12:0] mim_rx_raddr,
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output [71:0] mim_rx_rdata
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);
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// TX calculations
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localparam MPS_BYTES = ((DEV_CAP_MAX_PAYLOAD_SUPPORTED == 0) ? 128 :
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(DEV_CAP_MAX_PAYLOAD_SUPPORTED == 1) ? 256 :
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(DEV_CAP_MAX_PAYLOAD_SUPPORTED == 2) ? 512 :
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1024 );
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localparam BYTES_TX = (VC0_TX_LASTPACKET + 1) * (MPS_BYTES + TLM_TX_OVERHEAD);
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localparam ROWS_TX = 1;
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localparam COLS_TX = ((BYTES_TX <= 4096) ? 1 :
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(BYTES_TX <= 8192) ? 2 :
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(BYTES_TX <= 16384) ? 4 :
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(BYTES_TX <= 32768) ? 8 :
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18
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);
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// RX calculations
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localparam ROWS_RX = 1;
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localparam COLS_RX = ((VC0_RX_LIMIT < 'h0200) ? 1 :
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(VC0_RX_LIMIT < 'h0400) ? 2 :
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(VC0_RX_LIMIT < 'h0800) ? 4 :
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(VC0_RX_LIMIT < 'h1000) ? 8 :
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18
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);
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initial begin
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$display("[%t] %m ROWS_TX %0d COLS_TX %0d", $time, ROWS_TX, COLS_TX);
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$display("[%t] %m ROWS_RX %0d COLS_RX %0d", $time, ROWS_RX, COLS_RX);
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end
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pcie_brams_v6 #(.NUM_BRAMS (COLS_TX),
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.RAM_RADDR_LATENCY(TL_TX_RAM_RADDR_LATENCY),
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.RAM_RDATA_LATENCY(TL_TX_RAM_RDATA_LATENCY),
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.RAM_WRITE_LATENCY(TL_TX_RAM_WRITE_LATENCY))
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pcie_brams_tx
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(
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.user_clk_i(user_clk_i),
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.reset_i(reset_i),
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.waddr(mim_tx_waddr),
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.wen(mim_tx_wen),
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.ren(mim_tx_ren),
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.rce(mim_tx_rce),
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.wdata(mim_tx_wdata),
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.raddr(mim_tx_raddr),
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.rdata(mim_tx_rdata)
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);
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pcie_brams_v6 #(.NUM_BRAMS (COLS_RX),
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.RAM_RADDR_LATENCY(TL_RX_RAM_RADDR_LATENCY),
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.RAM_RDATA_LATENCY(TL_RX_RAM_RDATA_LATENCY),
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.RAM_WRITE_LATENCY(TL_RX_RAM_WRITE_LATENCY))
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pcie_brams_rx
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(
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.user_clk_i(user_clk_i),
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.reset_i(reset_i),
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.waddr(mim_rx_waddr),
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.wen(mim_rx_wen),
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.ren(mim_rx_ren),
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.rce(mim_rx_rce),
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.wdata(mim_rx_wdata),
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.raddr(mim_rx_raddr),
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.rdata(mim_rx_rdata)
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);
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endmodule // pcie_bram_top
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