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-------------------------------------------------------------------------------
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--
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-- (c) Copyright 2009-2011 Xilinx, Inc. All rights reserved.
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--
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-- This file contains confidential and proprietary information
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-- of Xilinx, Inc. and is protected under U.S. and
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-- international copyright and other intellectual property
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-- laws.
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--
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-- DISCLAIMER
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-- This disclaimer is not a license and does not grant any
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-- rights to the materials distributed herewith. Except as
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-- otherwise provided in a valid license issued to you by
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-- Xilinx, and to the maximum extent permitted by applicable
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-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
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-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
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-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
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-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
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-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
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-- (2) Xilinx shall not be liable (whether in contract or tort,
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-- including negligence, or under any other theory of
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-- liability) for any loss or damage of any kind or nature
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-- related to, arising under or in connection with these
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-- materials, including for any direct, or any indirect,
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-- special, incidental, or consequential loss or damage
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-- (including loss of data, profits, goodwill, or any type of
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-- loss or damage suffered as a result of any action brought
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-- by a third party) even if such damage or loss was
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-- reasonably foreseeable or Xilinx had been advised of the
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-- possibility of the same.
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--
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-- CRITICAL APPLICATIONS
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-- Xilinx products are not designed or intended to be fail-
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-- safe, or for use in any application requiring fail-safe
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-- performance, such as life-support or safety devices or
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-- systems, Class III medical devices, nuclear facilities,
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-- applications related to the deployment of airbags, or any
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-- other applications that could lead to death, personal
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-- injury, or severe property or environmental damage
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-- (individually and collectively, "Critical
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-- Applications"). Customer assumes the sole risk and
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-- liability of any use of Xilinx products in Critical
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-- Applications, subject only to applicable laws and
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-- regulations governing limitations on product liability.
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--
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-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
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-- PART OF THIS FILE AT ALL TIMES.
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--
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-------------------------------------------------------------------------------
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-- Project : Virtex-6 Integrated Block for PCI Express
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-- File : pcie_gtx_v6.vhd
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-- Version : 1.7
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-- Description: GTX module for Virtex6 PCIe Block
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--
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--
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--
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--------------------------------------------------------------------------------
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_unsigned.all;
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entity pcie_gtx_v6 is
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generic (
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NO_OF_LANES : integer := 8; -- 1 - x1 , 2 - x2 , 4 - x4 , 8 - x8
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LINK_CAP_MAX_LINK_SPEED : bit_vector := X"1"; -- 1 - Gen1, 2 - Gen2
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REF_CLK_FREQ : integer := 0; -- 0 - 100 MHz , 1 - 125 MHz , 2 - 250 MHz
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PL_FAST_TRAIN : boolean := FALSE
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);
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port (
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-- Pipe Per-Link Signals
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pipe_tx_rcvr_det : in std_logic;
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pipe_tx_reset : in std_logic;
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pipe_tx_rate : in std_logic;
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pipe_tx_deemph : in std_logic;
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pipe_tx_margin : in std_logic_vector(2 downto 0);
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pipe_tx_swing : in std_logic;
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-- Pipe Per-Lane Signals - Lane 0
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pipe_rx0_char_is_k : out std_logic_vector(1 downto 0);
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pipe_rx0_data : out std_logic_vector(15 downto 0);
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pipe_rx0_valid : out std_logic;
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pipe_rx0_chanisaligned : out std_logic;
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pipe_rx0_status : out std_logic_vector(2 downto 0);
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pipe_rx0_phy_status : out std_logic;
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pipe_rx0_elec_idle : out std_logic;
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pipe_rx0_polarity : in std_logic;
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pipe_tx0_compliance : in std_logic;
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pipe_tx0_char_is_k : in std_logic_vector(1 downto 0);
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pipe_tx0_data : in std_logic_vector(15 downto 0);
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pipe_tx0_elec_idle : in std_logic;
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pipe_tx0_powerdown : in std_logic_vector(1 downto 0);
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-- Pipe Per-Lane Signals - Lane 1
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pipe_rx1_char_is_k : out std_logic_vector(1 downto 0);
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pipe_rx1_data : out std_logic_vector(15 downto 0);
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pipe_rx1_valid : out std_logic;
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pipe_rx1_chanisaligned : out std_logic;
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pipe_rx1_status : out std_logic_vector(2 downto 0);
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pipe_rx1_phy_status : out std_logic;
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pipe_rx1_elec_idle : out std_logic;
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pipe_rx1_polarity : in std_logic;
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pipe_tx1_compliance : in std_logic;
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pipe_tx1_char_is_k : in std_logic_vector(1 downto 0);
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pipe_tx1_data : in std_logic_vector(15 downto 0);
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pipe_tx1_elec_idle : in std_logic;
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pipe_tx1_powerdown : in std_logic_vector(1 downto 0);
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-- Pipe Per-Lane Signals - Lane 2
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pipe_rx2_char_is_k : out std_logic_vector(1 downto 0);
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pipe_rx2_data : out std_logic_vector(15 downto 0);
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pipe_rx2_valid : out std_logic;
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pipe_rx2_chanisaligned : out std_logic;
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pipe_rx2_status : out std_logic_vector(2 downto 0);
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pipe_rx2_phy_status : out std_logic;
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pipe_rx2_elec_idle : out std_logic;
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pipe_rx2_polarity : in std_logic;
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pipe_tx2_compliance : in std_logic;
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pipe_tx2_char_is_k : in std_logic_vector(1 downto 0);
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pipe_tx2_data : in std_logic_vector(15 downto 0);
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pipe_tx2_elec_idle : in std_logic;
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pipe_tx2_powerdown : in std_logic_vector(1 downto 0);
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-- Pipe Per-Lane Signals - Lane 3
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pipe_rx3_char_is_k : out std_logic_vector(1 downto 0);
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pipe_rx3_data : out std_logic_vector(15 downto 0);
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pipe_rx3_valid : out std_logic;
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pipe_rx3_chanisaligned : out std_logic;
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pipe_rx3_status : out std_logic_vector(2 downto 0);
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pipe_rx3_phy_status : out std_logic;
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pipe_rx3_elec_idle : out std_logic;
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pipe_rx3_polarity : in std_logic;
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pipe_tx3_compliance : in std_logic;
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pipe_tx3_char_is_k : in std_logic_vector(1 downto 0);
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pipe_tx3_data : in std_logic_vector(15 downto 0);
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pipe_tx3_elec_idle : in std_logic;
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pipe_tx3_powerdown : in std_logic_vector(1 downto 0);
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-- Pipe Per-Lane Signals - Lane 4
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pipe_rx4_char_is_k : out std_logic_vector(1 downto 0);
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pipe_rx4_data : out std_logic_vector(15 downto 0);
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pipe_rx4_valid : out std_logic;
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pipe_rx4_chanisaligned : out std_logic;
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pipe_rx4_status : out std_logic_vector(2 downto 0);
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pipe_rx4_phy_status : out std_logic;
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pipe_rx4_elec_idle : out std_logic;
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pipe_rx4_polarity : in std_logic;
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pipe_tx4_compliance : in std_logic;
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pipe_tx4_char_is_k : in std_logic_vector(1 downto 0);
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pipe_tx4_data : in std_logic_vector(15 downto 0);
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pipe_tx4_elec_idle : in std_logic;
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pipe_tx4_powerdown : in std_logic_vector(1 downto 0);
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-- Pipe Per-Lane Signals - Lane 5
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pipe_rx5_char_is_k : out std_logic_vector(1 downto 0);
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pipe_rx5_data : out std_logic_vector(15 downto 0);
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pipe_rx5_valid : out std_logic;
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pipe_rx5_chanisaligned : out std_logic;
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pipe_rx5_status : out std_logic_vector(2 downto 0);
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pipe_rx5_phy_status : out std_logic;
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pipe_rx5_elec_idle : out std_logic;
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pipe_rx5_polarity : in std_logic;
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pipe_tx5_compliance : in std_logic;
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pipe_tx5_char_is_k : in std_logic_vector(1 downto 0);
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pipe_tx5_data : in std_logic_vector(15 downto 0);
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pipe_tx5_elec_idle : in std_logic;
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pipe_tx5_powerdown : in std_logic_vector(1 downto 0);
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-- Pipe Per-Lane Signals - Lane 6
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pipe_rx6_char_is_k : out std_logic_vector(1 downto 0);
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pipe_rx6_data : out std_logic_vector(15 downto 0);
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pipe_rx6_valid : out std_logic;
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pipe_rx6_chanisaligned : out std_logic;
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pipe_rx6_status : out std_logic_vector(2 downto 0);
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pipe_rx6_phy_status : out std_logic;
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pipe_rx6_elec_idle : out std_logic;
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pipe_rx6_polarity : in std_logic;
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pipe_tx6_compliance : in std_logic;
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pipe_tx6_char_is_k : in std_logic_vector(1 downto 0);
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pipe_tx6_data : in std_logic_vector(15 downto 0);
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pipe_tx6_elec_idle : in std_logic;
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pipe_tx6_powerdown : in std_logic_vector(1 downto 0);
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-- Pipe Per-Lane Signals - Lane 7
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pipe_rx7_char_is_k : out std_logic_vector(1 downto 0);
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pipe_rx7_data : out std_logic_vector(15 downto 0);
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pipe_rx7_valid : out std_logic;
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pipe_rx7_chanisaligned : out std_logic;
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pipe_rx7_status : out std_logic_vector(2 downto 0);
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pipe_rx7_phy_status : out std_logic;
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pipe_rx7_elec_idle : out std_logic;
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pipe_rx7_polarity : in std_logic;
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pipe_tx7_compliance : in std_logic;
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pipe_tx7_char_is_k : in std_logic_vector(1 downto 0);
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pipe_tx7_data : in std_logic_vector(15 downto 0);
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pipe_tx7_elec_idle : in std_logic;
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pipe_tx7_powerdown : in std_logic_vector(1 downto 0);
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-- PCI Express signals
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pci_exp_txn : out std_logic_vector((NO_OF_LANES - 1) downto 0);
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pci_exp_txp : out std_logic_vector((NO_OF_LANES - 1) downto 0);
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pci_exp_rxn : in std_logic_vector((NO_OF_LANES - 1) downto 0);
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pci_exp_rxp : in std_logic_vector((NO_OF_LANES - 1) downto 0);
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-- Non PIPE signals
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sys_clk : in std_logic;
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sys_rst_n : in std_logic;
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pipe_clk : in std_logic;
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drp_clk : in std_logic;
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clock_locked : in std_logic;
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gt_pll_lock : out std_logic;
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pl_ltssm_state : in std_logic_vector(5 downto 0);
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phy_rdy_n : out std_logic;
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TxOutClk : out std_logic
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);
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end pcie_gtx_v6;
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architecture v6_pcie of pcie_gtx_v6 is
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component gtx_wrapper_v6 is
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generic (
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NO_OF_LANES : integer := 1;
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REF_CLK_FREQ : integer := 0;
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PL_FAST_TRAIN : boolean := FALSE
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);
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port (
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TX : out std_logic_vector(NO_OF_LANES - 1 downto 0);
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TXN : out std_logic_vector(NO_OF_LANES - 1 downto 0);
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TxData : in std_logic_vector((NO_OF_LANES * 16) - 1 downto 0);
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TxDataK : in std_logic_vector((NO_OF_LANES * 2) - 1 downto 0);
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TxElecIdle : in std_logic_vector(NO_OF_LANES - 1 downto 0);
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TxCompliance : in std_logic_vector(NO_OF_LANES - 1 downto 0);
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RX : in std_logic_vector(NO_OF_LANES - 1 downto 0);
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RXN : in std_logic_vector(NO_OF_LANES - 1 downto 0);
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RxData : out std_logic_vector((NO_OF_LANES * 16) - 1 downto 0);
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RxDataK : out std_logic_vector((NO_OF_LANES * 2) - 1 downto 0);
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RxPolarity : in std_logic_vector(NO_OF_LANES - 1 downto 0);
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RxValid : out std_logic_vector(NO_OF_LANES - 1 downto 0);
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RxElecIdle : out std_logic_vector(NO_OF_LANES - 1 downto 0);
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RxStatus : out std_logic_vector((NO_OF_LANES * 3) - 1 downto 0);
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GTRefClkout : out std_logic_vector(NO_OF_LANES - 1 downto 0);
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plm_in_l0 : in std_logic;
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plm_in_rl : in std_logic;
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plm_in_dt : in std_logic;
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plm_in_rs : in std_logic;
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RxPLLLkDet : out std_logic_vector(NO_OF_LANES - 1 downto 0);
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TxDetectRx : in std_logic;
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PhyStatus : out std_logic_vector(NO_OF_LANES - 1 downto 0);
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TXPdownAsynch : in std_logic;
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PowerDown : in std_logic_vector((NO_OF_LANES * 2) - 1 downto 0);
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Rate : in std_logic;
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Reset_n : in std_logic;
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GTReset_n : in std_logic;
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PCLK : in std_logic;
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REFCLK : in std_logic;
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TxDeemph : in std_logic;
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TxMargin : in std_logic;
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TxSwing : in std_logic;
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ChanIsAligned : out std_logic_vector(NO_OF_LANES - 1 downto 0);
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local_pcs_reset : in std_logic;
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RxResetDone : out std_logic;
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SyncDone : out std_logic;
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DRPCLK : in std_logic;
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TxOutClk : out std_logic
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);
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end component;
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constant TCQ : integer := 1; -- clock to out delay model
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FUNCTION to_stdlogic (
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in_val : IN boolean) RETURN std_logic IS
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BEGIN
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IF (in_val) THEN
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RETURN('1');
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ELSE
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RETURN('0');
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END IF;
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END to_stdlogic;
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FUNCTION and_bw (
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val_in : std_logic_vector) RETURN std_logic IS
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VARIABLE ret : std_logic := '1';
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BEGIN
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FOR index IN val_in'RANGE LOOP
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ret := ret AND val_in(index);
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END LOOP;
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RETURN(ret);
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END and_bw;
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FUNCTION nand_bw (
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val_in : std_logic_vector) RETURN std_logic IS
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VARIABLE ret : std_logic := '1';
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BEGIN
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FOR index IN val_in'RANGE LOOP
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ret := ret AND val_in(index);
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END LOOP;
|
298 |
|
|
RETURN(NOT ret);
|
299 |
|
|
END nand_bw;
|
300 |
|
|
|
301 |
|
|
signal gt_rx_phy_status_wire : std_logic_vector(7 downto 0);
|
302 |
|
|
signal gt_rxchanisaligned_wire : std_logic_vector(7 downto 0);
|
303 |
|
|
signal gt_rx_data_k_wire : std_logic_vector(127 downto 0);
|
304 |
|
|
signal gt_rx_data_wire : std_logic_vector(127 downto 0);
|
305 |
|
|
signal gt_rx_elec_idle_wire : std_logic_vector(7 downto 0);
|
306 |
|
|
signal gt_rx_status_wire : std_logic_vector(23 downto 0);
|
307 |
|
|
signal gt_rx_valid_wire : std_logic_vector(7 downto 0);
|
308 |
|
|
signal gt_rx_polarity : std_logic_vector(7 downto 0);
|
309 |
|
|
signal gt_power_down : std_logic_vector(15 downto 0);
|
310 |
|
|
signal gt_tx_char_disp_mode : std_logic_vector(7 downto 0);
|
311 |
|
|
signal gt_tx_data_k : std_logic_vector(15 downto 0);
|
312 |
|
|
signal gt_tx_data : std_logic_vector(127 downto 0);
|
313 |
|
|
signal gt_tx_detect_rx_loopback : std_logic;
|
314 |
|
|
signal gt_tx_elec_idle : std_logic_vector(7 downto 0);
|
315 |
|
|
signal gt_rx_elec_idle_reset : std_logic_vector(7 downto 0);
|
316 |
|
|
|
317 |
|
|
signal plllkdet : std_logic_vector(NO_OF_LANES - 1 downto 0);
|
318 |
|
|
signal RxResetDone : std_logic;
|
319 |
|
|
signal plm_in_l0 : std_logic;
|
320 |
|
|
signal plm_in_rl : std_logic;
|
321 |
|
|
signal plm_in_dt : std_logic;
|
322 |
|
|
signal plm_in_rs : std_logic;
|
323 |
|
|
|
324 |
|
|
signal local_pcs_reset : std_logic;
|
325 |
|
|
signal local_pcs_reset_done : std_logic;
|
326 |
|
|
signal cnt_local_pcs_reset : std_logic_vector(3 downto 0);
|
327 |
|
|
signal phy_rdy_pre_cnt : std_logic_vector(4 downto 0);
|
328 |
|
|
signal pl_ltssm_state_q : std_logic_vector(5 downto 0);
|
329 |
|
|
|
330 |
|
|
signal SyncDone : std_logic;
|
331 |
|
|
|
332 |
|
|
-- X-HDL generated signals
|
333 |
|
|
|
334 |
|
|
signal v6pcie5 : std_logic;
|
335 |
|
|
|
336 |
|
|
-- Declare intermediate signals for referenced outputs
|
337 |
|
|
signal pci_exp_txn_v6pcie2 : std_logic_vector((NO_OF_LANES - 1) downto 0);
|
338 |
|
|
signal pci_exp_txp_v6pcie3 : std_logic_vector((NO_OF_LANES - 1) downto 0);
|
339 |
|
|
signal gt_pll_lock_v6pcie1 : std_logic;
|
340 |
|
|
signal phy_rdy_n_v6pcie4 : std_logic;
|
341 |
|
|
signal TxOutClk_v6pcie0 : std_logic;
|
342 |
|
|
|
343 |
|
|
signal plllkdet_nand : std_logic;
|
344 |
|
|
|
345 |
|
|
begin
|
346 |
|
|
-- Drive referenced outputs
|
347 |
|
|
pci_exp_txn <= pci_exp_txn_v6pcie2;
|
348 |
|
|
pci_exp_txp <= pci_exp_txp_v6pcie3;
|
349 |
|
|
gt_pll_lock <= gt_pll_lock_v6pcie1;
|
350 |
|
|
phy_rdy_n <= phy_rdy_n_v6pcie4;
|
351 |
|
|
TxOutClk <= TxOutClk_v6pcie0;
|
352 |
|
|
plm_in_l0 <= to_stdlogic((pl_ltssm_state_q = "010110"));
|
353 |
|
|
plm_in_rl <= to_stdlogic((pl_ltssm_state_q = "011100"));
|
354 |
|
|
plm_in_dt <= to_stdlogic((pl_ltssm_state_q = "101101"));
|
355 |
|
|
plm_in_rs <= to_stdlogic((pl_ltssm_state_q = "011111"));
|
356 |
|
|
|
357 |
|
|
v6pcie5 <= not(clock_locked);
|
358 |
|
|
|
359 |
|
|
gtx_v6_i : gtx_wrapper_v6
|
360 |
|
|
generic map (
|
361 |
|
|
NO_OF_LANES => NO_OF_LANES,
|
362 |
|
|
REF_CLK_FREQ => REF_CLK_FREQ,
|
363 |
|
|
PL_FAST_TRAIN => PL_FAST_TRAIN
|
364 |
|
|
)
|
365 |
|
|
port map (
|
366 |
|
|
|
367 |
|
|
-- TX
|
368 |
|
|
TX => pci_exp_txp_v6pcie3(((NO_OF_LANES) - 1) downto 0),
|
369 |
|
|
TXN => pci_exp_txn_v6pcie2(((NO_OF_LANES) - 1) downto 0),
|
370 |
|
|
TxData => gt_tx_data(((16 * NO_OF_LANES) - 1) downto 0),
|
371 |
|
|
TxDataK => gt_tx_data_k(((2 * NO_OF_LANES) - 1) downto 0),
|
372 |
|
|
TxElecIdle => gt_tx_elec_idle(((NO_OF_LANES) - 1) downto 0),
|
373 |
|
|
TxCompliance => gt_tx_char_disp_mode(((NO_OF_LANES) - 1) downto 0),
|
374 |
|
|
|
375 |
|
|
-- RX
|
376 |
|
|
RX => pci_exp_rxp(((NO_OF_LANES) - 1) downto 0),
|
377 |
|
|
RXN => pci_exp_rxn(((NO_OF_LANES) - 1) downto 0),
|
378 |
|
|
RxData => gt_rx_data_wire(((16 * NO_OF_LANES) - 1) downto 0),
|
379 |
|
|
RxDataK => gt_rx_data_k_wire(((2 * NO_OF_LANES) - 1) downto 0),
|
380 |
|
|
RxPolarity => gt_rx_polarity(((NO_OF_LANES) - 1) downto 0),
|
381 |
|
|
RxValid => gt_rx_valid_wire(((NO_OF_LANES) - 1) downto 0),
|
382 |
|
|
RxElecIdle => gt_rx_elec_idle_wire(((NO_OF_LANES) - 1) downto 0),
|
383 |
|
|
RxStatus => gt_rx_status_wire(((3 * NO_OF_LANES) - 1) downto 0),
|
384 |
|
|
|
385 |
|
|
-- other
|
386 |
|
|
GTRefClkout => open,
|
387 |
|
|
plm_in_l0 => plm_in_l0,
|
388 |
|
|
plm_in_rl => plm_in_rl,
|
389 |
|
|
plm_in_dt => plm_in_dt,
|
390 |
|
|
plm_in_rs => plm_in_rs,
|
391 |
|
|
RxPLLLkDet => plllkdet,
|
392 |
|
|
ChanIsAligned => gt_rxchanisaligned_wire(((NO_OF_LANES) - 1) downto 0),
|
393 |
|
|
TxDetectRx => gt_tx_detect_rx_loopback,
|
394 |
|
|
PhyStatus => gt_rx_phy_status_wire(((NO_OF_LANES) - 1) downto 0),
|
395 |
|
|
TXPdownAsynch => v6pcie5,
|
396 |
|
|
PowerDown => gt_power_down(((2 * NO_OF_LANES) - 1) downto 0),
|
397 |
|
|
Rate => pipe_tx_rate,
|
398 |
|
|
Reset_n => clock_locked,
|
399 |
|
|
GTReset_n => sys_rst_n,
|
400 |
|
|
PCLK => pipe_clk,
|
401 |
|
|
REFCLK => sys_clk,
|
402 |
|
|
DRPCLK => drp_clk,
|
403 |
|
|
TxDeemph => pipe_tx_deemph,
|
404 |
|
|
TxMargin => pipe_tx_margin(2),
|
405 |
|
|
TxSwing => pipe_tx_swing,
|
406 |
|
|
local_pcs_reset => local_pcs_reset,
|
407 |
|
|
RxResetDone => RxResetDone,
|
408 |
|
|
SyncDone => SyncDone,
|
409 |
|
|
TxOutClk => TxOutClk_v6pcie0
|
410 |
|
|
);
|
411 |
|
|
|
412 |
|
|
pipe_rx0_phy_status <= gt_rx_phy_status_wire(0);
|
413 |
|
|
pipe_rx1_phy_status <= gt_rx_phy_status_wire(1) when (NO_OF_LANES >= 2) else
|
414 |
|
|
'0';
|
415 |
|
|
pipe_rx2_phy_status <= gt_rx_phy_status_wire(2) when (NO_OF_LANES >= 4) else
|
416 |
|
|
'0';
|
417 |
|
|
pipe_rx3_phy_status <= gt_rx_phy_status_wire(3) when (NO_OF_LANES >= 4) else
|
418 |
|
|
'0';
|
419 |
|
|
pipe_rx4_phy_status <= gt_rx_phy_status_wire(4) when (NO_OF_LANES >= 8) else
|
420 |
|
|
'0';
|
421 |
|
|
pipe_rx5_phy_status <= gt_rx_phy_status_wire(5) when (NO_OF_LANES >= 8) else
|
422 |
|
|
'0';
|
423 |
|
|
pipe_rx6_phy_status <= gt_rx_phy_status_wire(6) when (NO_OF_LANES >= 8) else
|
424 |
|
|
'0';
|
425 |
|
|
pipe_rx7_phy_status <= gt_rx_phy_status_wire(7) when (NO_OF_LANES >= 8) else
|
426 |
|
|
'0';
|
427 |
|
|
|
428 |
|
|
pipe_rx0_chanisaligned <= gt_rxchanisaligned_wire(0);
|
429 |
|
|
pipe_rx1_chanisaligned <= gt_rxchanisaligned_wire(1) when (NO_OF_LANES >= 2) else
|
430 |
|
|
'0';
|
431 |
|
|
pipe_rx2_chanisaligned <= gt_rxchanisaligned_wire(2) when (NO_OF_LANES >= 4) else
|
432 |
|
|
'0';
|
433 |
|
|
pipe_rx3_chanisaligned <= gt_rxchanisaligned_wire(3) when (NO_OF_LANES >= 4) else
|
434 |
|
|
'0';
|
435 |
|
|
pipe_rx4_chanisaligned <= gt_rxchanisaligned_wire(4) when (NO_OF_LANES >= 8) else
|
436 |
|
|
'0';
|
437 |
|
|
pipe_rx5_chanisaligned <= gt_rxchanisaligned_wire(5) when (NO_OF_LANES >= 8) else
|
438 |
|
|
'0';
|
439 |
|
|
pipe_rx6_chanisaligned <= gt_rxchanisaligned_wire(6) when (NO_OF_LANES >= 8) else
|
440 |
|
|
'0';
|
441 |
|
|
pipe_rx7_chanisaligned <= gt_rxchanisaligned_wire(7) when (NO_OF_LANES >= 8) else
|
442 |
|
|
'0';
|
443 |
|
|
|
444 |
|
|
--<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<
|
445 |
|
|
--<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<
|
446 |
|
|
|
447 |
|
|
pipe_rx0_char_is_k <= (gt_rx_data_k_wire(1) & gt_rx_data_k_wire(0));
|
448 |
|
|
pipe_rx1_char_is_k <= (gt_rx_data_k_wire(3) & gt_rx_data_k_wire(2)) when (NO_OF_LANES >= 2) else
|
449 |
|
|
"00";
|
450 |
|
|
pipe_rx2_char_is_k <= (gt_rx_data_k_wire(5) & gt_rx_data_k_wire(4)) when (NO_OF_LANES >= 4) else
|
451 |
|
|
"00";
|
452 |
|
|
pipe_rx3_char_is_k <= (gt_rx_data_k_wire(7) & gt_rx_data_k_wire(6)) when (NO_OF_LANES >= 4) else
|
453 |
|
|
"00";
|
454 |
|
|
pipe_rx4_char_is_k <= (gt_rx_data_k_wire(9) & gt_rx_data_k_wire(8)) when (NO_OF_LANES >= 8) else
|
455 |
|
|
"00";
|
456 |
|
|
pipe_rx5_char_is_k <= (gt_rx_data_k_wire(11) & gt_rx_data_k_wire(10)) when (NO_OF_LANES >= 8) else
|
457 |
|
|
"00";
|
458 |
|
|
pipe_rx6_char_is_k <= (gt_rx_data_k_wire(13) & gt_rx_data_k_wire(12)) when (NO_OF_LANES >= 8) else
|
459 |
|
|
"00";
|
460 |
|
|
pipe_rx7_char_is_k <= (gt_rx_data_k_wire(15) & gt_rx_data_k_wire(14)) when (NO_OF_LANES >= 8) else
|
461 |
|
|
"00";
|
462 |
|
|
|
463 |
|
|
pipe_rx0_data <= (gt_rx_data_wire(15 downto 8) & gt_rx_data_wire(7 downto 0));
|
464 |
|
|
pipe_rx1_data <= (gt_rx_data_wire(31 downto 24) & gt_rx_data_wire(23 downto 16)) when (NO_OF_LANES >= 2) else
|
465 |
|
|
"0000000000000000";
|
466 |
|
|
pipe_rx2_data <= (gt_rx_data_wire(47 downto 40) & gt_rx_data_wire(39 downto 32)) when (NO_OF_LANES >= 4) else
|
467 |
|
|
"0000000000000000";
|
468 |
|
|
pipe_rx3_data <= (gt_rx_data_wire(63 downto 56) & gt_rx_data_wire(55 downto 48)) when (NO_OF_LANES >= 4) else
|
469 |
|
|
"0000000000000000";
|
470 |
|
|
pipe_rx4_data <= (gt_rx_data_wire(79 downto 72) & gt_rx_data_wire(71 downto 64)) when (NO_OF_LANES >= 8) else
|
471 |
|
|
"0000000000000000";
|
472 |
|
|
pipe_rx5_data <= (gt_rx_data_wire(95 downto 88) & gt_rx_data_wire(87 downto 80)) when (NO_OF_LANES >= 8) else
|
473 |
|
|
"0000000000000000";
|
474 |
|
|
pipe_rx6_data <= (gt_rx_data_wire(111 downto 104) & gt_rx_data_wire(103 downto 96)) when (NO_OF_LANES >= 8) else
|
475 |
|
|
"0000000000000000";
|
476 |
|
|
pipe_rx7_data <= (gt_rx_data_wire(127 downto 120) & gt_rx_data_wire(119 downto 112)) when (NO_OF_LANES >= 8) else
|
477 |
|
|
"0000000000000000";
|
478 |
|
|
|
479 |
|
|
--<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<
|
480 |
|
|
--<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<
|
481 |
|
|
|
482 |
|
|
pipe_rx0_elec_idle <= gt_rx_elec_idle_wire(0);
|
483 |
|
|
pipe_rx1_elec_idle <= gt_rx_elec_idle_wire(1) when (NO_OF_LANES >= 2) else
|
484 |
|
|
'1';
|
485 |
|
|
pipe_rx2_elec_idle <= gt_rx_elec_idle_wire(2) when (NO_OF_LANES >= 4) else
|
486 |
|
|
'1';
|
487 |
|
|
pipe_rx3_elec_idle <= gt_rx_elec_idle_wire(3) when (NO_OF_LANES >= 4) else
|
488 |
|
|
'1';
|
489 |
|
|
pipe_rx4_elec_idle <= gt_rx_elec_idle_wire(4) when (NO_OF_LANES >= 8) else
|
490 |
|
|
'1';
|
491 |
|
|
pipe_rx5_elec_idle <= gt_rx_elec_idle_wire(5) when (NO_OF_LANES >= 8) else
|
492 |
|
|
'1';
|
493 |
|
|
pipe_rx6_elec_idle <= gt_rx_elec_idle_wire(6) when (NO_OF_LANES >= 8) else
|
494 |
|
|
'1';
|
495 |
|
|
pipe_rx7_elec_idle <= gt_rx_elec_idle_wire(7) when (NO_OF_LANES >= 8) else
|
496 |
|
|
'1';
|
497 |
|
|
|
498 |
|
|
pipe_rx0_status <= gt_rx_status_wire(2 downto 0);
|
499 |
|
|
pipe_rx1_status <= gt_rx_status_wire(5 downto 3) when (NO_OF_LANES >= 2) else
|
500 |
|
|
"000";
|
501 |
|
|
pipe_rx2_status <= gt_rx_status_wire(8 downto 6) when (NO_OF_LANES >= 4) else
|
502 |
|
|
"000";
|
503 |
|
|
pipe_rx3_status <= gt_rx_status_wire(11 downto 9) when (NO_OF_LANES >= 4) else
|
504 |
|
|
"000";
|
505 |
|
|
pipe_rx4_status <= gt_rx_status_wire(14 downto 12) when (NO_OF_LANES >= 8) else
|
506 |
|
|
"000";
|
507 |
|
|
pipe_rx5_status <= gt_rx_status_wire(17 downto 15) when (NO_OF_LANES >= 8) else
|
508 |
|
|
"000";
|
509 |
|
|
pipe_rx6_status <= gt_rx_status_wire(20 downto 18) when (NO_OF_LANES >= 8) else
|
510 |
|
|
"000";
|
511 |
|
|
pipe_rx7_status <= gt_rx_status_wire(23 downto 21) when (NO_OF_LANES >= 8) else
|
512 |
|
|
"000";
|
513 |
|
|
|
514 |
|
|
pipe_rx0_valid <= gt_rx_valid_wire(0);
|
515 |
|
|
pipe_rx1_valid <= gt_rx_valid_wire(1) when (NO_OF_LANES >= 2) else
|
516 |
|
|
'0';
|
517 |
|
|
pipe_rx2_valid <= gt_rx_valid_wire(2) when (NO_OF_LANES >= 4) else
|
518 |
|
|
'0';
|
519 |
|
|
pipe_rx3_valid <= gt_rx_valid_wire(3) when (NO_OF_LANES >= 4) else
|
520 |
|
|
'0';
|
521 |
|
|
pipe_rx4_valid <= gt_rx_valid_wire(4) when (NO_OF_LANES >= 8) else
|
522 |
|
|
'0';
|
523 |
|
|
pipe_rx5_valid <= gt_rx_valid_wire(5) when (NO_OF_LANES >= 8) else
|
524 |
|
|
'0';
|
525 |
|
|
pipe_rx6_valid <= gt_rx_valid_wire(6) when (NO_OF_LANES >= 8) else
|
526 |
|
|
'0';
|
527 |
|
|
pipe_rx7_valid <= gt_rx_valid_wire(7) when (NO_OF_LANES >= 8) else
|
528 |
|
|
'0';
|
529 |
|
|
|
530 |
|
|
gt_rx_polarity(0) <= pipe_rx0_polarity;
|
531 |
|
|
gt_rx_polarity(1) <= pipe_rx1_polarity;
|
532 |
|
|
gt_rx_polarity(2) <= pipe_rx2_polarity;
|
533 |
|
|
gt_rx_polarity(3) <= pipe_rx3_polarity;
|
534 |
|
|
gt_rx_polarity(4) <= pipe_rx4_polarity;
|
535 |
|
|
gt_rx_polarity(5) <= pipe_rx5_polarity;
|
536 |
|
|
gt_rx_polarity(6) <= pipe_rx6_polarity;
|
537 |
|
|
gt_rx_polarity(7) <= pipe_rx7_polarity;
|
538 |
|
|
|
539 |
|
|
gt_power_down(1 downto 0) <= pipe_tx0_powerdown;
|
540 |
|
|
gt_power_down(3 downto 2) <= pipe_tx1_powerdown;
|
541 |
|
|
gt_power_down(5 downto 4) <= pipe_tx2_powerdown;
|
542 |
|
|
gt_power_down(7 downto 6) <= pipe_tx3_powerdown;
|
543 |
|
|
gt_power_down(9 downto 8) <= pipe_tx4_powerdown;
|
544 |
|
|
gt_power_down(11 downto 10) <= pipe_tx5_powerdown;
|
545 |
|
|
gt_power_down(13 downto 12) <= pipe_tx6_powerdown;
|
546 |
|
|
gt_power_down(15 downto 14) <= pipe_tx7_powerdown;
|
547 |
|
|
|
548 |
|
|
gt_tx_char_disp_mode <= (pipe_tx7_compliance & pipe_tx6_compliance & pipe_tx5_compliance & pipe_tx4_compliance & pipe_tx3_compliance & pipe_tx2_compliance & pipe_tx1_compliance & pipe_tx0_compliance);
|
549 |
|
|
|
550 |
|
|
gt_tx_data_k <= (pipe_tx7_char_is_k & pipe_tx6_char_is_k & pipe_tx5_char_is_k & pipe_tx4_char_is_k & pipe_tx3_char_is_k & pipe_tx2_char_is_k & pipe_tx1_char_is_k & pipe_tx0_char_is_k);
|
551 |
|
|
|
552 |
|
|
gt_tx_data <= (pipe_tx7_data & pipe_tx6_data & pipe_tx5_data & pipe_tx4_data & pipe_tx3_data & pipe_tx2_data & pipe_tx1_data & pipe_tx0_data);
|
553 |
|
|
|
554 |
|
|
gt_tx_detect_rx_loopback <= pipe_tx_rcvr_det;
|
555 |
|
|
|
556 |
|
|
gt_tx_elec_idle <= (pipe_tx7_elec_idle & pipe_tx6_elec_idle & pipe_tx5_elec_idle & pipe_tx4_elec_idle & pipe_tx3_elec_idle & pipe_tx2_elec_idle & pipe_tx1_elec_idle & pipe_tx0_elec_idle);
|
557 |
|
|
|
558 |
|
|
gt_pll_lock_v6pcie1 <= and_bw(plllkdet(NO_OF_LANES - 1 downto 0)) or not(phy_rdy_pre_cnt(4));
|
559 |
|
|
|
560 |
|
|
plllkdet_nand <= nand_bw(plllkdet(NO_OF_LANES - 1 downto 0));
|
561 |
|
|
|
562 |
|
|
-- Asserted after all workarounds have completed.
|
563 |
|
|
|
564 |
|
|
process (pipe_clk, clock_locked)
|
565 |
|
|
begin
|
566 |
|
|
|
567 |
|
|
if ((not(clock_locked)) = '1') then
|
568 |
|
|
|
569 |
|
|
phy_rdy_n_v6pcie4 <= '1' after (TCQ)*1 ps;
|
570 |
|
|
|
571 |
|
|
elsif (pipe_clk'event and pipe_clk = '1') then
|
572 |
|
|
|
573 |
|
|
if (plllkdet_nand = '1') then
|
574 |
|
|
phy_rdy_n_v6pcie4 <= '1' after (TCQ)*1 ps;
|
575 |
|
|
elsif ((local_pcs_reset_done and RxResetDone and phy_rdy_n_v6pcie4 and SyncDone) = '1') then
|
576 |
|
|
phy_rdy_n_v6pcie4 <= '0' after (TCQ)*1 ps;
|
577 |
|
|
end if;
|
578 |
|
|
|
579 |
|
|
end if;
|
580 |
|
|
end process;
|
581 |
|
|
|
582 |
|
|
|
583 |
|
|
-- Handle the warm reset case, where sys_rst_n is asseted when
|
584 |
|
|
-- phy_rdy_n is asserted. phy_rdy_n is to be de-asserted
|
585 |
|
|
-- before gt_pll_lock is de-asserted so that synnchronous
|
586 |
|
|
-- logic see reset de-asset before clock is lost.
|
587 |
|
|
|
588 |
|
|
process (pipe_clk, clock_locked)
|
589 |
|
|
begin
|
590 |
|
|
|
591 |
|
|
if ((not(clock_locked)) = '1') then
|
592 |
|
|
|
593 |
|
|
phy_rdy_pre_cnt <= "11111" after (TCQ)*1 ps;
|
594 |
|
|
|
595 |
|
|
elsif (pipe_clk'event and pipe_clk = '1') then
|
596 |
|
|
|
597 |
|
|
if ((gt_pll_lock_v6pcie1 and phy_rdy_n_v6pcie4) = '1') then
|
598 |
|
|
|
599 |
|
|
phy_rdy_pre_cnt <= phy_rdy_pre_cnt + "00001" after (TCQ)*1 ps;
|
600 |
|
|
|
601 |
|
|
end if;
|
602 |
|
|
end if;
|
603 |
|
|
end process;
|
604 |
|
|
|
605 |
|
|
|
606 |
|
|
process (pipe_clk, clock_locked)
|
607 |
|
|
begin
|
608 |
|
|
|
609 |
|
|
if ((not(clock_locked)) = '1') then
|
610 |
|
|
|
611 |
|
|
cnt_local_pcs_reset <= "1111" after (TCQ)*1 ps;
|
612 |
|
|
local_pcs_reset <= '0' after (TCQ)*1 ps;
|
613 |
|
|
local_pcs_reset_done <= '0' after (TCQ)*1 ps;
|
614 |
|
|
|
615 |
|
|
elsif (pipe_clk'event and pipe_clk = '1') then
|
616 |
|
|
|
617 |
|
|
if ((local_pcs_reset = '0') and (cnt_local_pcs_reset = "1111")) then
|
618 |
|
|
local_pcs_reset <= '1' after (TCQ)*1 ps;
|
619 |
|
|
elsif ((local_pcs_reset = '1') and (cnt_local_pcs_reset /= "0000")) then
|
620 |
|
|
local_pcs_reset <= '1' after (TCQ)*1 ps;
|
621 |
|
|
cnt_local_pcs_reset <= cnt_local_pcs_reset - "0001" after (TCQ)*1 ps;
|
622 |
|
|
elsif ((local_pcs_reset = '1') and (cnt_local_pcs_reset = "0000")) then
|
623 |
|
|
local_pcs_reset <= '0' after (TCQ)*1 ps;
|
624 |
|
|
local_pcs_reset_done <= '1' after (TCQ)*1 ps;
|
625 |
|
|
end if;
|
626 |
|
|
|
627 |
|
|
end if;
|
628 |
|
|
end process;
|
629 |
|
|
|
630 |
|
|
process (pipe_clk, clock_locked)
|
631 |
|
|
begin
|
632 |
|
|
|
633 |
|
|
if ((not(clock_locked)) = '1') then
|
634 |
|
|
|
635 |
|
|
pl_ltssm_state_q <= "000000" after (TCQ)*1 ps;
|
636 |
|
|
|
637 |
|
|
elsif (pipe_clk'event and pipe_clk = '1') then
|
638 |
|
|
|
639 |
|
|
pl_ltssm_state_q <= pl_ltssm_state after (TCQ)*1 ps;
|
640 |
|
|
|
641 |
|
|
end if;
|
642 |
|
|
end process;
|
643 |
|
|
|
644 |
|
|
|
645 |
|
|
end v6_pcie;
|