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-------------------------------------------------------------------------------
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--
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-- (c) Copyright 2009-2011 Xilinx, Inc. All rights reserved.
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--
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-- This file contains confidential and proprietary information
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-- of Xilinx, Inc. and is protected under U.S. and
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-- international copyright and other intellectual property
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-- laws.
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--
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-- DISCLAIMER
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-- This disclaimer is not a license and does not grant any
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-- rights to the materials distributed herewith. Except as
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-- otherwise provided in a valid license issued to you by
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-- Xilinx, and to the maximum extent permitted by applicable
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-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
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-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
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-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
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-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
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-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
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-- (2) Xilinx shall not be liable (whether in contract or tort,
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-- including negligence, or under any other theory of
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-- liability) for any loss or damage of any kind or nature
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-- related to, arising under or in connection with these
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-- materials, including for any direct, or any indirect,
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-- special, incidental, or consequential loss or damage
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-- (including loss of data, profits, goodwill, or any type of
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-- loss or damage suffered as a result of any action brought
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-- by a third party) even if such damage or loss was
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-- reasonably foreseeable or Xilinx had been advised of the
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-- possibility of the same.
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--
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-- CRITICAL APPLICATIONS
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-- Xilinx products are not designed or intended to be fail-
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-- safe, or for use in any application requiring fail-safe
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-- performance, such as life-support or safety devices or
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-- systems, Class III medical devices, nuclear facilities,
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-- applications related to the deployment of airbags, or any
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-- other applications that could lead to death, personal
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-- injury, or severe property or environmental damage
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-- (individually and collectively, "Critical
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-- Applications"). Customer assumes the sole risk and
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-- liability of any use of Xilinx products in Critical
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-- Applications, subject only to applicable laws and
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-- regulations governing limitations on product liability.
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--
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-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
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-- PART OF THIS FILE AT ALL TIMES.
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--
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-------------------------------------------------------------------------------
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-- Project : Virtex-6 Integrated Block for PCI Express
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-- File : pcie_pipe_v6.vhd
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-- Version : 1.7
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---- Description: PIPE module for Virtex6 PCIe Block
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----
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----
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----
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----------------------------------------------------------------------------------
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library ieee;
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use ieee.std_logic_1164.all;
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entity pcie_pipe_v6 is
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generic (
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NO_OF_LANES : integer := 8;
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LINK_CAP_MAX_LINK_SPEED : bit_vector := X"1";
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PIPE_PIPELINE_STAGES : integer := 0 -- 0 - 0 stages, 1 - 1 stage, 2 - 2 stages
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);
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port (
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-- Pipe Per-Link Signals
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pipe_tx_rcvr_det_i : in std_logic;
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pipe_tx_reset_i : in std_logic;
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pipe_tx_rate_i : in std_logic;
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pipe_tx_deemph_i : in std_logic;
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pipe_tx_margin_i : in std_logic_vector(2 downto 0);
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pipe_tx_swing_i : in std_logic;
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pipe_tx_rcvr_det_o : out std_logic;
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pipe_tx_reset_o : out std_logic;
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pipe_tx_rate_o : out std_logic;
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pipe_tx_deemph_o : out std_logic;
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pipe_tx_margin_o : out std_logic_vector(2 downto 0);
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pipe_tx_swing_o : out std_logic;
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-- Pipe Per-Lane Signals - Lane 0
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pipe_rx0_char_is_k_o : out std_logic_vector(1 downto 0);
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pipe_rx0_data_o : out std_logic_vector(15 downto 0);
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pipe_rx0_valid_o : out std_logic;
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pipe_rx0_chanisaligned_o : out std_logic;
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pipe_rx0_status_o : out std_logic_vector(2 downto 0);
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pipe_rx0_phy_status_o : out std_logic;
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pipe_rx0_elec_idle_o : out std_logic;
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pipe_rx0_polarity_i : in std_logic;
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pipe_tx0_compliance_i : in std_logic;
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pipe_tx0_char_is_k_i : in std_logic_vector(1 downto 0);
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pipe_tx0_data_i : in std_logic_vector(15 downto 0);
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pipe_tx0_elec_idle_i : in std_logic;
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pipe_tx0_powerdown_i : in std_logic_vector(1 downto 0);
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pipe_rx0_char_is_k_i : in std_logic_vector(1 downto 0);
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pipe_rx0_data_i : in std_logic_vector(15 downto 0);
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pipe_rx0_valid_i : in std_logic;
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pipe_rx0_chanisaligned_i : in std_logic;
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pipe_rx0_status_i : in std_logic_vector(2 downto 0);
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pipe_rx0_phy_status_i : in std_logic;
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pipe_rx0_elec_idle_i : in std_logic;
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pipe_rx0_polarity_o : out std_logic;
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pipe_tx0_compliance_o : out std_logic;
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pipe_tx0_char_is_k_o : out std_logic_vector(1 downto 0);
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pipe_tx0_data_o : out std_logic_vector(15 downto 0);
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pipe_tx0_elec_idle_o : out std_logic;
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pipe_tx0_powerdown_o : out std_logic_vector(1 downto 0);
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-- Pipe Per-Lane Signals - Lane 1
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pipe_rx1_char_is_k_o : out std_logic_vector(1 downto 0);
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pipe_rx1_data_o : out std_logic_vector(15 downto 0);
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pipe_rx1_valid_o : out std_logic;
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pipe_rx1_chanisaligned_o : out std_logic;
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pipe_rx1_status_o : out std_logic_vector(2 downto 0);
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pipe_rx1_phy_status_o : out std_logic;
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pipe_rx1_elec_idle_o : out std_logic;
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pipe_rx1_polarity_i : in std_logic;
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pipe_tx1_compliance_i : in std_logic;
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pipe_tx1_char_is_k_i : in std_logic_vector(1 downto 0);
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pipe_tx1_data_i : in std_logic_vector(15 downto 0);
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pipe_tx1_elec_idle_i : in std_logic;
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pipe_tx1_powerdown_i : in std_logic_vector(1 downto 0);
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pipe_rx1_char_is_k_i : in std_logic_vector(1 downto 0);
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pipe_rx1_data_i : in std_logic_vector(15 downto 0);
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pipe_rx1_valid_i : in std_logic;
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pipe_rx1_chanisaligned_i : in std_logic;
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pipe_rx1_status_i : in std_logic_vector(2 downto 0);
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pipe_rx1_phy_status_i : in std_logic;
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pipe_rx1_elec_idle_i : in std_logic;
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pipe_rx1_polarity_o : out std_logic;
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pipe_tx1_compliance_o : out std_logic;
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pipe_tx1_char_is_k_o : out std_logic_vector(1 downto 0);
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pipe_tx1_data_o : out std_logic_vector(15 downto 0);
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pipe_tx1_elec_idle_o : out std_logic;
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pipe_tx1_powerdown_o : out std_logic_vector(1 downto 0);
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-- Pipe Per-Lane Signals - Lane 2
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pipe_rx2_char_is_k_o : out std_logic_vector(1 downto 0);
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pipe_rx2_data_o : out std_logic_vector(15 downto 0);
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pipe_rx2_valid_o : out std_logic;
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pipe_rx2_chanisaligned_o : out std_logic;
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pipe_rx2_status_o : out std_logic_vector(2 downto 0);
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pipe_rx2_phy_status_o : out std_logic;
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pipe_rx2_elec_idle_o : out std_logic;
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pipe_rx2_polarity_i : in std_logic;
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pipe_tx2_compliance_i : in std_logic;
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pipe_tx2_char_is_k_i : in std_logic_vector(1 downto 0);
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pipe_tx2_data_i : in std_logic_vector(15 downto 0);
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pipe_tx2_elec_idle_i : in std_logic;
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pipe_tx2_powerdown_i : in std_logic_vector(1 downto 0);
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pipe_rx2_char_is_k_i : in std_logic_vector(1 downto 0);
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pipe_rx2_data_i : in std_logic_vector(15 downto 0);
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pipe_rx2_valid_i : in std_logic;
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pipe_rx2_chanisaligned_i : in std_logic;
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pipe_rx2_status_i : in std_logic_vector(2 downto 0);
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pipe_rx2_phy_status_i : in std_logic;
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pipe_rx2_elec_idle_i : in std_logic;
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pipe_rx2_polarity_o : out std_logic;
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pipe_tx2_compliance_o : out std_logic;
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pipe_tx2_char_is_k_o : out std_logic_vector(1 downto 0);
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pipe_tx2_data_o : out std_logic_vector(15 downto 0);
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pipe_tx2_elec_idle_o : out std_logic;
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pipe_tx2_powerdown_o : out std_logic_vector(1 downto 0);
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-- Pipe Per-Lane Signals - Lane 3
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pipe_rx3_char_is_k_o : out std_logic_vector(1 downto 0);
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pipe_rx3_data_o : out std_logic_vector(15 downto 0);
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pipe_rx3_valid_o : out std_logic;
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pipe_rx3_chanisaligned_o : out std_logic;
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pipe_rx3_status_o : out std_logic_vector(2 downto 0);
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pipe_rx3_phy_status_o : out std_logic;
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pipe_rx3_elec_idle_o : out std_logic;
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pipe_rx3_polarity_i : in std_logic;
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pipe_tx3_compliance_i : in std_logic;
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pipe_tx3_char_is_k_i : in std_logic_vector(1 downto 0);
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pipe_tx3_data_i : in std_logic_vector(15 downto 0);
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pipe_tx3_elec_idle_i : in std_logic;
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pipe_tx3_powerdown_i : in std_logic_vector(1 downto 0);
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pipe_rx3_char_is_k_i : in std_logic_vector(1 downto 0);
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pipe_rx3_data_i : in std_logic_vector(15 downto 0);
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pipe_rx3_valid_i : in std_logic;
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pipe_rx3_chanisaligned_i : in std_logic;
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pipe_rx3_status_i : in std_logic_vector(2 downto 0);
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pipe_rx3_phy_status_i : in std_logic;
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pipe_rx3_elec_idle_i : in std_logic;
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pipe_rx3_polarity_o : out std_logic;
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pipe_tx3_compliance_o : out std_logic;
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pipe_tx3_char_is_k_o : out std_logic_vector(1 downto 0);
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pipe_tx3_data_o : out std_logic_vector(15 downto 0);
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pipe_tx3_elec_idle_o : out std_logic;
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pipe_tx3_powerdown_o : out std_logic_vector(1 downto 0);
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-- Pipe Per-Lane Signals - Lane 4
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pipe_rx4_char_is_k_o : out std_logic_vector(1 downto 0);
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pipe_rx4_data_o : out std_logic_vector(15 downto 0);
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pipe_rx4_valid_o : out std_logic;
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pipe_rx4_chanisaligned_o : out std_logic;
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pipe_rx4_status_o : out std_logic_vector(2 downto 0);
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pipe_rx4_phy_status_o : out std_logic;
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pipe_rx4_elec_idle_o : out std_logic;
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pipe_rx4_polarity_i : in std_logic;
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pipe_tx4_compliance_i : in std_logic;
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pipe_tx4_char_is_k_i : in std_logic_vector(1 downto 0);
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pipe_tx4_data_i : in std_logic_vector(15 downto 0);
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pipe_tx4_elec_idle_i : in std_logic;
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pipe_tx4_powerdown_i : in std_logic_vector(1 downto 0);
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pipe_rx4_char_is_k_i : in std_logic_vector(1 downto 0);
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pipe_rx4_data_i : in std_logic_vector(15 downto 0);
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pipe_rx4_valid_i : in std_logic;
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pipe_rx4_chanisaligned_i : in std_logic;
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pipe_rx4_status_i : in std_logic_vector(2 downto 0);
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pipe_rx4_phy_status_i : in std_logic;
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pipe_rx4_elec_idle_i : in std_logic;
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pipe_rx4_polarity_o : out std_logic;
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pipe_tx4_compliance_o : out std_logic;
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pipe_tx4_char_is_k_o : out std_logic_vector(1 downto 0);
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pipe_tx4_data_o : out std_logic_vector(15 downto 0);
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pipe_tx4_elec_idle_o : out std_logic;
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pipe_tx4_powerdown_o : out std_logic_vector(1 downto 0);
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-- Pipe Per-Lane Signals - Lane 5
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pipe_rx5_char_is_k_o : out std_logic_vector(1 downto 0);
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pipe_rx5_data_o : out std_logic_vector(15 downto 0);
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pipe_rx5_valid_o : out std_logic;
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pipe_rx5_chanisaligned_o : out std_logic;
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pipe_rx5_status_o : out std_logic_vector(2 downto 0);
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pipe_rx5_phy_status_o : out std_logic;
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pipe_rx5_elec_idle_o : out std_logic;
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pipe_rx5_polarity_i : in std_logic;
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pipe_tx5_compliance_i : in std_logic;
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pipe_tx5_char_is_k_i : in std_logic_vector(1 downto 0);
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pipe_tx5_data_i : in std_logic_vector(15 downto 0);
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pipe_tx5_elec_idle_i : in std_logic;
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pipe_tx5_powerdown_i : in std_logic_vector(1 downto 0);
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pipe_rx5_char_is_k_i : in std_logic_vector(1 downto 0);
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pipe_rx5_data_i : in std_logic_vector(15 downto 0);
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pipe_rx5_valid_i : in std_logic;
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pipe_rx5_chanisaligned_i : in std_logic;
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pipe_rx5_status_i : in std_logic_vector(2 downto 0);
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pipe_rx5_phy_status_i : in std_logic;
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pipe_rx5_elec_idle_i : in std_logic;
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pipe_rx5_polarity_o : out std_logic;
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pipe_tx5_compliance_o : out std_logic;
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pipe_tx5_char_is_k_o : out std_logic_vector(1 downto 0);
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pipe_tx5_data_o : out std_logic_vector(15 downto 0);
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pipe_tx5_elec_idle_o : out std_logic;
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pipe_tx5_powerdown_o : out std_logic_vector(1 downto 0);
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-- Pipe Per-Lane Signals - Lane 6
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pipe_rx6_char_is_k_o : out std_logic_vector(1 downto 0);
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pipe_rx6_data_o : out std_logic_vector(15 downto 0);
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pipe_rx6_valid_o : out std_logic;
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pipe_rx6_chanisaligned_o : out std_logic;
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pipe_rx6_status_o : out std_logic_vector(2 downto 0);
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pipe_rx6_phy_status_o : out std_logic;
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pipe_rx6_elec_idle_o : out std_logic;
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pipe_rx6_polarity_i : in std_logic;
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pipe_tx6_compliance_i : in std_logic;
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|
pipe_tx6_char_is_k_i : in std_logic_vector(1 downto 0);
|
282 |
|
|
pipe_tx6_data_i : in std_logic_vector(15 downto 0);
|
283 |
|
|
pipe_tx6_elec_idle_i : in std_logic;
|
284 |
|
|
pipe_tx6_powerdown_i : in std_logic_vector(1 downto 0);
|
285 |
|
|
|
286 |
|
|
pipe_rx6_char_is_k_i : in std_logic_vector(1 downto 0);
|
287 |
|
|
pipe_rx6_data_i : in std_logic_vector(15 downto 0);
|
288 |
|
|
pipe_rx6_valid_i : in std_logic;
|
289 |
|
|
pipe_rx6_chanisaligned_i : in std_logic;
|
290 |
|
|
pipe_rx6_status_i : in std_logic_vector(2 downto 0);
|
291 |
|
|
pipe_rx6_phy_status_i : in std_logic;
|
292 |
|
|
pipe_rx6_elec_idle_i : in std_logic;
|
293 |
|
|
pipe_rx6_polarity_o : out std_logic;
|
294 |
|
|
|
295 |
|
|
pipe_tx6_compliance_o : out std_logic;
|
296 |
|
|
pipe_tx6_char_is_k_o : out std_logic_vector(1 downto 0);
|
297 |
|
|
pipe_tx6_data_o : out std_logic_vector(15 downto 0);
|
298 |
|
|
pipe_tx6_elec_idle_o : out std_logic;
|
299 |
|
|
pipe_tx6_powerdown_o : out std_logic_vector(1 downto 0);
|
300 |
|
|
|
301 |
|
|
-- Pipe Per-Lane Signals - Lane 7
|
302 |
|
|
pipe_rx7_char_is_k_o : out std_logic_vector(1 downto 0);
|
303 |
|
|
pipe_rx7_data_o : out std_logic_vector(15 downto 0);
|
304 |
|
|
pipe_rx7_valid_o : out std_logic;
|
305 |
|
|
pipe_rx7_chanisaligned_o : out std_logic;
|
306 |
|
|
pipe_rx7_status_o : out std_logic_vector(2 downto 0);
|
307 |
|
|
pipe_rx7_phy_status_o : out std_logic;
|
308 |
|
|
pipe_rx7_elec_idle_o : out std_logic;
|
309 |
|
|
pipe_rx7_polarity_i : in std_logic;
|
310 |
|
|
|
311 |
|
|
pipe_tx7_compliance_i : in std_logic;
|
312 |
|
|
pipe_tx7_char_is_k_i : in std_logic_vector(1 downto 0);
|
313 |
|
|
pipe_tx7_data_i : in std_logic_vector(15 downto 0);
|
314 |
|
|
pipe_tx7_elec_idle_i : in std_logic;
|
315 |
|
|
pipe_tx7_powerdown_i : in std_logic_vector(1 downto 0);
|
316 |
|
|
|
317 |
|
|
pipe_rx7_char_is_k_i : in std_logic_vector(1 downto 0);
|
318 |
|
|
pipe_rx7_data_i : in std_logic_vector(15 downto 0);
|
319 |
|
|
pipe_rx7_valid_i : in std_logic;
|
320 |
|
|
pipe_rx7_chanisaligned_i : in std_logic;
|
321 |
|
|
pipe_rx7_status_i : in std_logic_vector(2 downto 0);
|
322 |
|
|
pipe_rx7_phy_status_i : in std_logic;
|
323 |
|
|
pipe_rx7_elec_idle_i : in std_logic;
|
324 |
|
|
pipe_rx7_polarity_o : out std_logic;
|
325 |
|
|
|
326 |
|
|
pipe_tx7_compliance_o : out std_logic;
|
327 |
|
|
pipe_tx7_char_is_k_o : out std_logic_vector(1 downto 0);
|
328 |
|
|
pipe_tx7_data_o : out std_logic_vector(15 downto 0);
|
329 |
|
|
pipe_tx7_elec_idle_o : out std_logic;
|
330 |
|
|
pipe_tx7_powerdown_o : out std_logic_vector(1 downto 0);
|
331 |
|
|
|
332 |
|
|
-- Non PIPE signals
|
333 |
|
|
pl_ltssm_state : in std_logic_vector(5 downto 0);
|
334 |
|
|
pipe_clk : in std_logic;
|
335 |
|
|
rst_n : in std_logic
|
336 |
|
|
);
|
337 |
|
|
end pcie_pipe_v6;
|
338 |
|
|
|
339 |
|
|
architecture v6_pcie of pcie_pipe_v6 is
|
340 |
|
|
component pcie_pipe_lane_v6 is
|
341 |
|
|
generic (
|
342 |
|
|
PIPE_PIPELINE_STAGES : integer := 0
|
343 |
|
|
);
|
344 |
|
|
port (
|
345 |
|
|
pipe_rx_char_is_k_o : out std_logic_vector(1 downto 0);
|
346 |
|
|
pipe_rx_data_o : out std_logic_vector(15 downto 0);
|
347 |
|
|
pipe_rx_valid_o : out std_logic;
|
348 |
|
|
pipe_rx_chanisaligned_o : out std_logic;
|
349 |
|
|
pipe_rx_status_o : out std_logic_vector(2 downto 0);
|
350 |
|
|
pipe_rx_phy_status_o : out std_logic;
|
351 |
|
|
pipe_rx_elec_idle_o : out std_logic;
|
352 |
|
|
pipe_rx_polarity_i : in std_logic;
|
353 |
|
|
pipe_tx_compliance_i : in std_logic;
|
354 |
|
|
pipe_tx_char_is_k_i : in std_logic_vector(1 downto 0);
|
355 |
|
|
pipe_tx_data_i : in std_logic_vector(15 downto 0);
|
356 |
|
|
pipe_tx_elec_idle_i : in std_logic;
|
357 |
|
|
pipe_tx_powerdown_i : in std_logic_vector(1 downto 0);
|
358 |
|
|
pipe_rx_char_is_k_i : in std_logic_vector(1 downto 0);
|
359 |
|
|
pipe_rx_data_i : in std_logic_vector(15 downto 0);
|
360 |
|
|
pipe_rx_valid_i : in std_logic;
|
361 |
|
|
pipe_rx_chanisaligned_i : in std_logic;
|
362 |
|
|
pipe_rx_status_i : in std_logic_vector(2 downto 0);
|
363 |
|
|
pipe_rx_phy_status_i : in std_logic;
|
364 |
|
|
pipe_rx_elec_idle_i : in std_logic;
|
365 |
|
|
pipe_rx_polarity_o : out std_logic;
|
366 |
|
|
pipe_tx_compliance_o : out std_logic;
|
367 |
|
|
pipe_tx_char_is_k_o : out std_logic_vector(1 downto 0);
|
368 |
|
|
pipe_tx_data_o : out std_logic_vector(15 downto 0);
|
369 |
|
|
pipe_tx_elec_idle_o : out std_logic;
|
370 |
|
|
pipe_tx_powerdown_o : out std_logic_vector(1 downto 0);
|
371 |
|
|
pipe_clk : in std_logic;
|
372 |
|
|
rst_n : in std_logic
|
373 |
|
|
);
|
374 |
|
|
end component;
|
375 |
|
|
|
376 |
|
|
component pcie_pipe_misc_v6 is
|
377 |
|
|
generic (
|
378 |
|
|
PIPE_PIPELINE_STAGES : integer := 0
|
379 |
|
|
);
|
380 |
|
|
port (
|
381 |
|
|
pipe_tx_rcvr_det_i : in std_logic;
|
382 |
|
|
pipe_tx_reset_i : in std_logic;
|
383 |
|
|
pipe_tx_rate_i : in std_logic;
|
384 |
|
|
pipe_tx_deemph_i : in std_logic;
|
385 |
|
|
pipe_tx_margin_i : in std_logic_vector(2 downto 0);
|
386 |
|
|
pipe_tx_swing_i : in std_logic;
|
387 |
|
|
pipe_tx_rcvr_det_o : out std_logic;
|
388 |
|
|
pipe_tx_reset_o : out std_logic;
|
389 |
|
|
pipe_tx_rate_o : out std_logic;
|
390 |
|
|
pipe_tx_deemph_o : out std_logic;
|
391 |
|
|
pipe_tx_margin_o : out std_logic_vector(2 downto 0);
|
392 |
|
|
pipe_tx_swing_o : out std_logic;
|
393 |
|
|
pipe_clk : in std_logic;
|
394 |
|
|
rst_n : in std_logic
|
395 |
|
|
);
|
396 |
|
|
end component;
|
397 |
|
|
|
398 |
|
|
--******************************************************************//
|
399 |
|
|
-- Reality check. //
|
400 |
|
|
--******************************************************************//
|
401 |
|
|
|
402 |
|
|
constant Tc2o : integer := 1; -- clock to out delay model
|
403 |
|
|
|
404 |
|
|
signal pipe_rx0_char_is_k_q : std_logic_vector(1 downto 0);
|
405 |
|
|
signal pipe_rx0_data_q : std_logic_vector(15 downto 0);
|
406 |
|
|
signal pipe_rx1_char_is_k_q : std_logic_vector(1 downto 0);
|
407 |
|
|
signal pipe_rx1_data_q : std_logic_vector(15 downto 0);
|
408 |
|
|
signal pipe_rx2_char_is_k_q : std_logic_vector(1 downto 0);
|
409 |
|
|
signal pipe_rx2_data_q : std_logic_vector(15 downto 0);
|
410 |
|
|
signal pipe_rx3_char_is_k_q : std_logic_vector(1 downto 0);
|
411 |
|
|
signal pipe_rx3_data_q : std_logic_vector(15 downto 0);
|
412 |
|
|
signal pipe_rx4_char_is_k_q : std_logic_vector(1 downto 0);
|
413 |
|
|
signal pipe_rx4_data_q : std_logic_vector(15 downto 0);
|
414 |
|
|
signal pipe_rx5_char_is_k_q : std_logic_vector(1 downto 0);
|
415 |
|
|
signal pipe_rx5_data_q : std_logic_vector(15 downto 0);
|
416 |
|
|
signal pipe_rx6_char_is_k_q : std_logic_vector(1 downto 0);
|
417 |
|
|
signal pipe_rx6_data_q : std_logic_vector(15 downto 0);
|
418 |
|
|
signal pipe_rx7_char_is_k_q : std_logic_vector(1 downto 0);
|
419 |
|
|
signal pipe_rx7_data_q : std_logic_vector(15 downto 0);
|
420 |
|
|
|
421 |
|
|
-- Declare intermediate signals for referenced outputs
|
422 |
|
|
signal pipe_tx_rcvr_det_o_v6pcie91 : std_logic;
|
423 |
|
|
signal pipe_tx_reset_o_v6pcie92 : std_logic;
|
424 |
|
|
signal pipe_tx_rate_o_v6pcie90 : std_logic;
|
425 |
|
|
signal pipe_tx_deemph_o_v6pcie88 : std_logic;
|
426 |
|
|
signal pipe_tx_margin_o_v6pcie89 : std_logic_vector(2 downto 0);
|
427 |
|
|
signal pipe_tx_swing_o_v6pcie93 : std_logic;
|
428 |
|
|
signal pipe_rx0_valid_o_v6pcie5 : std_logic;
|
429 |
|
|
signal pipe_rx0_chanisaligned_o_v6pcie0 : std_logic;
|
430 |
|
|
signal pipe_rx0_status_o_v6pcie4 : std_logic_vector(2 downto 0);
|
431 |
|
|
signal pipe_rx0_phy_status_o_v6pcie2 : std_logic;
|
432 |
|
|
signal pipe_rx0_elec_idle_o_v6pcie1 : std_logic;
|
433 |
|
|
signal pipe_rx0_polarity_o_v6pcie3 : std_logic;
|
434 |
|
|
signal pipe_tx0_compliance_o_v6pcie49 : std_logic;
|
435 |
|
|
signal pipe_tx0_char_is_k_o_v6pcie48 : std_logic_vector(1 downto 0);
|
436 |
|
|
signal pipe_tx0_data_o_v6pcie50 : std_logic_vector(15 downto 0);
|
437 |
|
|
signal pipe_tx0_elec_idle_o_v6pcie51 : std_logic;
|
438 |
|
|
signal pipe_tx0_powerdown_o_v6pcie52 : std_logic_vector(1 downto 0);
|
439 |
|
|
signal pipe_rx1_valid_o_v6pcie11 : std_logic;
|
440 |
|
|
signal pipe_rx1_chanisaligned_o_v6pcie6 : std_logic;
|
441 |
|
|
signal pipe_rx1_status_o_v6pcie10 : std_logic_vector(2 downto 0);
|
442 |
|
|
signal pipe_rx1_phy_status_o_v6pcie8 : std_logic;
|
443 |
|
|
signal pipe_rx1_elec_idle_o_v6pcie7 : std_logic;
|
444 |
|
|
signal pipe_rx1_polarity_o_v6pcie9 : std_logic;
|
445 |
|
|
signal pipe_tx1_compliance_o_v6pcie54 : std_logic;
|
446 |
|
|
signal pipe_tx1_char_is_k_o_v6pcie53 : std_logic_vector(1 downto 0);
|
447 |
|
|
signal pipe_tx1_data_o_v6pcie55 : std_logic_vector(15 downto 0);
|
448 |
|
|
signal pipe_tx1_elec_idle_o_v6pcie56 : std_logic;
|
449 |
|
|
signal pipe_tx1_powerdown_o_v6pcie57 : std_logic_vector(1 downto 0);
|
450 |
|
|
signal pipe_rx2_valid_o_v6pcie17 : std_logic;
|
451 |
|
|
signal pipe_rx2_chanisaligned_o_v6pcie12 : std_logic;
|
452 |
|
|
signal pipe_rx2_status_o_v6pcie16 : std_logic_vector(2 downto 0);
|
453 |
|
|
signal pipe_rx2_phy_status_o_v6pcie14 : std_logic;
|
454 |
|
|
signal pipe_rx2_elec_idle_o_v6pcie13 : std_logic;
|
455 |
|
|
signal pipe_rx2_polarity_o_v6pcie15 : std_logic;
|
456 |
|
|
signal pipe_tx2_compliance_o_v6pcie59 : std_logic;
|
457 |
|
|
signal pipe_tx2_char_is_k_o_v6pcie58 : std_logic_vector(1 downto 0);
|
458 |
|
|
signal pipe_tx2_data_o_v6pcie60 : std_logic_vector(15 downto 0);
|
459 |
|
|
signal pipe_tx2_elec_idle_o_v6pcie61 : std_logic;
|
460 |
|
|
signal pipe_tx2_powerdown_o_v6pcie62 : std_logic_vector(1 downto 0);
|
461 |
|
|
signal pipe_rx3_valid_o_v6pcie23 : std_logic;
|
462 |
|
|
signal pipe_rx3_chanisaligned_o_v6pcie18 : std_logic;
|
463 |
|
|
signal pipe_rx3_status_o_v6pcie22 : std_logic_vector(2 downto 0);
|
464 |
|
|
signal pipe_rx3_phy_status_o_v6pcie20 : std_logic;
|
465 |
|
|
signal pipe_rx3_elec_idle_o_v6pcie19 : std_logic;
|
466 |
|
|
signal pipe_rx3_polarity_o_v6pcie21 : std_logic;
|
467 |
|
|
signal pipe_tx3_compliance_o_v6pcie64 : std_logic;
|
468 |
|
|
signal pipe_tx3_char_is_k_o_v6pcie63 : std_logic_vector(1 downto 0);
|
469 |
|
|
signal pipe_tx3_data_o_v6pcie65 : std_logic_vector(15 downto 0);
|
470 |
|
|
signal pipe_tx3_elec_idle_o_v6pcie66 : std_logic;
|
471 |
|
|
signal pipe_tx3_powerdown_o_v6pcie67 : std_logic_vector(1 downto 0);
|
472 |
|
|
signal pipe_rx4_valid_o_v6pcie29 : std_logic;
|
473 |
|
|
signal pipe_rx4_chanisaligned_o_v6pcie24 : std_logic;
|
474 |
|
|
signal pipe_rx4_status_o_v6pcie28 : std_logic_vector(2 downto 0);
|
475 |
|
|
signal pipe_rx4_phy_status_o_v6pcie26 : std_logic;
|
476 |
|
|
signal pipe_rx4_elec_idle_o_v6pcie25 : std_logic;
|
477 |
|
|
signal pipe_rx4_polarity_o_v6pcie27 : std_logic;
|
478 |
|
|
signal pipe_tx4_compliance_o_v6pcie69 : std_logic;
|
479 |
|
|
signal pipe_tx4_char_is_k_o_v6pcie68 : std_logic_vector(1 downto 0);
|
480 |
|
|
signal pipe_tx4_data_o_v6pcie70 : std_logic_vector(15 downto 0);
|
481 |
|
|
signal pipe_tx4_elec_idle_o_v6pcie71 : std_logic;
|
482 |
|
|
signal pipe_tx4_powerdown_o_v6pcie72 : std_logic_vector(1 downto 0);
|
483 |
|
|
signal pipe_rx5_valid_o_v6pcie35 : std_logic;
|
484 |
|
|
signal pipe_rx5_chanisaligned_o_v6pcie30 : std_logic;
|
485 |
|
|
signal pipe_rx5_status_o_v6pcie34 : std_logic_vector(2 downto 0);
|
486 |
|
|
signal pipe_rx5_phy_status_o_v6pcie32 : std_logic;
|
487 |
|
|
signal pipe_rx5_elec_idle_o_v6pcie31 : std_logic;
|
488 |
|
|
signal pipe_rx5_polarity_o_v6pcie33 : std_logic;
|
489 |
|
|
signal pipe_tx5_compliance_o_v6pcie74 : std_logic;
|
490 |
|
|
signal pipe_tx5_char_is_k_o_v6pcie73 : std_logic_vector(1 downto 0);
|
491 |
|
|
signal pipe_tx5_data_o_v6pcie75 : std_logic_vector(15 downto 0);
|
492 |
|
|
signal pipe_tx5_elec_idle_o_v6pcie76 : std_logic;
|
493 |
|
|
signal pipe_tx5_powerdown_o_v6pcie77 : std_logic_vector(1 downto 0);
|
494 |
|
|
signal pipe_rx6_valid_o_v6pcie41 : std_logic;
|
495 |
|
|
signal pipe_rx6_chanisaligned_o_v6pcie36 : std_logic;
|
496 |
|
|
signal pipe_rx6_status_o_v6pcie40 : std_logic_vector(2 downto 0);
|
497 |
|
|
signal pipe_rx6_phy_status_o_v6pcie38 : std_logic;
|
498 |
|
|
signal pipe_rx6_elec_idle_o_v6pcie37 : std_logic;
|
499 |
|
|
signal pipe_rx6_polarity_o_v6pcie39 : std_logic;
|
500 |
|
|
signal pipe_tx6_compliance_o_v6pcie79 : std_logic;
|
501 |
|
|
signal pipe_tx6_char_is_k_o_v6pcie78 : std_logic_vector(1 downto 0);
|
502 |
|
|
signal pipe_tx6_data_o_v6pcie80 : std_logic_vector(15 downto 0);
|
503 |
|
|
signal pipe_tx6_elec_idle_o_v6pcie81 : std_logic;
|
504 |
|
|
signal pipe_tx6_powerdown_o_v6pcie82 : std_logic_vector(1 downto 0);
|
505 |
|
|
signal pipe_rx7_valid_o_v6pcie47 : std_logic;
|
506 |
|
|
signal pipe_rx7_chanisaligned_o_v6pcie42 : std_logic;
|
507 |
|
|
signal pipe_rx7_status_o_v6pcie46 : std_logic_vector(2 downto 0);
|
508 |
|
|
signal pipe_rx7_phy_status_o_v6pcie44 : std_logic;
|
509 |
|
|
signal pipe_rx7_elec_idle_o_v6pcie43 : std_logic;
|
510 |
|
|
signal pipe_rx7_polarity_o_v6pcie45 : std_logic;
|
511 |
|
|
signal pipe_tx7_compliance_o_v6pcie84 : std_logic;
|
512 |
|
|
signal pipe_tx7_char_is_k_o_v6pcie83 : std_logic_vector(1 downto 0);
|
513 |
|
|
signal pipe_tx7_data_o_v6pcie85 : std_logic_vector(15 downto 0);
|
514 |
|
|
signal pipe_tx7_elec_idle_o_v6pcie86 : std_logic;
|
515 |
|
|
signal pipe_tx7_powerdown_o_v6pcie87 : std_logic_vector(1 downto 0);
|
516 |
|
|
begin
|
517 |
|
|
-- Drive referenced outputs
|
518 |
|
|
pipe_tx_rcvr_det_o <= pipe_tx_rcvr_det_o_v6pcie91;
|
519 |
|
|
pipe_tx_reset_o <= pipe_tx_reset_o_v6pcie92;
|
520 |
|
|
pipe_tx_rate_o <= pipe_tx_rate_o_v6pcie90;
|
521 |
|
|
pipe_tx_deemph_o <= pipe_tx_deemph_o_v6pcie88;
|
522 |
|
|
pipe_tx_margin_o <= pipe_tx_margin_o_v6pcie89;
|
523 |
|
|
pipe_tx_swing_o <= pipe_tx_swing_o_v6pcie93;
|
524 |
|
|
pipe_rx0_valid_o <= pipe_rx0_valid_o_v6pcie5;
|
525 |
|
|
pipe_rx0_chanisaligned_o <= pipe_rx0_chanisaligned_o_v6pcie0;
|
526 |
|
|
pipe_rx0_status_o <= pipe_rx0_status_o_v6pcie4;
|
527 |
|
|
pipe_rx0_phy_status_o <= pipe_rx0_phy_status_o_v6pcie2;
|
528 |
|
|
pipe_rx0_elec_idle_o <= pipe_rx0_elec_idle_o_v6pcie1;
|
529 |
|
|
pipe_rx0_polarity_o <= pipe_rx0_polarity_o_v6pcie3;
|
530 |
|
|
pipe_tx0_compliance_o <= pipe_tx0_compliance_o_v6pcie49;
|
531 |
|
|
pipe_tx0_char_is_k_o <= pipe_tx0_char_is_k_o_v6pcie48;
|
532 |
|
|
pipe_tx0_data_o <= pipe_tx0_data_o_v6pcie50;
|
533 |
|
|
pipe_tx0_elec_idle_o <= pipe_tx0_elec_idle_o_v6pcie51;
|
534 |
|
|
pipe_tx0_powerdown_o <= pipe_tx0_powerdown_o_v6pcie52;
|
535 |
|
|
pipe_rx1_valid_o <= pipe_rx1_valid_o_v6pcie11;
|
536 |
|
|
pipe_rx1_chanisaligned_o <= pipe_rx1_chanisaligned_o_v6pcie6;
|
537 |
|
|
pipe_rx1_status_o <= pipe_rx1_status_o_v6pcie10;
|
538 |
|
|
pipe_rx1_phy_status_o <= pipe_rx1_phy_status_o_v6pcie8;
|
539 |
|
|
pipe_rx1_elec_idle_o <= pipe_rx1_elec_idle_o_v6pcie7;
|
540 |
|
|
pipe_rx1_polarity_o <= pipe_rx1_polarity_o_v6pcie9;
|
541 |
|
|
pipe_tx1_compliance_o <= pipe_tx1_compliance_o_v6pcie54;
|
542 |
|
|
pipe_tx1_char_is_k_o <= pipe_tx1_char_is_k_o_v6pcie53;
|
543 |
|
|
pipe_tx1_data_o <= pipe_tx1_data_o_v6pcie55;
|
544 |
|
|
pipe_tx1_elec_idle_o <= pipe_tx1_elec_idle_o_v6pcie56;
|
545 |
|
|
pipe_tx1_powerdown_o <= pipe_tx1_powerdown_o_v6pcie57;
|
546 |
|
|
pipe_rx2_valid_o <= pipe_rx2_valid_o_v6pcie17;
|
547 |
|
|
pipe_rx2_chanisaligned_o <= pipe_rx2_chanisaligned_o_v6pcie12;
|
548 |
|
|
pipe_rx2_status_o <= pipe_rx2_status_o_v6pcie16;
|
549 |
|
|
pipe_rx2_phy_status_o <= pipe_rx2_phy_status_o_v6pcie14;
|
550 |
|
|
pipe_rx2_elec_idle_o <= pipe_rx2_elec_idle_o_v6pcie13;
|
551 |
|
|
pipe_rx2_polarity_o <= pipe_rx2_polarity_o_v6pcie15;
|
552 |
|
|
pipe_tx2_compliance_o <= pipe_tx2_compliance_o_v6pcie59;
|
553 |
|
|
pipe_tx2_char_is_k_o <= pipe_tx2_char_is_k_o_v6pcie58;
|
554 |
|
|
pipe_tx2_data_o <= pipe_tx2_data_o_v6pcie60;
|
555 |
|
|
pipe_tx2_elec_idle_o <= pipe_tx2_elec_idle_o_v6pcie61;
|
556 |
|
|
pipe_tx2_powerdown_o <= pipe_tx2_powerdown_o_v6pcie62;
|
557 |
|
|
pipe_rx3_valid_o <= pipe_rx3_valid_o_v6pcie23;
|
558 |
|
|
pipe_rx3_chanisaligned_o <= pipe_rx3_chanisaligned_o_v6pcie18;
|
559 |
|
|
pipe_rx3_status_o <= pipe_rx3_status_o_v6pcie22;
|
560 |
|
|
pipe_rx3_phy_status_o <= pipe_rx3_phy_status_o_v6pcie20;
|
561 |
|
|
pipe_rx3_elec_idle_o <= pipe_rx3_elec_idle_o_v6pcie19;
|
562 |
|
|
pipe_rx3_polarity_o <= pipe_rx3_polarity_o_v6pcie21;
|
563 |
|
|
pipe_tx3_compliance_o <= pipe_tx3_compliance_o_v6pcie64;
|
564 |
|
|
pipe_tx3_char_is_k_o <= pipe_tx3_char_is_k_o_v6pcie63;
|
565 |
|
|
pipe_tx3_data_o <= pipe_tx3_data_o_v6pcie65;
|
566 |
|
|
pipe_tx3_elec_idle_o <= pipe_tx3_elec_idle_o_v6pcie66;
|
567 |
|
|
pipe_tx3_powerdown_o <= pipe_tx3_powerdown_o_v6pcie67;
|
568 |
|
|
pipe_rx4_valid_o <= pipe_rx4_valid_o_v6pcie29;
|
569 |
|
|
pipe_rx4_chanisaligned_o <= pipe_rx4_chanisaligned_o_v6pcie24;
|
570 |
|
|
pipe_rx4_status_o <= pipe_rx4_status_o_v6pcie28;
|
571 |
|
|
pipe_rx4_phy_status_o <= pipe_rx4_phy_status_o_v6pcie26;
|
572 |
|
|
pipe_rx4_elec_idle_o <= pipe_rx4_elec_idle_o_v6pcie25;
|
573 |
|
|
pipe_rx4_polarity_o <= pipe_rx4_polarity_o_v6pcie27;
|
574 |
|
|
pipe_tx4_compliance_o <= pipe_tx4_compliance_o_v6pcie69;
|
575 |
|
|
pipe_tx4_char_is_k_o <= pipe_tx4_char_is_k_o_v6pcie68;
|
576 |
|
|
pipe_tx4_data_o <= pipe_tx4_data_o_v6pcie70;
|
577 |
|
|
pipe_tx4_elec_idle_o <= pipe_tx4_elec_idle_o_v6pcie71;
|
578 |
|
|
pipe_tx4_powerdown_o <= pipe_tx4_powerdown_o_v6pcie72;
|
579 |
|
|
pipe_rx5_valid_o <= pipe_rx5_valid_o_v6pcie35;
|
580 |
|
|
pipe_rx5_chanisaligned_o <= pipe_rx5_chanisaligned_o_v6pcie30;
|
581 |
|
|
pipe_rx5_status_o <= pipe_rx5_status_o_v6pcie34;
|
582 |
|
|
pipe_rx5_phy_status_o <= pipe_rx5_phy_status_o_v6pcie32;
|
583 |
|
|
pipe_rx5_elec_idle_o <= pipe_rx5_elec_idle_o_v6pcie31;
|
584 |
|
|
pipe_rx5_polarity_o <= pipe_rx5_polarity_o_v6pcie33;
|
585 |
|
|
pipe_tx5_compliance_o <= pipe_tx5_compliance_o_v6pcie74;
|
586 |
|
|
pipe_tx5_char_is_k_o <= pipe_tx5_char_is_k_o_v6pcie73;
|
587 |
|
|
pipe_tx5_data_o <= pipe_tx5_data_o_v6pcie75;
|
588 |
|
|
pipe_tx5_elec_idle_o <= pipe_tx5_elec_idle_o_v6pcie76;
|
589 |
|
|
pipe_tx5_powerdown_o <= pipe_tx5_powerdown_o_v6pcie77;
|
590 |
|
|
pipe_rx6_valid_o <= pipe_rx6_valid_o_v6pcie41;
|
591 |
|
|
pipe_rx6_chanisaligned_o <= pipe_rx6_chanisaligned_o_v6pcie36;
|
592 |
|
|
pipe_rx6_status_o <= pipe_rx6_status_o_v6pcie40;
|
593 |
|
|
pipe_rx6_phy_status_o <= pipe_rx6_phy_status_o_v6pcie38;
|
594 |
|
|
pipe_rx6_elec_idle_o <= pipe_rx6_elec_idle_o_v6pcie37;
|
595 |
|
|
pipe_rx6_polarity_o <= pipe_rx6_polarity_o_v6pcie39;
|
596 |
|
|
pipe_tx6_compliance_o <= pipe_tx6_compliance_o_v6pcie79;
|
597 |
|
|
pipe_tx6_char_is_k_o <= pipe_tx6_char_is_k_o_v6pcie78;
|
598 |
|
|
pipe_tx6_data_o <= pipe_tx6_data_o_v6pcie80;
|
599 |
|
|
pipe_tx6_elec_idle_o <= pipe_tx6_elec_idle_o_v6pcie81;
|
600 |
|
|
pipe_tx6_powerdown_o <= pipe_tx6_powerdown_o_v6pcie82;
|
601 |
|
|
pipe_rx7_valid_o <= pipe_rx7_valid_o_v6pcie47;
|
602 |
|
|
pipe_rx7_chanisaligned_o <= pipe_rx7_chanisaligned_o_v6pcie42;
|
603 |
|
|
pipe_rx7_status_o <= pipe_rx7_status_o_v6pcie46;
|
604 |
|
|
pipe_rx7_phy_status_o <= pipe_rx7_phy_status_o_v6pcie44;
|
605 |
|
|
pipe_rx7_elec_idle_o <= pipe_rx7_elec_idle_o_v6pcie43;
|
606 |
|
|
pipe_rx7_polarity_o <= pipe_rx7_polarity_o_v6pcie45;
|
607 |
|
|
pipe_tx7_compliance_o <= pipe_tx7_compliance_o_v6pcie84;
|
608 |
|
|
pipe_tx7_char_is_k_o <= pipe_tx7_char_is_k_o_v6pcie83;
|
609 |
|
|
pipe_tx7_data_o <= pipe_tx7_data_o_v6pcie85;
|
610 |
|
|
pipe_tx7_elec_idle_o <= pipe_tx7_elec_idle_o_v6pcie86;
|
611 |
|
|
pipe_tx7_powerdown_o <= pipe_tx7_powerdown_o_v6pcie87;
|
612 |
|
|
|
613 |
|
|
--synthesis translate_off
|
614 |
|
|
-- initial begin
|
615 |
|
|
-- $display("[%t] %m NO_OF_LANES %0d PIPE_PIPELINE_STAGES %0d", $time, NO_OF_LANES, PIPE_PIPELINE_STAGES);
|
616 |
|
|
-- end
|
617 |
|
|
--synthesis translate_on
|
618 |
|
|
|
619 |
|
|
pipe_misc_i : pcie_pipe_misc_v6
|
620 |
|
|
generic map (
|
621 |
|
|
PIPE_PIPELINE_STAGES => PIPE_PIPELINE_STAGES
|
622 |
|
|
)
|
623 |
|
|
port map (
|
624 |
|
|
|
625 |
|
|
pipe_tx_rcvr_det_i => pipe_tx_rcvr_det_i,
|
626 |
|
|
pipe_tx_reset_i => pipe_tx_reset_i,
|
627 |
|
|
pipe_tx_rate_i => pipe_tx_rate_i,
|
628 |
|
|
pipe_tx_deemph_i => pipe_tx_deemph_i,
|
629 |
|
|
pipe_tx_margin_i => pipe_tx_margin_i,
|
630 |
|
|
pipe_tx_swing_i => pipe_tx_swing_i,
|
631 |
|
|
|
632 |
|
|
pipe_tx_rcvr_det_o => pipe_tx_rcvr_det_o_v6pcie91,
|
633 |
|
|
pipe_tx_reset_o => pipe_tx_reset_o_v6pcie92,
|
634 |
|
|
pipe_tx_rate_o => pipe_tx_rate_o_v6pcie90,
|
635 |
|
|
pipe_tx_deemph_o => pipe_tx_deemph_o_v6pcie88,
|
636 |
|
|
pipe_tx_margin_o => pipe_tx_margin_o_v6pcie89,
|
637 |
|
|
pipe_tx_swing_o => pipe_tx_swing_o_v6pcie93,
|
638 |
|
|
|
639 |
|
|
pipe_clk => pipe_clk,
|
640 |
|
|
rst_n => rst_n
|
641 |
|
|
);
|
642 |
|
|
|
643 |
|
|
pipe_lane_0_i : pcie_pipe_lane_v6
|
644 |
|
|
generic map (
|
645 |
|
|
PIPE_PIPELINE_STAGES => PIPE_PIPELINE_STAGES
|
646 |
|
|
)
|
647 |
|
|
port map (
|
648 |
|
|
|
649 |
|
|
pipe_rx_char_is_k_o => pipe_rx0_char_is_k_q,
|
650 |
|
|
pipe_rx_data_o => pipe_rx0_data_q,
|
651 |
|
|
pipe_rx_valid_o => pipe_rx0_valid_o_v6pcie5,
|
652 |
|
|
pipe_rx_chanisaligned_o => pipe_rx0_chanisaligned_o_v6pcie0,
|
653 |
|
|
pipe_rx_status_o => pipe_rx0_status_o_v6pcie4,
|
654 |
|
|
pipe_rx_phy_status_o => pipe_rx0_phy_status_o_v6pcie2,
|
655 |
|
|
pipe_rx_elec_idle_o => pipe_rx0_elec_idle_o_v6pcie1,
|
656 |
|
|
pipe_rx_polarity_i => pipe_rx0_polarity_i,
|
657 |
|
|
pipe_tx_compliance_i => pipe_tx0_compliance_i,
|
658 |
|
|
pipe_tx_char_is_k_i => pipe_tx0_char_is_k_i,
|
659 |
|
|
pipe_tx_data_i => pipe_tx0_data_i,
|
660 |
|
|
pipe_tx_elec_idle_i => pipe_tx0_elec_idle_i,
|
661 |
|
|
pipe_tx_powerdown_i => pipe_tx0_powerdown_i,
|
662 |
|
|
|
663 |
|
|
pipe_rx_char_is_k_i => pipe_rx0_char_is_k_i,
|
664 |
|
|
pipe_rx_data_i => pipe_rx0_data_i,
|
665 |
|
|
pipe_rx_valid_i => pipe_rx0_valid_i,
|
666 |
|
|
pipe_rx_chanisaligned_i => pipe_rx0_chanisaligned_i,
|
667 |
|
|
pipe_rx_status_i => pipe_rx0_status_i,
|
668 |
|
|
pipe_rx_phy_status_i => pipe_rx0_phy_status_i,
|
669 |
|
|
pipe_rx_elec_idle_i => pipe_rx0_elec_idle_i,
|
670 |
|
|
pipe_rx_polarity_o => pipe_rx0_polarity_o_v6pcie3,
|
671 |
|
|
pipe_tx_compliance_o => pipe_tx0_compliance_o_v6pcie49,
|
672 |
|
|
pipe_tx_char_is_k_o => pipe_tx0_char_is_k_o_v6pcie48,
|
673 |
|
|
pipe_tx_data_o => pipe_tx0_data_o_v6pcie50,
|
674 |
|
|
pipe_tx_elec_idle_o => pipe_tx0_elec_idle_o_v6pcie51,
|
675 |
|
|
pipe_tx_powerdown_o => pipe_tx0_powerdown_o_v6pcie52,
|
676 |
|
|
|
677 |
|
|
pipe_clk => pipe_clk,
|
678 |
|
|
rst_n => rst_n
|
679 |
|
|
);
|
680 |
|
|
|
681 |
|
|
v6pcie94 : if (NO_OF_LANES >= 2) generate
|
682 |
|
|
|
683 |
|
|
pipe_lane_1_i : pcie_pipe_lane_v6
|
684 |
|
|
generic map (
|
685 |
|
|
PIPE_PIPELINE_STAGES => PIPE_PIPELINE_STAGES
|
686 |
|
|
)
|
687 |
|
|
port map (
|
688 |
|
|
|
689 |
|
|
pipe_rx_char_is_k_o => pipe_rx1_char_is_k_q,
|
690 |
|
|
pipe_rx_data_o => pipe_rx1_data_q,
|
691 |
|
|
pipe_rx_valid_o => pipe_rx1_valid_o_v6pcie11,
|
692 |
|
|
pipe_rx_chanisaligned_o => pipe_rx1_chanisaligned_o_v6pcie6,
|
693 |
|
|
pipe_rx_status_o => pipe_rx1_status_o_v6pcie10,
|
694 |
|
|
pipe_rx_phy_status_o => pipe_rx1_phy_status_o_v6pcie8,
|
695 |
|
|
pipe_rx_elec_idle_o => pipe_rx1_elec_idle_o_v6pcie7,
|
696 |
|
|
pipe_rx_polarity_i => pipe_rx1_polarity_i,
|
697 |
|
|
pipe_tx_compliance_i => pipe_tx1_compliance_i,
|
698 |
|
|
pipe_tx_char_is_k_i => pipe_tx1_char_is_k_i,
|
699 |
|
|
pipe_tx_data_i => pipe_tx1_data_i,
|
700 |
|
|
pipe_tx_elec_idle_i => pipe_tx1_elec_idle_i,
|
701 |
|
|
pipe_tx_powerdown_i => pipe_tx1_powerdown_i,
|
702 |
|
|
|
703 |
|
|
pipe_rx_char_is_k_i => pipe_rx1_char_is_k_i,
|
704 |
|
|
pipe_rx_data_i => pipe_rx1_data_i,
|
705 |
|
|
pipe_rx_valid_i => pipe_rx1_valid_i,
|
706 |
|
|
pipe_rx_chanisaligned_i => pipe_rx1_chanisaligned_i,
|
707 |
|
|
pipe_rx_status_i => pipe_rx1_status_i,
|
708 |
|
|
pipe_rx_phy_status_i => pipe_rx1_phy_status_i,
|
709 |
|
|
pipe_rx_elec_idle_i => pipe_rx1_elec_idle_i,
|
710 |
|
|
pipe_rx_polarity_o => pipe_rx1_polarity_o_v6pcie9,
|
711 |
|
|
pipe_tx_compliance_o => pipe_tx1_compliance_o_v6pcie54,
|
712 |
|
|
pipe_tx_char_is_k_o => pipe_tx1_char_is_k_o_v6pcie53,
|
713 |
|
|
pipe_tx_data_o => pipe_tx1_data_o_v6pcie55,
|
714 |
|
|
pipe_tx_elec_idle_o => pipe_tx1_elec_idle_o_v6pcie56,
|
715 |
|
|
pipe_tx_powerdown_o => pipe_tx1_powerdown_o_v6pcie57,
|
716 |
|
|
|
717 |
|
|
pipe_clk => pipe_clk,
|
718 |
|
|
rst_n => rst_n
|
719 |
|
|
);
|
720 |
|
|
|
721 |
|
|
end generate;
|
722 |
|
|
v6pcie95 : if (not(NO_OF_LANES >= 2)) generate
|
723 |
|
|
--<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<
|
724 |
|
|
--<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<
|
725 |
|
|
pipe_rx1_char_is_k_q <= "00";
|
726 |
|
|
pipe_rx1_data_q <= "0000000000000000";
|
727 |
|
|
pipe_rx1_valid_o_v6pcie11 <= '0';
|
728 |
|
|
pipe_rx1_chanisaligned_o_v6pcie6 <= '0';
|
729 |
|
|
pipe_rx1_status_o_v6pcie10 <= "000";
|
730 |
|
|
pipe_rx1_phy_status_o_v6pcie8 <= '0';
|
731 |
|
|
pipe_rx1_elec_idle_o_v6pcie7 <= '1';
|
732 |
|
|
pipe_rx1_polarity_o_v6pcie9 <= '0';
|
733 |
|
|
pipe_tx1_compliance_o_v6pcie54 <= '0';
|
734 |
|
|
pipe_tx1_char_is_k_o_v6pcie53 <= "00";
|
735 |
|
|
pipe_tx1_data_o_v6pcie55 <= "0000000000000000";
|
736 |
|
|
pipe_tx1_elec_idle_o_v6pcie56 <= '1';
|
737 |
|
|
pipe_tx1_powerdown_o_v6pcie57 <= "00";
|
738 |
|
|
--<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<
|
739 |
|
|
--<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<
|
740 |
|
|
|
741 |
|
|
end generate;
|
742 |
|
|
v6pcie96 : if (NO_OF_LANES >= 4) generate
|
743 |
|
|
pipe_lane_2_i : pcie_pipe_lane_v6
|
744 |
|
|
generic map (
|
745 |
|
|
PIPE_PIPELINE_STAGES => PIPE_PIPELINE_STAGES
|
746 |
|
|
)
|
747 |
|
|
port map (
|
748 |
|
|
|
749 |
|
|
pipe_rx_char_is_k_o => pipe_rx2_char_is_k_q,
|
750 |
|
|
pipe_rx_data_o => pipe_rx2_data_q,
|
751 |
|
|
pipe_rx_valid_o => pipe_rx2_valid_o_v6pcie17,
|
752 |
|
|
pipe_rx_chanisaligned_o => pipe_rx2_chanisaligned_o_v6pcie12,
|
753 |
|
|
pipe_rx_status_o => pipe_rx2_status_o_v6pcie16,
|
754 |
|
|
pipe_rx_phy_status_o => pipe_rx2_phy_status_o_v6pcie14,
|
755 |
|
|
pipe_rx_elec_idle_o => pipe_rx2_elec_idle_o_v6pcie13,
|
756 |
|
|
pipe_rx_polarity_i => pipe_rx2_polarity_i,
|
757 |
|
|
pipe_tx_compliance_i => pipe_tx2_compliance_i,
|
758 |
|
|
pipe_tx_char_is_k_i => pipe_tx2_char_is_k_i,
|
759 |
|
|
pipe_tx_data_i => pipe_tx2_data_i,
|
760 |
|
|
pipe_tx_elec_idle_i => pipe_tx2_elec_idle_i,
|
761 |
|
|
pipe_tx_powerdown_i => pipe_tx2_powerdown_i,
|
762 |
|
|
|
763 |
|
|
pipe_rx_char_is_k_i => pipe_rx2_char_is_k_i,
|
764 |
|
|
pipe_rx_data_i => pipe_rx2_data_i,
|
765 |
|
|
pipe_rx_valid_i => pipe_rx2_valid_i,
|
766 |
|
|
pipe_rx_chanisaligned_i => pipe_rx2_chanisaligned_i,
|
767 |
|
|
pipe_rx_status_i => pipe_rx2_status_i,
|
768 |
|
|
pipe_rx_phy_status_i => pipe_rx2_phy_status_i,
|
769 |
|
|
pipe_rx_elec_idle_i => pipe_rx2_elec_idle_i,
|
770 |
|
|
pipe_rx_polarity_o => pipe_rx2_polarity_o_v6pcie15,
|
771 |
|
|
pipe_tx_compliance_o => pipe_tx2_compliance_o_v6pcie59,
|
772 |
|
|
pipe_tx_char_is_k_o => pipe_tx2_char_is_k_o_v6pcie58,
|
773 |
|
|
pipe_tx_data_o => pipe_tx2_data_o_v6pcie60,
|
774 |
|
|
pipe_tx_elec_idle_o => pipe_tx2_elec_idle_o_v6pcie61,
|
775 |
|
|
pipe_tx_powerdown_o => pipe_tx2_powerdown_o_v6pcie62,
|
776 |
|
|
|
777 |
|
|
pipe_clk => pipe_clk,
|
778 |
|
|
rst_n => rst_n
|
779 |
|
|
);
|
780 |
|
|
|
781 |
|
|
pipe_lane_3_i : pcie_pipe_lane_v6
|
782 |
|
|
generic map (
|
783 |
|
|
PIPE_PIPELINE_STAGES => PIPE_PIPELINE_STAGES
|
784 |
|
|
)
|
785 |
|
|
port map (
|
786 |
|
|
|
787 |
|
|
pipe_rx_char_is_k_o => pipe_rx3_char_is_k_q,
|
788 |
|
|
pipe_rx_data_o => pipe_rx3_data_q,
|
789 |
|
|
pipe_rx_valid_o => pipe_rx3_valid_o_v6pcie23,
|
790 |
|
|
pipe_rx_chanisaligned_o => pipe_rx3_chanisaligned_o_v6pcie18,
|
791 |
|
|
pipe_rx_status_o => pipe_rx3_status_o_v6pcie22,
|
792 |
|
|
pipe_rx_phy_status_o => pipe_rx3_phy_status_o_v6pcie20,
|
793 |
|
|
pipe_rx_elec_idle_o => pipe_rx3_elec_idle_o_v6pcie19,
|
794 |
|
|
pipe_rx_polarity_i => pipe_rx3_polarity_i,
|
795 |
|
|
pipe_tx_compliance_i => pipe_tx3_compliance_i,
|
796 |
|
|
pipe_tx_char_is_k_i => pipe_tx3_char_is_k_i,
|
797 |
|
|
pipe_tx_data_i => pipe_tx3_data_i,
|
798 |
|
|
pipe_tx_elec_idle_i => pipe_tx3_elec_idle_i,
|
799 |
|
|
pipe_tx_powerdown_i => pipe_tx3_powerdown_i,
|
800 |
|
|
|
801 |
|
|
pipe_rx_char_is_k_i => pipe_rx3_char_is_k_i,
|
802 |
|
|
pipe_rx_data_i => pipe_rx3_data_i,
|
803 |
|
|
pipe_rx_valid_i => pipe_rx3_valid_i,
|
804 |
|
|
pipe_rx_chanisaligned_i => pipe_rx3_chanisaligned_i,
|
805 |
|
|
pipe_rx_status_i => pipe_rx3_status_i,
|
806 |
|
|
pipe_rx_phy_status_i => pipe_rx3_phy_status_i,
|
807 |
|
|
pipe_rx_elec_idle_i => pipe_rx3_elec_idle_i,
|
808 |
|
|
pipe_rx_polarity_o => pipe_rx3_polarity_o_v6pcie21,
|
809 |
|
|
pipe_tx_compliance_o => pipe_tx3_compliance_o_v6pcie64,
|
810 |
|
|
pipe_tx_char_is_k_o => pipe_tx3_char_is_k_o_v6pcie63,
|
811 |
|
|
pipe_tx_data_o => pipe_tx3_data_o_v6pcie65,
|
812 |
|
|
pipe_tx_elec_idle_o => pipe_tx3_elec_idle_o_v6pcie66,
|
813 |
|
|
pipe_tx_powerdown_o => pipe_tx3_powerdown_o_v6pcie67,
|
814 |
|
|
|
815 |
|
|
pipe_clk => pipe_clk,
|
816 |
|
|
rst_n => rst_n
|
817 |
|
|
);
|
818 |
|
|
|
819 |
|
|
end generate;
|
820 |
|
|
v6pcie97 : if (not(NO_OF_LANES >= 4)) generate
|
821 |
|
|
--<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<
|
822 |
|
|
--<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<
|
823 |
|
|
pipe_rx2_char_is_k_q <= "00";
|
824 |
|
|
pipe_rx2_data_q <= "0000000000000000";
|
825 |
|
|
pipe_rx2_valid_o_v6pcie17 <= '0';
|
826 |
|
|
pipe_rx2_chanisaligned_o_v6pcie12 <= '0';
|
827 |
|
|
pipe_rx2_status_o_v6pcie16 <= "000";
|
828 |
|
|
pipe_rx2_phy_status_o_v6pcie14 <= '0';
|
829 |
|
|
pipe_rx2_elec_idle_o_v6pcie13 <= '1';
|
830 |
|
|
pipe_rx2_polarity_o_v6pcie15 <= '0';
|
831 |
|
|
pipe_tx2_compliance_o_v6pcie59 <= '0';
|
832 |
|
|
pipe_tx2_char_is_k_o_v6pcie58 <= "00";
|
833 |
|
|
pipe_tx2_data_o_v6pcie60 <= "0000000000000000";
|
834 |
|
|
pipe_tx2_elec_idle_o_v6pcie61 <= '1';
|
835 |
|
|
pipe_tx2_powerdown_o_v6pcie62 <= "00";
|
836 |
|
|
|
837 |
|
|
pipe_rx3_char_is_k_q <= "00";
|
838 |
|
|
pipe_rx3_data_q <= "0000000000000000";
|
839 |
|
|
pipe_rx3_valid_o_v6pcie23 <= '0';
|
840 |
|
|
pipe_rx3_chanisaligned_o_v6pcie18 <= '0';
|
841 |
|
|
pipe_rx3_status_o_v6pcie22 <= "000";
|
842 |
|
|
pipe_rx3_phy_status_o_v6pcie20 <= '0';
|
843 |
|
|
pipe_rx3_elec_idle_o_v6pcie19 <= '1';
|
844 |
|
|
pipe_rx3_polarity_o_v6pcie21 <= '0';
|
845 |
|
|
pipe_tx3_compliance_o_v6pcie64 <= '0';
|
846 |
|
|
pipe_tx3_char_is_k_o_v6pcie63 <= "00";
|
847 |
|
|
pipe_tx3_data_o_v6pcie65 <= "0000000000000000";
|
848 |
|
|
pipe_tx3_elec_idle_o_v6pcie66 <= '1';
|
849 |
|
|
pipe_tx3_powerdown_o_v6pcie67 <= "00";
|
850 |
|
|
--<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<
|
851 |
|
|
--<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<
|
852 |
|
|
|
853 |
|
|
end generate;
|
854 |
|
|
v6pcie98 : if (NO_OF_LANES >= 8) generate
|
855 |
|
|
|
856 |
|
|
pipe_lane_4_i : pcie_pipe_lane_v6
|
857 |
|
|
generic map (
|
858 |
|
|
PIPE_PIPELINE_STAGES => PIPE_PIPELINE_STAGES
|
859 |
|
|
)
|
860 |
|
|
port map (
|
861 |
|
|
|
862 |
|
|
pipe_rx_char_is_k_o => pipe_rx4_char_is_k_q,
|
863 |
|
|
pipe_rx_data_o => pipe_rx4_data_q,
|
864 |
|
|
pipe_rx_valid_o => pipe_rx4_valid_o_v6pcie29,
|
865 |
|
|
pipe_rx_chanisaligned_o => pipe_rx4_chanisaligned_o_v6pcie24,
|
866 |
|
|
pipe_rx_status_o => pipe_rx4_status_o_v6pcie28,
|
867 |
|
|
pipe_rx_phy_status_o => pipe_rx4_phy_status_o_v6pcie26,
|
868 |
|
|
pipe_rx_elec_idle_o => pipe_rx4_elec_idle_o_v6pcie25,
|
869 |
|
|
pipe_rx_polarity_i => pipe_rx4_polarity_i,
|
870 |
|
|
pipe_tx_compliance_i => pipe_tx4_compliance_i,
|
871 |
|
|
pipe_tx_char_is_k_i => pipe_tx4_char_is_k_i,
|
872 |
|
|
pipe_tx_data_i => pipe_tx4_data_i,
|
873 |
|
|
pipe_tx_elec_idle_i => pipe_tx4_elec_idle_i,
|
874 |
|
|
pipe_tx_powerdown_i => pipe_tx4_powerdown_i,
|
875 |
|
|
|
876 |
|
|
pipe_rx_char_is_k_i => pipe_rx4_char_is_k_i,
|
877 |
|
|
pipe_rx_data_i => pipe_rx4_data_i,
|
878 |
|
|
pipe_rx_valid_i => pipe_rx4_valid_i,
|
879 |
|
|
pipe_rx_chanisaligned_i => pipe_rx4_chanisaligned_i,
|
880 |
|
|
pipe_rx_status_i => pipe_rx4_status_i,
|
881 |
|
|
pipe_rx_phy_status_i => pipe_rx4_phy_status_i,
|
882 |
|
|
pipe_rx_elec_idle_i => pipe_rx4_elec_idle_i,
|
883 |
|
|
pipe_rx_polarity_o => pipe_rx4_polarity_o_v6pcie27,
|
884 |
|
|
pipe_tx_compliance_o => pipe_tx4_compliance_o_v6pcie69,
|
885 |
|
|
pipe_tx_char_is_k_o => pipe_tx4_char_is_k_o_v6pcie68,
|
886 |
|
|
pipe_tx_data_o => pipe_tx4_data_o_v6pcie70,
|
887 |
|
|
pipe_tx_elec_idle_o => pipe_tx4_elec_idle_o_v6pcie71,
|
888 |
|
|
pipe_tx_powerdown_o => pipe_tx4_powerdown_o_v6pcie72,
|
889 |
|
|
|
890 |
|
|
pipe_clk => pipe_clk,
|
891 |
|
|
rst_n => rst_n
|
892 |
|
|
);
|
893 |
|
|
|
894 |
|
|
pipe_lane_5_i : pcie_pipe_lane_v6
|
895 |
|
|
generic map (
|
896 |
|
|
PIPE_PIPELINE_STAGES => PIPE_PIPELINE_STAGES
|
897 |
|
|
)
|
898 |
|
|
port map (
|
899 |
|
|
|
900 |
|
|
pipe_rx_char_is_k_o => pipe_rx5_char_is_k_q,
|
901 |
|
|
pipe_rx_data_o => pipe_rx5_data_q,
|
902 |
|
|
pipe_rx_valid_o => pipe_rx5_valid_o_v6pcie35,
|
903 |
|
|
pipe_rx_chanisaligned_o => pipe_rx5_chanisaligned_o_v6pcie30,
|
904 |
|
|
pipe_rx_status_o => pipe_rx5_status_o_v6pcie34,
|
905 |
|
|
pipe_rx_phy_status_o => pipe_rx5_phy_status_o_v6pcie32,
|
906 |
|
|
pipe_rx_elec_idle_o => pipe_rx5_elec_idle_o_v6pcie31,
|
907 |
|
|
pipe_rx_polarity_i => pipe_rx5_polarity_i,
|
908 |
|
|
pipe_tx_compliance_i => pipe_tx5_compliance_i,
|
909 |
|
|
pipe_tx_char_is_k_i => pipe_tx5_char_is_k_i,
|
910 |
|
|
pipe_tx_data_i => pipe_tx5_data_i,
|
911 |
|
|
pipe_tx_elec_idle_i => pipe_tx5_elec_idle_i,
|
912 |
|
|
pipe_tx_powerdown_i => pipe_tx5_powerdown_i,
|
913 |
|
|
|
914 |
|
|
pipe_rx_char_is_k_i => pipe_rx5_char_is_k_i,
|
915 |
|
|
pipe_rx_data_i => pipe_rx5_data_i,
|
916 |
|
|
pipe_rx_valid_i => pipe_rx5_valid_i,
|
917 |
|
|
pipe_rx_chanisaligned_i => pipe_rx5_chanisaligned_i,
|
918 |
|
|
pipe_rx_status_i => pipe_rx5_status_i,
|
919 |
|
|
pipe_rx_phy_status_i => pipe_rx4_phy_status_i,
|
920 |
|
|
pipe_rx_elec_idle_i => pipe_rx4_elec_idle_i,
|
921 |
|
|
pipe_rx_polarity_o => pipe_rx5_polarity_o_v6pcie33,
|
922 |
|
|
pipe_tx_compliance_o => pipe_tx5_compliance_o_v6pcie74,
|
923 |
|
|
pipe_tx_char_is_k_o => pipe_tx5_char_is_k_o_v6pcie73,
|
924 |
|
|
pipe_tx_data_o => pipe_tx5_data_o_v6pcie75,
|
925 |
|
|
pipe_tx_elec_idle_o => pipe_tx5_elec_idle_o_v6pcie76,
|
926 |
|
|
pipe_tx_powerdown_o => pipe_tx5_powerdown_o_v6pcie77,
|
927 |
|
|
|
928 |
|
|
pipe_clk => pipe_clk,
|
929 |
|
|
rst_n => rst_n
|
930 |
|
|
);
|
931 |
|
|
|
932 |
|
|
pipe_lane_6_i : pcie_pipe_lane_v6
|
933 |
|
|
generic map (
|
934 |
|
|
PIPE_PIPELINE_STAGES => PIPE_PIPELINE_STAGES
|
935 |
|
|
)
|
936 |
|
|
port map (
|
937 |
|
|
|
938 |
|
|
pipe_rx_char_is_k_o => pipe_rx6_char_is_k_q,
|
939 |
|
|
pipe_rx_data_o => pipe_rx6_data_q,
|
940 |
|
|
pipe_rx_valid_o => pipe_rx6_valid_o_v6pcie41,
|
941 |
|
|
pipe_rx_chanisaligned_o => pipe_rx6_chanisaligned_o_v6pcie36,
|
942 |
|
|
pipe_rx_status_o => pipe_rx6_status_o_v6pcie40,
|
943 |
|
|
pipe_rx_phy_status_o => pipe_rx6_phy_status_o_v6pcie38,
|
944 |
|
|
pipe_rx_elec_idle_o => pipe_rx6_elec_idle_o_v6pcie37,
|
945 |
|
|
pipe_rx_polarity_i => pipe_rx6_polarity_i,
|
946 |
|
|
pipe_tx_compliance_i => pipe_tx6_compliance_i,
|
947 |
|
|
pipe_tx_char_is_k_i => pipe_tx6_char_is_k_i,
|
948 |
|
|
pipe_tx_data_i => pipe_tx6_data_i,
|
949 |
|
|
pipe_tx_elec_idle_i => pipe_tx6_elec_idle_i,
|
950 |
|
|
pipe_tx_powerdown_i => pipe_tx6_powerdown_i,
|
951 |
|
|
|
952 |
|
|
pipe_rx_char_is_k_i => pipe_rx6_char_is_k_i,
|
953 |
|
|
pipe_rx_data_i => pipe_rx6_data_i,
|
954 |
|
|
pipe_rx_valid_i => pipe_rx6_valid_i,
|
955 |
|
|
pipe_rx_chanisaligned_i => pipe_rx6_chanisaligned_i,
|
956 |
|
|
pipe_rx_status_i => pipe_rx6_status_i,
|
957 |
|
|
pipe_rx_phy_status_i => pipe_rx4_phy_status_i,
|
958 |
|
|
pipe_rx_elec_idle_i => pipe_rx6_elec_idle_i,
|
959 |
|
|
pipe_rx_polarity_o => pipe_rx6_polarity_o_v6pcie39,
|
960 |
|
|
pipe_tx_compliance_o => pipe_tx6_compliance_o_v6pcie79,
|
961 |
|
|
pipe_tx_char_is_k_o => pipe_tx6_char_is_k_o_v6pcie78,
|
962 |
|
|
pipe_tx_data_o => pipe_tx6_data_o_v6pcie80,
|
963 |
|
|
pipe_tx_elec_idle_o => pipe_tx6_elec_idle_o_v6pcie81,
|
964 |
|
|
pipe_tx_powerdown_o => pipe_tx6_powerdown_o_v6pcie82,
|
965 |
|
|
|
966 |
|
|
pipe_clk => pipe_clk,
|
967 |
|
|
rst_n => rst_n
|
968 |
|
|
);
|
969 |
|
|
|
970 |
|
|
pipe_lane_7_i : pcie_pipe_lane_v6
|
971 |
|
|
generic map (
|
972 |
|
|
PIPE_PIPELINE_STAGES => PIPE_PIPELINE_STAGES
|
973 |
|
|
)
|
974 |
|
|
port map (
|
975 |
|
|
|
976 |
|
|
pipe_rx_char_is_k_o => pipe_rx7_char_is_k_q,
|
977 |
|
|
pipe_rx_data_o => pipe_rx7_data_q,
|
978 |
|
|
pipe_rx_valid_o => pipe_rx7_valid_o_v6pcie47,
|
979 |
|
|
pipe_rx_chanisaligned_o => pipe_rx7_chanisaligned_o_v6pcie42,
|
980 |
|
|
pipe_rx_status_o => pipe_rx7_status_o_v6pcie46,
|
981 |
|
|
pipe_rx_phy_status_o => pipe_rx7_phy_status_o_v6pcie44,
|
982 |
|
|
pipe_rx_elec_idle_o => pipe_rx7_elec_idle_o_v6pcie43,
|
983 |
|
|
pipe_rx_polarity_i => pipe_rx7_polarity_i,
|
984 |
|
|
pipe_tx_compliance_i => pipe_tx7_compliance_i,
|
985 |
|
|
pipe_tx_char_is_k_i => pipe_tx7_char_is_k_i,
|
986 |
|
|
pipe_tx_data_i => pipe_tx7_data_i,
|
987 |
|
|
pipe_tx_elec_idle_i => pipe_tx7_elec_idle_i,
|
988 |
|
|
pipe_tx_powerdown_i => pipe_tx7_powerdown_i,
|
989 |
|
|
|
990 |
|
|
pipe_rx_char_is_k_i => pipe_rx7_char_is_k_i,
|
991 |
|
|
pipe_rx_data_i => pipe_rx7_data_i,
|
992 |
|
|
pipe_rx_valid_i => pipe_rx7_valid_i,
|
993 |
|
|
pipe_rx_chanisaligned_i => pipe_rx7_chanisaligned_i,
|
994 |
|
|
pipe_rx_status_i => pipe_rx7_status_i,
|
995 |
|
|
pipe_rx_phy_status_i => pipe_rx4_phy_status_i,
|
996 |
|
|
pipe_rx_elec_idle_i => pipe_rx7_elec_idle_i,
|
997 |
|
|
pipe_rx_polarity_o => pipe_rx7_polarity_o_v6pcie45,
|
998 |
|
|
pipe_tx_compliance_o => pipe_tx7_compliance_o_v6pcie84,
|
999 |
|
|
pipe_tx_char_is_k_o => pipe_tx7_char_is_k_o_v6pcie83,
|
1000 |
|
|
pipe_tx_data_o => pipe_tx7_data_o_v6pcie85,
|
1001 |
|
|
pipe_tx_elec_idle_o => pipe_tx7_elec_idle_o_v6pcie86,
|
1002 |
|
|
pipe_tx_powerdown_o => pipe_tx7_powerdown_o_v6pcie87,
|
1003 |
|
|
|
1004 |
|
|
pipe_clk => pipe_clk,
|
1005 |
|
|
rst_n => rst_n
|
1006 |
|
|
);
|
1007 |
|
|
|
1008 |
|
|
end generate;
|
1009 |
|
|
v6pcie99 : if (not(NO_OF_LANES >= 8)) generate
|
1010 |
|
|
--<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<
|
1011 |
|
|
--<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<
|
1012 |
|
|
pipe_rx4_char_is_k_q <= "00";
|
1013 |
|
|
pipe_rx4_data_q <= "0000000000000000";
|
1014 |
|
|
pipe_rx4_valid_o_v6pcie29 <= '0';
|
1015 |
|
|
pipe_rx4_chanisaligned_o_v6pcie24 <= '0';
|
1016 |
|
|
pipe_rx4_status_o_v6pcie28 <= "000";
|
1017 |
|
|
pipe_rx4_phy_status_o_v6pcie26 <= '0';
|
1018 |
|
|
pipe_rx4_elec_idle_o_v6pcie25 <= '1';
|
1019 |
|
|
pipe_rx4_polarity_o_v6pcie27 <= '0';
|
1020 |
|
|
pipe_tx4_compliance_o_v6pcie69 <= '0';
|
1021 |
|
|
pipe_tx4_char_is_k_o_v6pcie68 <= "00";
|
1022 |
|
|
pipe_tx4_data_o_v6pcie70 <= "0000000000000000";
|
1023 |
|
|
pipe_tx4_elec_idle_o_v6pcie71 <= '1';
|
1024 |
|
|
pipe_tx4_powerdown_o_v6pcie72 <= "00";
|
1025 |
|
|
|
1026 |
|
|
pipe_rx5_char_is_k_q <= "00";
|
1027 |
|
|
pipe_rx5_data_q <= "0000000000000000";
|
1028 |
|
|
pipe_rx5_valid_o_v6pcie35 <= '0';
|
1029 |
|
|
pipe_rx5_chanisaligned_o_v6pcie30 <= '0';
|
1030 |
|
|
pipe_rx5_status_o_v6pcie34 <= "000";
|
1031 |
|
|
pipe_rx5_phy_status_o_v6pcie32 <= '0';
|
1032 |
|
|
pipe_rx5_elec_idle_o_v6pcie31 <= '1';
|
1033 |
|
|
pipe_rx5_polarity_o_v6pcie33 <= '0';
|
1034 |
|
|
pipe_tx5_compliance_o_v6pcie74 <= '0';
|
1035 |
|
|
pipe_tx5_char_is_k_o_v6pcie73 <= "00";
|
1036 |
|
|
pipe_tx5_data_o_v6pcie75 <= "0000000000000000";
|
1037 |
|
|
pipe_tx5_elec_idle_o_v6pcie76 <= '1';
|
1038 |
|
|
pipe_tx5_powerdown_o_v6pcie77 <= "00";
|
1039 |
|
|
|
1040 |
|
|
pipe_rx6_char_is_k_q <= "00";
|
1041 |
|
|
pipe_rx6_data_q <= "0000000000000000";
|
1042 |
|
|
pipe_rx6_valid_o_v6pcie41 <= '0';
|
1043 |
|
|
pipe_rx6_chanisaligned_o_v6pcie36 <= '0';
|
1044 |
|
|
pipe_rx6_status_o_v6pcie40 <= "000";
|
1045 |
|
|
pipe_rx6_phy_status_o_v6pcie38 <= '0';
|
1046 |
|
|
pipe_rx6_elec_idle_o_v6pcie37 <= '1';
|
1047 |
|
|
pipe_rx6_polarity_o_v6pcie39 <= '0';
|
1048 |
|
|
pipe_tx6_compliance_o_v6pcie79 <= '0';
|
1049 |
|
|
pipe_tx6_char_is_k_o_v6pcie78 <= "00";
|
1050 |
|
|
pipe_tx6_data_o_v6pcie80 <= "0000000000000000";
|
1051 |
|
|
pipe_tx6_elec_idle_o_v6pcie81 <= '1';
|
1052 |
|
|
pipe_tx6_powerdown_o_v6pcie82 <= "00";
|
1053 |
|
|
|
1054 |
|
|
pipe_rx7_char_is_k_q <= "00";
|
1055 |
|
|
pipe_rx7_data_q <= "0000000000000000";
|
1056 |
|
|
pipe_rx7_valid_o_v6pcie47 <= '0';
|
1057 |
|
|
pipe_rx7_chanisaligned_o_v6pcie42 <= '0';
|
1058 |
|
|
pipe_rx7_status_o_v6pcie46 <= "000";
|
1059 |
|
|
pipe_rx7_phy_status_o_v6pcie44 <= '0';
|
1060 |
|
|
pipe_rx7_elec_idle_o_v6pcie43 <= '1';
|
1061 |
|
|
pipe_rx7_polarity_o_v6pcie45 <= '0';
|
1062 |
|
|
pipe_tx7_compliance_o_v6pcie84 <= '0';
|
1063 |
|
|
pipe_tx7_char_is_k_o_v6pcie83 <= "00";
|
1064 |
|
|
pipe_tx7_data_o_v6pcie85 <= "0000000000000000";
|
1065 |
|
|
pipe_tx7_elec_idle_o_v6pcie86 <= '1';
|
1066 |
|
|
pipe_tx7_powerdown_o_v6pcie87 <= "00";
|
1067 |
|
|
--<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<
|
1068 |
|
|
--<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<
|
1069 |
|
|
|
1070 |
|
|
end generate;
|
1071 |
|
|
|
1072 |
|
|
--<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<
|
1073 |
|
|
--<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<
|
1074 |
|
|
|
1075 |
|
|
--<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<
|
1076 |
|
|
--<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<
|
1077 |
|
|
|
1078 |
|
|
pipe_rx0_char_is_k_o <= pipe_rx0_char_is_k_q;
|
1079 |
|
|
pipe_rx0_data_o <= pipe_rx0_data_q;
|
1080 |
|
|
pipe_rx1_char_is_k_o <= pipe_rx1_char_is_k_q;
|
1081 |
|
|
pipe_rx1_data_o <= pipe_rx1_data_q;
|
1082 |
|
|
pipe_rx2_char_is_k_o <= pipe_rx2_char_is_k_q;
|
1083 |
|
|
pipe_rx2_data_o <= pipe_rx2_data_q;
|
1084 |
|
|
pipe_rx3_char_is_k_o <= pipe_rx3_char_is_k_q;
|
1085 |
|
|
pipe_rx3_data_o <= pipe_rx3_data_q;
|
1086 |
|
|
pipe_rx4_char_is_k_o <= pipe_rx4_char_is_k_q;
|
1087 |
|
|
pipe_rx4_data_o <= pipe_rx4_data_q;
|
1088 |
|
|
pipe_rx5_char_is_k_o <= pipe_rx5_char_is_k_q;
|
1089 |
|
|
pipe_rx5_data_o <= pipe_rx5_data_q;
|
1090 |
|
|
pipe_rx6_char_is_k_o <= pipe_rx6_char_is_k_q;
|
1091 |
|
|
pipe_rx6_data_o <= pipe_rx6_data_q;
|
1092 |
|
|
pipe_rx7_char_is_k_o <= pipe_rx7_char_is_k_q;
|
1093 |
|
|
pipe_rx7_data_o <= pipe_rx7_data_q;
|
1094 |
|
|
|
1095 |
|
|
end v6_pcie;
|