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Core name: Xilinx Virtex-6 Integrated Block for PCI Express
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Version: 1.7
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Release Date: March 02, 2011
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================================================================================
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This document contains the following sections:
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1. Introduction
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2. New Features
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3. Supported Devices
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4. Resolved Issues
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5. Known Issues
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6. Technical Support
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7. Other Information
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8. Core Release History
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9. Legal Disclaimer
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================================================================================
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1. INTRODUCTION
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For the most recent updates to the IP installation instructions for this core,
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please go to:
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http://www.xilinx.com/ipcenter/coregen/ip_update_install_instructions.htm
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For system requirements:
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http://www.xilinx.com/ipcenter/coregen/ip_update_system_requirements.htm
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This file contains release notes for the Xilinx LogiCORE(TM) IP Virtex-6
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Integrated Block for PCI Express v1.6 solution. For the latest core updates,
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see the product page at:
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http://www.xilinx.com/products/ipcenter/V6_PCI_Express_Block.htm
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2. NEW FEATURES
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- ISE 12.3 software support
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- QPro Virtex-6 Hi-Rel device support
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- Enabled ISE Simulator (ISIM) support
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3. SUPPORTED DEVICES
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- Virtex-6 LXT
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- Virtex-6 SXT
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- Virtex-6 HXT
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- Virtex-6 CXT
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- Virtex-6 Lower Power
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- QPro Virtex-6 Hi-Rel
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4. RESOLVED ISSUES
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- Synplify flow now supported for entire synthesis / implementation
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o CR 531976
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Synplify flow is now supported for complete synthesis and implementation
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process.
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- Added support for QPro Virtex-6 Hi-Rel devices
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o CR 551821
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Support for all QPro Virtex-6 Hi-Rel devices has now been enabled.
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- Added support for ISE Simulator (ISIM)
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o CR 448851
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Support has been enabled for ISE Simulator (ISIM).
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- 8-lane Gen2 product is now supported in the Virtex-6 HXT devices.
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o CR 531975
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Support for 8-lane Gen2 product, in Virtex-6 HXT devices is now available.
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- GTX Production Settings Updated
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o CR 556498
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GTX settings have been updated per Production GTX settings, based on
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PCI Express protocol characterization.
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- GUI support for 8-lane Gen2 configuration
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o CR 563396
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Issue resolved where GUI did not allow generation of an 8-lane Gen2 design
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for an LX365T-3 device and allowed generation of an 8-lane Gen2 design for
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a LX550T-2 device, which is not supported.
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- GUI support for PCIe Block locations for SX315T-FF1156
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o CR 560140
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Issue resolved where the GUI claimed 4 PCIe Block locations available on
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the SX315T-FF1156, whereas this device only has 2 available PCIe Blocks.
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- Use of corename "core" in VHDL design causing implementation failure
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o CR 538681, 569546
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Issue resolved where use of corename "core" for a VHDL design caused
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implementation failures. The use of corename "core_i" is however
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disabled, as this is used as the instance name of the core in the VHDL
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design.
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- Updates to improve timing on Root Port configuration
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o CR 572179
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Updates have been made to implementation scripts and delivered UCFs to
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improve timing on the Root Port configuration design.
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- Default simulation test has been upgraded
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o CR 571632, 532234
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Default simulation test has been upgraded to include memory and IO
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reads and writes.
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- cfg_msg_* interface ports on Root Port Model now visible
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o CR 571176
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cfg_msg_* ports are now visible at the top level of the Root Port Model
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delivered with Endpoint product.
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- cfg_wr_rw1c_as_rw_n port in Root Port product now connected to Hard Block
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o CR 571018
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cfg_wr_rw1c_as_rw_n port in the Root Port product is now connected to the
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port on the Integrated Block for PCI Express.
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- 128-bit wrapper back-pressure on User Interface when Block is full
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o CR 569361
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Issue resolved where the 128-bit wrapper was not back pressuring the User
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Interface when the Transmit buffers were full, causing data loss.
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- User non-posted OK signal undriven in VHDL Root Port model
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o CR 568793
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Issue resolved where the User non-posted OK signal was undriven in the
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VHDL Root Port model, preventing memory read transactions from passing to
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the User Interface.
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- Fixed missing default case statement in FSM in 128bit PIO example design
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o CR 567366
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Issue resolved where the default case statement was missing in the FSM in
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the 128bit PIO example design.
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- Redeclaration of signals in VHDL instantiation template
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o CR 555620
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Issue resolved where the signals were re-declared in the VHDL
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instantiation template, causing synthesis errors when used.
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5. KNOWN ISSUES
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The following are known issues for v1.6 of this core at time of release:
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5.1 Functional Issues
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5.2 Simulation Issues
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5.3 Implementation Issues
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- Timing Closure
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In order to obtain timing closure, designers may be required to use
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multiple PAR seeds and/or floorplanning. Using Multi-Pass Place and
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Route (MPPR), designers can try multiple cost tables in order to meet
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timing. Please see the Development System Reference Guide in the
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Software Manuals found at: http://www.xilinx.com/support/library.htm
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for more information on using MPPR. Designers may also have to
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floorplan and add advanced placement constraints for both their
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design and the core to meet timing.
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The most recent information, including known issues, workarounds, and
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resolutions for this version is provided in the IP Release Notes Guide located at
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http://www.xilinx.com/support/documentation/user_guides/xtp025.pdf
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6. TECHNICAL SUPPORT
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To obtain technical support, create a WebCase at www.xilinx.com/support.
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Questions are routed to a team with expertise using this product.
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Xilinx provides technical support for use of this product when used
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according to the guidelines described in the core documentation, and
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cannot guarantee timing, functionality, or support of this product for
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designs that do not follow specified guidelines.
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7. OTHER INFORMATION
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8. CORE RELEASE HISTORY
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Date By Version Description
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================================================================================
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03/02/2011 Xilinx, Inc. 1.7 13.1 support
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09/21/2010 Xilinx, Inc. 1.6 12.3 support
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07/23/2010 Xilinx, Inc. 1.5 Rev 1 Patch Release
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04/19/2010 Xilinx, Inc. 1.5 12.1 support
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03/09/2010 Xilinx, Inc. 1.4 Rev 3 Patch Release
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03/09/2010 Xilinx, Inc. 1.4 Rev 2 11.5 support
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12/02/2009 Xilinx, Inc. 1.4 Rev 1 Patch Release
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12/02/2009 Xilinx, Inc. 1.4 11.4 support
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09/16/2009 Xilinx, Inc. 1.3 11.3 support
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06/24/2009 Xilinx, Inc. 1.2 11.2 support
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04/24/2009 Xilinx, Inc. 1.1 Initial release (BETA)
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================================================================================
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9. Legal Disclaimer
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(c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
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This file contains confidential and proprietary information
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of Xilinx, Inc. and is protected under U.S. and
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international copyright and other intellectual property
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laws.
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DISCLAIMER
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This disclaimer is not a license and does not grant any
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rights to the materials distributed herewith. Except as
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otherwise provided in a valid license issued to you by
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Xilinx, and to the maximum extent permitted by applicable
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law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
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WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
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AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
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BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
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INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
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(2) Xilinx shall not be liable (whether in contract or tort,
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including negligence, or under any other theory of
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liability) for any loss or damage of any kind or nature
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related to, arising under or in connection with these
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materials, including for any direct, or any indirect,
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special, incidental, or consequential loss or damage
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(including loss of data, profits, goodwill, or any type of
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loss or damage suffered as a result of any action brought
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by a third party) even if such damage or loss was
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reasonably foreseeable or Xilinx had been advised of the
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possibility of the same.
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CRITICAL APPLICATIONS
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Xilinx products are not designed or intended to be fail-
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safe, or for use in any application requiring fail-safe
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performance, such as life-support or safety devices or
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systems, Class III medical devices, nuclear facilities,
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applications related to the deployment of airbags, or any
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other applications that could lead to death, personal
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injury, or severe property or environmental damage
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(individually and collectively, "Critical
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Applications"). Customer assumes the sole risk and
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liability of any use of Xilinx products in Critical
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Applications, subject only to applicable laws and
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regulations governing limitations on product liability.
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THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
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PART OF THIS FILE AT ALL TIMES.
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