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//-----------------------------------------------------------------------------
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//
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// (c) Copyright 2009-2011 Xilinx, Inc. All rights reserved.
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//
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// This file contains confidential and proprietary information
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// of Xilinx, Inc. and is protected under U.S. and
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// international copyright and other intellectual property
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// laws.
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//
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// DISCLAIMER
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// This disclaimer is not a license and does not grant any
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// rights to the materials distributed herewith. Except as
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// otherwise provided in a valid license issued to you by
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// Xilinx, and to the maximum extent permitted by applicable
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// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
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// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
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// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
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// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
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// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
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// (2) Xilinx shall not be liable (whether in contract or tort,
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// including negligence, or under any other theory of
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// liability) for any loss or damage of any kind or nature
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// related to, arising under or in connection with these
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// materials, including for any direct, or any indirect,
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// special, incidental, or consequential loss or damage
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// (including loss of data, profits, goodwill, or any type of
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// loss or damage suffered as a result of any action brought
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// by a third party) even if such damage or loss was
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// reasonably foreseeable or Xilinx had been advised of the
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// possibility of the same.
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//
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// CRITICAL APPLICATIONS
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// Xilinx products are not designed or intended to be fail-
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// safe, or for use in any application requiring fail-safe
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// performance, such as life-support or safety devices or
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// systems, Class III medical devices, nuclear facilities,
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// applications related to the deployment of airbags, or any
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// other applications that could lead to death, personal
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// injury, or severe property or environmental damage
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// (individually and collectively, "Critical
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// Applications"). Customer assumes the sole risk and
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// liability of any use of Xilinx products in Critical
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// Applications, subject only to applicable laws and
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// regulations governing limitations on product liability.
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//
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// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
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// PART OF THIS FILE AT ALL TIMES.
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//
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//-----------------------------------------------------------------------------
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// Project : Virtex-6 Integrated Block for PCI Express
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// File : v6_pcie_v1_7_x4.veo
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// Version : 1.7
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//--
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//------------------------------------------------------------------------------
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// The following must be inserted into your Verilog file for this
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// core to be instantiated. Change the instance name and port connections
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// (in parentheses) to your own signal names.
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//----------- Begin Cut here for INSTANTIATION Template ---// INST_TAG
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v6_pcie_v1_7_x4YourInstanceName (
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//-------------------------------------------------------
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// 1. PCI Express (pci_exp) Interface
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//-------------------------------------------------------
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// Tx
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.pci_exp_txp( pci_exp_txp ),
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.pci_exp_txn( pci_exp_txn ),
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// Rx
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.pci_exp_rxp( pci_exp_rxp ),
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.pci_exp_rxn( pci_exp_rxn ),
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//-------------------------------------------------------
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// 2. Transaction (TRN) Interface
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//-------------------------------------------------------
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// Common
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.trn_clk( trn_clk ),
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.trn_reset_n( trn_reset_n_int1 ),
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.trn_lnk_up_n( trn_lnk_up_n_int1 ),
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// Tx
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.trn_tbuf_av( trn_tbuf_av ),
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.trn_tcfg_req_n( trn_tcfg_req_n ),
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.trn_terr_drop_n( trn_terr_drop_n ),
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.trn_tdst_rdy_n( trn_tdst_rdy_n ),
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.trn_td( trn_td ),
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.trn_trem_n( trn_trem_n ),
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.trn_tsof_n( trn_tsof_n ),
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.trn_teof_n( trn_teof_n ),
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.trn_tsrc_rdy_n( trn_tsrc_rdy_n ),
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.trn_tsrc_dsc_n( trn_tsrc_dsc_n ),
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.trn_terrfwd_n( trn_terrfwd_n ),
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.trn_tcfg_gnt_n( trn_tcfg_gnt_n ),
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.trn_tstr_n( trn_tstr_n ),
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// Rx
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.trn_rd( trn_rd ),
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.trn_rrem_n( trn_rrem_n ),
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.trn_rsof_n( trn_rsof_n ),
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.trn_reof_n( trn_reof_n ),
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.trn_rsrc_rdy_n( trn_rsrc_rdy_n ),
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.trn_rsrc_dsc_n( trn_rsrc_dsc_n ),
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.trn_rerrfwd_n( trn_rerrfwd_n ),
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.trn_rbar_hit_n( trn_rbar_hit_n ),
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.trn_rdst_rdy_n( trn_rdst_rdy_n ),
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.trn_rnp_ok_n( trn_rnp_ok_n ),
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// Flow Control
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.trn_fc_cpld( trn_fc_cpld ),
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.trn_fc_cplh( trn_fc_cplh ),
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.trn_fc_npd( trn_fc_npd ),
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.trn_fc_nph( trn_fc_nph ),
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.trn_fc_pd( trn_fc_pd ),
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.trn_fc_ph( trn_fc_ph ),
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.trn_fc_sel( trn_fc_sel ),
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//-------------------------------------------------------
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// 3. Configuration (CFG) Interface
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//-------------------------------------------------------
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.cfg_do( cfg_do ),
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.cfg_rd_wr_done_n( cfg_rd_wr_done_n),
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.cfg_di( cfg_di ),
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.cfg_byte_en_n( cfg_byte_en_n ),
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.cfg_dwaddr( cfg_dwaddr ),
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.cfg_wr_en_n( cfg_wr_en_n ),
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.cfg_rd_en_n( cfg_rd_en_n ),
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.cfg_err_cor_n( cfg_err_cor_n ),
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.cfg_err_ur_n( cfg_err_ur_n ),
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.cfg_err_ecrc_n( cfg_err_ecrc_n ),
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.cfg_err_cpl_timeout_n( cfg_err_cpl_timeout_n ),
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.cfg_err_cpl_abort_n( cfg_err_cpl_abort_n ),
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.cfg_err_cpl_unexpect_n( cfg_err_cpl_unexpect_n ),
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.cfg_err_posted_n( cfg_err_posted_n ),
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.cfg_err_locked_n( cfg_err_locked_n ),
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.cfg_err_tlp_cpl_header( cfg_err_tlp_cpl_header ),
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.cfg_err_cpl_rdy_n( cfg_err_cpl_rdy_n ),
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.cfg_interrupt_n( cfg_interrupt_n ),
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.cfg_interrupt_rdy_n( cfg_interrupt_rdy_n ),
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.cfg_interrupt_assert_n( cfg_interrupt_assert_n ),
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.cfg_interrupt_di( cfg_interrupt_di ),
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.cfg_interrupt_do( cfg_interrupt_do ),
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.cfg_interrupt_mmenable( cfg_interrupt_mmenable ),
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.cfg_interrupt_msienable( cfg_interrupt_msienable ),
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.cfg_interrupt_msixenable( cfg_interrupt_msixenable ),
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.cfg_interrupt_msixfm( cfg_interrupt_msixfm ),
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.cfg_turnoff_ok_n( cfg_turnoff_ok_n ),
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.cfg_to_turnoff_n( cfg_to_turnoff_n ),
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.cfg_trn_pending_n( cfg_trn_pending_n ),
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.cfg_pm_wake_n( cfg_pm_wake_n ),
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.cfg_bus_number( cfg_bus_number ),
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.cfg_device_number( cfg_device_number ),
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.cfg_function_number( cfg_function_number ),
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.cfg_status( cfg_status ),
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.cfg_command( cfg_command ),
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.cfg_dstatus( cfg_dstatus ),
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.cfg_dcommand( cfg_dcommand ),
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.cfg_lstatus( cfg_lstatus ),
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.cfg_lcommand( cfg_lcommand ),
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.cfg_dcommand2( cfg_dcommand2 ),
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.cfg_pcie_link_state_n( cfg_pcie_link_state_n ),
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.cfg_dsn( cfg_dsn ),
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.cfg_pmcsr_pme_en( cfg_pmcsr_pme_en ),
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.cfg_pmcsr_pme_status( cfg_pmcsr_pme_status ),
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.cfg_pmcsr_powerstate( cfg_pmcsr_powerstate ),
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//-------------------------------------------------------
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// 4. Physical Layer Control and Status (PL) Interface
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//-------------------------------------------------------
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.pl_initial_link_width( pl_initial_link_width ),
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.pl_lane_reversal_mode( pl_lane_reversal_mode ),
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.pl_link_gen2_capable( pl_link_gen2_capable ),
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.pl_link_partner_gen2_supported( pl_link_partner_gen2_supported ),
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.pl_link_upcfg_capable( pl_link_upcfg_capable ),
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.pl_ltssm_state( pl_ltssm_state ),
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.pl_received_hot_rst( pl_received_hot_rst ),
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.pl_sel_link_rate( pl_sel_link_rate ),
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.pl_sel_link_width( pl_sel_link_width ),
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.pl_directed_link_auton( pl_directed_link_auton ),
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.pl_directed_link_change( pl_directed_link_change ),
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.pl_directed_link_speed( pl_directed_link_speed ),
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.pl_directed_link_width( pl_directed_link_width ),
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.pl_upstream_prefer_deemph( pl_upstream_prefer_deemph ),
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//-------------------------------------------------------
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// 5. System (SYS) Interface
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//-------------------------------------------------------
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.sys_clk( sys_clk_c ),
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.sys_reset_n( sys_reset_n_c )
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);
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// INST_TAG_END ------ End INSTANTIATION Template ---------
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