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[/] [pcie_sg_dma/] [trunk/] [rtl/] [DDR_Blinker.vhd] - Blame information for rev 2

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1 2 weng_ziti 
----------------------------------------------------------------------------------
2 
-- Company:  ZITI
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-- Engineer:  wgao
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--
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-- Create Date:    16:38:03 06 Oct 2008
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-- Design Name:
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-- Module Name:    DDR_Blink - Behavioral
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-- Project Name:
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-- Target Devices:
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-- Tool versions:
11 
-- Description:
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--
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-- Dependencies:
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--
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-- Revision 1.00 - first release.  08.10.2008
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--
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-- Additional Comments:
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--
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----------------------------------------------------------------------------------
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library IEEE;
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use IEEE.STD_LOGIC_1164.ALL;
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use IEEE.STD_LOGIC_ARITH.ALL;
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use IEEE.STD_LOGIC_UNSIGNED.ALL;
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25 
library work;
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use work.abb64Package.all;
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---- Uncomment the following library declaration if instantiating
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---- any Xilinx primitives in this code.
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--library UNISIM;
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--use UNISIM.VComponents.all;
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33 
entity DDR_Blink is
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    Port (
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           DDR_blinker              : OUT   std_logic;
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           DBG_dma_start            : IN    std_logic;
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           DBG_bram_wea             : IN    std_logic_vector(7 downto 0);
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           DBG_bram_addra           : IN    std_logic_vector(C_PRAM_AWIDTH-1 downto 0);
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           DDR_Write                : IN    std_logic;
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           DDR_Read                 : IN    std_logic;
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           DDR_Both                 : IN    std_logic;
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           ddr_Clock                : IN    std_logic;
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           DDr_Rst_n                : IN    std_logic
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          );
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end entity DDR_Blink;
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50 
 
51 
architecture Behavioral of DDR_Blink is
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53 
 
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  -- Blinking -_-_-_-_
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  Constant  C_BLINKER_MSB       : integer      :=   15;  -- 4;  -- 15;
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  Constant  CBIT_SLOW_BLINKER   : integer      :=   11;  -- 2;  -- 11;
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58 
  signal  DDR_dma_write_wrong_lo   :  std_logic;
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  signal  DDR_dma_write_wrong_hi   :  std_logic;
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  signal  DDR_dma_write_init_lo    :  std_logic;
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  signal  DDR_dma_write_init_hi    :  std_logic;
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  signal  dma_bram_wr_address_lo   :  std_logic_vector(C_PRAM_AWIDTH-1 downto 0);
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  signal  dma_bram_wr_address_hi   :  std_logic_vector(C_PRAM_AWIDTH-1 downto 0);
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65 
  signal  DDR_blinker_i         :  std_logic;
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  signal  Fast_blinker          :  std_logic_vector(C_BLINKER_MSB downto 0);
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  signal  Fast_blinker_MSB_r1   :  std_logic;
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  signal  Blink_Pulse           :  std_logic;
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  signal  Slow_blinker          :  std_logic_vector(CBIT_SLOW_BLINKER downto 0);
70 
 
71 
  signal  DDR_write_extension    :  std_logic;
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  signal  DDR_write_extension_Cnt:  std_logic_vector(1 downto 0);
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  signal  DDR_read_extension     :  std_logic;
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  signal  DDR_read_extension_Cnt :  std_logic_vector(1 downto 0);
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76 
 
77 
begin
78 
 
79 
--   DDR_blinker    <=  DDR_blinker_i;
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   DDR_blinker    <=  DDR_dma_write_wrong_lo or DDR_dma_write_wrong_hi;
81 
 
82 
   --
83 
   Syn_DDR_Fast_blinker:
84 
   process ( ddr_Clock, DDr_Rst_n)
85 
   begin
86 
      if DDr_Rst_n = '0' then
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         Fast_blinker        <= (OTHERS=>'0');
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         Fast_blinker_MSB_r1 <= '0';
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         Blink_Pulse         <= '0';
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91 
         Slow_blinker        <= (OTHERS=>'0');
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93 
      elsif ddr_Clock'event and ddr_Clock = '1' then
94 
         Fast_blinker        <= Fast_blinker + '1';
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         Fast_blinker_MSB_r1 <= Fast_blinker(C_BLINKER_MSB);
96 
         Blink_Pulse         <= Fast_blinker(C_BLINKER_MSB) and not Fast_blinker_MSB_r1;
97 
 
98 
         Slow_blinker        <= Slow_blinker + Blink_Pulse;
99 
 
100 
      end if;
101 
   end process;
102 
 
103 
 
104 
   --
105 
   Syn_DDR_Write_Extenstion:
106 
   process ( ddr_Clock, DDr_Rst_n)
107 
   begin
108 
      if DDr_Rst_n = '0' then
109 
         DDR_write_extension_Cnt <= (OTHERS=>'0');
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         DDR_write_extension     <= '0';
111 
 
112 
      elsif ddr_Clock'event and ddr_Clock = '1' then
113 
 
114 
         case DDR_write_extension_Cnt is
115 
 
116 
           when "00"   =>
117 
             if DDR_Write='1' then
118 
                DDR_write_extension_Cnt <= "01";
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                DDR_write_extension     <= '1';
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             else
121 
                DDR_write_extension_Cnt <= DDR_write_extension_Cnt;
122 
                DDR_write_extension     <= DDR_write_extension;
123 
             end if;
124 
 
125 
           when "01"   =>
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             if Slow_blinker(CBIT_SLOW_BLINKER)='1' then
127 
                DDR_write_extension_Cnt <= "11";
128 
                DDR_write_extension     <= '1';
129 
             else
130 
                DDR_write_extension_Cnt <= DDR_write_extension_Cnt;
131 
                DDR_write_extension     <= DDR_write_extension;
132 
             end if;
133 
 
134 
           when "11"   =>
135 
             if Slow_blinker(CBIT_SLOW_BLINKER)='0' then
136 
                DDR_write_extension_Cnt <= "10";
137 
                DDR_write_extension     <= '1';
138 
             else
139 
                DDR_write_extension_Cnt <= DDR_write_extension_Cnt;
140 
                DDR_write_extension     <= DDR_write_extension;
141 
             end if;
142 
 
143 
           when Others          =>
144 
             if Slow_blinker(CBIT_SLOW_BLINKER)='1' then
145 
                DDR_write_extension_Cnt <= "00";
146 
                DDR_write_extension     <= '0';
147 
             else
148 
                DDR_write_extension_Cnt <= DDR_write_extension_Cnt;
149 
                DDR_write_extension     <= DDR_write_extension;
150 
             end if;
151 
 
152 
         end case;
153 
 
154 
      end if;
155 
   end process;
156 
 
157 
 
158 
   --
159 
   Syn_DDR_Read_Extenstion:
160 
   process ( ddr_Clock, DDr_Rst_n)
161 
   begin
162 
      if DDr_Rst_n = '0' then
163 
         DDR_read_extension_Cnt <= (OTHERS=>'0');
164 
         DDR_read_extension     <= '1';
165 
 
166 
      elsif ddr_Clock'event and ddr_Clock = '1' then
167 
 
168 
         case DDR_read_extension_Cnt is
169 
 
170 
           when "00"   =>
171 
             if DDR_Read='1' then
172 
                DDR_read_extension_Cnt <= "01";
173 
                DDR_read_extension     <= '0';
174 
             else
175 
                DDR_read_extension_Cnt <= DDR_read_extension_Cnt;
176 
                DDR_read_extension     <= DDR_read_extension;
177 
             end if;
178 
 
179 
           when "01"   =>
180 
             if Slow_blinker(CBIT_SLOW_BLINKER)='1' then
181 
                DDR_read_extension_Cnt <= "11";
182 
                DDR_read_extension     <= '0';
183 
             else
184 
                DDR_read_extension_Cnt <= DDR_read_extension_Cnt;
185 
                DDR_read_extension     <= DDR_read_extension;
186 
             end if;
187 
 
188 
           when "11"   =>
189 
             if Slow_blinker(CBIT_SLOW_BLINKER)='0' then
190 
                DDR_read_extension_Cnt <= "10";
191 
                DDR_read_extension     <= '0';
192 
             else
193 
                DDR_read_extension_Cnt <= DDR_read_extension_Cnt;
194 
                DDR_read_extension     <= DDR_read_extension;
195 
             end if;
196 
 
197 
           when Others          =>
198 
             if Slow_blinker(CBIT_SLOW_BLINKER)='1' then
199 
                DDR_read_extension_Cnt <= "00";
200 
                DDR_read_extension     <= '1';
201 
             else
202 
                DDR_read_extension_Cnt <= DDR_read_extension_Cnt;
203 
                DDR_read_extension     <= DDR_read_extension;
204 
             end if;
205 
 
206 
         end case;
207 
 
208 
      end if;
209 
   end process;
210 
 
211 
 
212 
   --
213 
   Syn_DDR_Working_blinker:
214 
   process ( ddr_Clock, DDr_Rst_n)
215 
   begin
216 
      if DDr_Rst_n = '0' then
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         DDR_Blinker_i      <= '0';
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      elsif ddr_Clock'event and ddr_Clock = '1' then
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         DDR_Blinker_i      <= (Slow_blinker(CBIT_SLOW_BLINKER-2) or DDR_write_extension) and DDR_read_extension;
220 
      end if;
221 
   end process;
222 
 
223 
 
224 
   -- !!! DBG !!!
225 
   Syn_DDR_DBG_blinker:
226 
   process ( ddr_Clock, DBG_dma_start)
227 
   begin
228 
      if DBG_dma_start = '1' then
229 
         DDR_dma_write_init_lo  <= '1';
230 
         DDR_dma_write_init_hi  <= '1';
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         DDR_dma_write_wrong_lo <= '0';
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         DDR_dma_write_wrong_hi <= '0';
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         dma_bram_wr_address_lo <= (others=>'0');
234 
         dma_bram_wr_address_hi <= (others=>'0');
235 
 
236 
      elsif ddr_Clock'event and ddr_Clock = '1' then
237 
         if DBG_bram_wea(0)='1' then
238 
            DDR_dma_write_init_lo  <= '0';
239 
         else
240 
            DDR_dma_write_init_lo  <= DDR_dma_write_init_lo;
241 
         end if;
242 
 
243 
         if DDR_dma_write_init_lo='1' then
244 
            DDR_dma_write_wrong_lo <= '0';
245 
            if DBG_bram_wea(0)='1' then
246 
               dma_bram_wr_address_lo <= DBG_bram_addra + '1';
247 
            else
248 
               dma_bram_wr_address_lo <= dma_bram_wr_address_lo;
249 
            end if;
250 
         else
251 
           if DBG_bram_wea(0)='1' then
252 
               dma_bram_wr_address_lo <= dma_bram_wr_address_lo + '1';
253 
               if DBG_bram_addra<dma_bram_wr_address_lo then
254 
                  DDR_dma_write_wrong_lo <= '1';
255 
               else
256 
                  DDR_dma_write_wrong_lo <= '0';
257 
               end if;
258 
           else
259 
               dma_bram_wr_address_lo <= dma_bram_wr_address_lo;
260 
           end if;
261 
         end if;
262 
 
263 
         --------------------------------------------------------------------------------
264 
 
265 
         if DBG_bram_wea(4)='1' then
266 
            DDR_dma_write_init_hi  <= '0';
267 
         else
268 
            DDR_dma_write_init_hi  <= DDR_dma_write_init_hi;
269 
         end if;
270 
 
271 
         if DDR_dma_write_init_hi='1' then
272 
            DDR_dma_write_wrong_hi <= '0';
273 
            if DBG_bram_wea(4)='1' then
274 
               dma_bram_wr_address_hi <= DBG_bram_addra + '1';
275 
            else
276 
               dma_bram_wr_address_hi <= dma_bram_wr_address_hi;
277 
            end if;
278 
         else
279 
           if DBG_bram_wea(4)='1' then
280 
               dma_bram_wr_address_hi <= dma_bram_wr_address_hi + '1';
281 
               if DBG_bram_addra<dma_bram_wr_address_hi then
282 
                  DDR_dma_write_wrong_hi <= '1';
283 
               else
284 
                  DDR_dma_write_wrong_hi <= '0';
285 
               end if;
286 
           else
287 
               dma_bram_wr_address_hi <= dma_bram_wr_address_hi;
288 
           end if;
289 
         end if;
290 
 
291 
      end if;
292 
   end process;
293 
 
294 
end architecture Behavioral;

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