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weng_ziti |
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-- Company: ziti, Uni. HD
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-- Engineer: wgao
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--
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-- Design Name:
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-- Module Name: DMA_Calculate - Behavioral
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-- Project Name:
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-- Target Devices:
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-- Tool versions:
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-- Description:
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--
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-- Dependencies:
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--
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-- Revision 1.00 - first release. 09.02.2007
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--
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-- Additional Comments:
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--
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----------------------------------------------------------------------------------
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library IEEE;
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use IEEE.STD_LOGIC_1164.ALL;
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use IEEE.STD_LOGIC_ARITH.ALL;
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use IEEE.STD_LOGIC_UNSIGNED.ALL;
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library work;
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use work.abb64Package.all;
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-- Uncomment the following library declaration if instantiating
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-- any Xilinx primitives in this code.
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--library UNISIM;
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--use UNISIM.VComponents.all;
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entity DMA_Calculate is
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port (
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-- Downstream Registers from MWr Channel
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DMA_PA : IN std_logic_vector(C_DBUS_WIDTH-1 downto 0); -- EP (local)
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DMA_HA : IN std_logic_vector(C_DBUS_WIDTH-1 downto 0); -- Host (remote)
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DMA_BDA : IN std_logic_vector(C_DBUS_WIDTH-1 downto 0);
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DMA_Length : IN std_logic_vector(C_DBUS_WIDTH-1 downto 0);
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DMA_Control : IN std_logic_vector(C_DBUS_WIDTH-1 downto 0);
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-- Calculation in advance, for better timing
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HA_is_64b : IN std_logic;
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BDA_is_64b : IN std_logic;
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-- Calculation in advance, for better timing
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Leng_Hi19b_True : IN std_logic;
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Leng_Lo7b_True : IN std_logic;
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-- Parameters fed to DMA_FSM
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DMA_PA_Loaded : OUT std_logic_vector(C_DBUS_WIDTH-1 downto 0);
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DMA_PA_Var : OUT std_logic_vector(C_DBUS_WIDTH-1 downto 0);
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DMA_HA_Var : OUT std_logic_vector(C_DBUS_WIDTH-1 downto 0);
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DMA_BDA_fsm : OUT std_logic_vector(C_DBUS_WIDTH-1 downto 0);
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BDA_is_64b_fsm : OUT std_logic;
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DMA_0_Leng : OUT std_logic;
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DMA_Snout_Length : OUT std_logic_vector(C_MAXSIZE_FLD_BIT_TOP downto 0);
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DMA_Body_Length : OUT std_logic_vector(C_MAXSIZE_FLD_BIT_TOP downto 0);
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DMA_Tail_Length : OUT std_logic_vector(C_TLP_FLD_WIDTH_OF_LENG+1 downto 0);
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-- Only for downstream channel
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DMA_PA_Snout : OUT std_logic_vector(C_DBUS_WIDTH-1 downto 0);
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DMA_BAR_Number : OUT std_logic_vector(C_ENCODE_BAR_NUMBER-1 downto 0);
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-- Engine control signals
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DMA_Start : IN std_logic;
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DMA_Start2 : IN std_logic; -- out of consecutive dex
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-- Control signals to FSM
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No_More_Bodies : OUT std_logic; -- No more block(s) of Max_Size
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ThereIs_Snout : OUT std_logic; -- 1st packet before Body blocks
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ThereIs_Body : OUT std_logic; -- Block(s) of Max_Size
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ThereIs_Tail : OUT std_logic; -- Last packet with size less than Max_Size
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ThereIs_Dex : OUT std_logic; -- Not the last descriptor
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HA64bit : OUT std_logic; -- Host Address is 64-bit
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Addr_Inc : OUT std_logic; -- Peripheral Address increase token
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-- FSM indicators
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State_Is_LoadParam : IN std_logic;
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State_Is_Snout : IN std_logic;
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State_Is_Body : IN std_logic;
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-- State_Is_Tail : IN std_logic;
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-- Additional
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Param_Max_Cfg : IN std_logic_vector(2 downto 0);
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-- Common ports
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dma_clk : IN std_logic;
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dma_reset : IN std_logic
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);
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end entity DMA_Calculate;
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architecture Behavioral of DMA_Calculate is
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-- Significant bits from the MaXSiZe parameter
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signal Max_TLP_Size : std_logic_vector(C_MAXSIZE_FLD_BIT_TOP downto 0);
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signal mxsz_left : std_logic_vector(C_MAXSIZE_FLD_BIT_TOP downto C_MAXSIZE_FLD_BIT_BOT);
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signal mxsz_mid : std_logic_vector(C_MAXSIZE_FLD_BIT_TOP downto C_MAXSIZE_FLD_BIT_BOT);
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signal mxsz_right : std_logic_vector(C_MAXSIZE_FLD_BIT_TOP downto C_MAXSIZE_FLD_BIT_BOT);
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-- Signals masked by MaxSize
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signal DMA_Leng_Left_Msk : std_logic_vector(C_MAXSIZE_FLD_BIT_TOP downto C_MAXSIZE_FLD_BIT_BOT);
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signal DMA_Leng_Mid_Msk : std_logic_vector(C_MAXSIZE_FLD_BIT_TOP downto C_MAXSIZE_FLD_BIT_BOT);
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signal DMA_Leng_Right_Msk : std_logic_vector(C_MAXSIZE_FLD_BIT_TOP downto C_MAXSIZE_FLD_BIT_BOT);
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-- Alias
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signal Lo_Leng_Left_Msk_is_True : std_logic;
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signal Lo_Leng_Mid_Msk_is_True : std_logic;
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signal Lo_Leng_Right_Msk_is_True : std_logic;
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-- Masked values of HA and Length
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signal DMA_HA_Msk : std_logic_vector(C_MAXSIZE_FLD_BIT_TOP downto 0);
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signal DMA_Length_Msk : std_logic_vector(C_MAXSIZE_FLD_BIT_TOP downto 0);
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-- Indicates whether the DMA_PA is already accepted
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signal PA_is_taken : std_logic;
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-- Calculation for the PA of the next DMA, if UPA bit = 0
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signal DMA_PA_next : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
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signal DMA_PA_current : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
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-- eventual PA parameter for the current DMA transaction
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signal DMA_PA_Loaded_i : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
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-- Calculation in advance, only for better timing
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signal Carry_PA_plus_Leng : std_logic_vector(CBIT_CARRY downto 0);
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signal Carry_PAx_plus_Leng : std_logic_vector(CBIT_CARRY downto 0);
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signal Leng_Hi_plus_PA_Hi : std_logic_vector(C_DBUS_WIDTH-1 downto CBIT_CARRY);
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signal Leng_Hi_plus_PAx_Hi : std_logic_vector(C_DBUS_WIDTH-1 downto CBIT_CARRY);
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-- DMA parameters from the register module
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signal DMA_PA_i : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
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signal DMA_HA_i : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
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signal DMA_BDA_i : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
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signal DMA_Length_i : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
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signal DMA_Control_i : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
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-- delay
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signal State_Is_Snout_r1 : std_logic;
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signal State_Is_Body_r1 : std_logic;
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-- from control word
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signal Dex_is_Last : std_logic;
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signal Engine_Ends : std_logic;
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-- Major FSM control signals
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signal ThereIs_Snout_i : std_logic;
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signal ThereIs_Body_i : std_logic;
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signal ThereIs_Tail_i : std_logic;
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signal Snout_Only : std_logic;
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signal ThereIs_Dex_i : std_logic;
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signal No_More_Bodies_i : std_logic;
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-- Address/Length combination
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signal ALc : std_logic_vector(C_MAXSIZE_FLD_BIT_TOP downto 0);
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-- Compressed ALc
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-- ALc_B bit means the ALc has carry in, making an extra Body block.
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signal ALc_B : std_logic;
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signal ALc_B_wire : std_logic;
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-- ALc_T bit means the ALc has trailer, making a final Tail block.
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signal ALc_T : std_logic;
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signal ALc_T_wire : std_logic;
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-- Compressed Length
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-- Leng_Two bit means Length >= 2 Max_Size.
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signal Leng_Two : std_logic;
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-- Leng_One bit means Length >= 1 Max_Size.
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signal Leng_One : std_logic;
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-- Leng_nint bit means Length is not integral of Max_Sizes.
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signal Leng_nint : std_logic;
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signal Length_analysis : std_logic_vector(2 downto 0);
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signal Snout_Body_Tail : std_logic_vector(2 downto 0);
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-- Byte counter
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signal DMA_Byte_Counter : std_logic_vector(C_DBUS_WIDTH-1 downto 0); -- !!! Elastic
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signal Length_minus : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
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signal DMA_BC_Carry : std_logic_vector(CBIT_CARRY downto 0);
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-- Remote & Local Address variable
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signal DMA_HA_Var_i : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
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signal DMA_HA_Carry32 : std_logic_vector(C_DBUS_WIDTH/2 downto 0);
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signal DMA_PA_Var_i : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
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-- BDA parameter is buffered for FSM module
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signal DMA_BDA_fsm_i : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
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signal BDA_is_64b_fsm_i : std_logic;
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-- Token bits out of Control word
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signal HA64bit_i : std_logic;
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signal Addr_Inc_i : std_logic;
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signal use_PA : std_logic;
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signal DMA_Start_r1 : std_logic;
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signal DMA_Start2_r1 : std_logic;
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signal DMA_Leng_sub : std_logic_vector(4-1 downto 0);
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signal DMA_0_Leng_i : std_logic;
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-- for better timing
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signal HA_gap : std_logic_vector(C_MAXSIZE_FLD_BIT_TOP downto 0);
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--
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signal DMA_Snout_Length_i : std_logic_vector(C_MAXSIZE_FLD_BIT_TOP downto 0);
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signal DMA_Tail_Length_i : std_logic_vector(C_TLP_FLD_WIDTH_OF_LENG+1 downto 0);
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-- for better timing
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signal raw_Tail_Length : std_logic_vector(C_TLP_FLD_WIDTH_OF_LENG+1 downto 0);
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signal DMA_PA_Snout_Carry : std_logic_vector(CBIT_CARRY downto 0);
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signal DMA_PA_Body_Carry : std_logic_vector(CBIT_CARRY downto 0);
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signal DMA_BAR_Number_i : std_logic_vector(C_ENCODE_BAR_NUMBER-1 downto 0);
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begin
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-- Partition indicators
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No_More_Bodies <= No_More_Bodies_i ;
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ThereIs_Snout <= ThereIs_Snout_i ;
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ThereIs_Body <= ThereIs_Body_i ;
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ThereIs_Tail <= ThereIs_Tail_i ;
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ThereIs_Dex <= ThereIs_Dex_i ;
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HA64bit <= HA64bit_i ;
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Addr_Inc <= Addr_Inc_i ;
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DMA_0_Leng <= DMA_0_Leng_i ;
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--
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DMA_PA_Loaded <= DMA_PA_Loaded_i ;
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DMA_PA_Var <= DMA_PA_Var_i ;
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DMA_HA_Var <= DMA_HA_Var_i ;
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DMA_BDA_fsm <= DMA_BDA_fsm_i ;
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BDA_is_64b_fsm <= BDA_is_64b_fsm_i;
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-- Only for downstream channel
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DMA_PA_Snout <= DMA_PA_current(C_DBUS_WIDTH-1 downto 0);
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DMA_BAR_Number <= DMA_BAR_Number_i;
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-- different lengths
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DMA_Snout_Length <= DMA_Snout_Length_i ;
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DMA_Body_Length <= Max_TLP_Size ;
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DMA_Tail_Length <= DMA_Tail_Length_i ;
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-- Register stubs
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DMA_PA_i <= DMA_PA;
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DMA_HA_i <= DMA_HA;
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DMA_BDA_i <= DMA_BDA;
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DMA_Length_i <= DMA_Length;
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DMA_Control_i <= DMA_Control;
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-- ---------------------------------------------------------------
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-- Parameters should be captured by the start/start2 and be kept
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-- in case Pause command comes.
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--
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Syn_Param_Capture:
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process ( dma_clk, dma_reset)
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begin
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if dma_reset = '1' then
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Addr_Inc_i <= '0';
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use_PA <= '0';
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Dex_is_Last <= '0';
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Engine_Ends <= '1';
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DMA_BAR_Number_i <= (OTHERS=>'0');
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DMA_BDA_fsm_i <= (OTHERS=>'0');
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BDA_is_64b_fsm_i <= '0';
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elsif dma_clk'event and dma_clk = '1' then
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if DMA_Start ='1' or DMA_Start2 ='1' then
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Addr_Inc_i <= DMA_Control_i(CINT_BIT_DMA_CTRL_AINC);
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use_PA <= DMA_Control_i(CINT_BIT_DMA_CTRL_UPA);
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Dex_is_Last <= DMA_Control_i(CINT_BIT_DMA_CTRL_LAST);
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Engine_Ends <= DMA_Control_i(CINT_BIT_DMA_CTRL_END);
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DMA_BAR_Number_i <= DMA_Control_i(CINT_BIT_DMA_CTRL_BAR_TOP downto CINT_BIT_DMA_CTRL_BAR_BOT);
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DMA_BDA_fsm_i <= DMA_BDA_i ;
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BDA_is_64b_fsm_i <= BDA_is_64b ;
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else
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Addr_Inc_i <= Addr_Inc_i ;
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use_PA <= use_PA ;
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Dex_is_Last <= Dex_is_Last ;
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Engine_Ends <= Engine_Ends ;
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DMA_BAR_Number_i <= DMA_BAR_Number_i;
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DMA_BDA_fsm_i <= DMA_BDA_fsm_i ;
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BDA_is_64b_fsm_i <= BDA_is_64b_fsm_i ;
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end if;
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end if;
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end process;
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-- -----------------------------------------------------------------
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-- DMA has zero length.
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-- for sake of timing convergence, divided calculating is used.
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--
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Syn_DMA_0_Leng:
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process ( dma_clk, dma_reset)
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begin
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if dma_reset = '1' then
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DMA_Start_r1 <= '0';
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DMA_Start2_r1 <= '0';
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DMA_Leng_sub <= (OTHERS=>'0');
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DMA_0_Leng_i <= '1';
|
319 |
|
|
|
320 |
|
|
elsif dma_clk'event and dma_clk = '1' then
|
321 |
|
|
|
322 |
|
|
DMA_Start_r1 <= DMA_Start;
|
323 |
|
|
DMA_Start2_r1 <= DMA_Start2;
|
324 |
|
|
if DMA_Length(C_DBUS_WIDTH/2-1 downto C_DBUS_WIDTH/2-8)
|
325 |
|
|
=C_ALL_ZEROS(C_DBUS_WIDTH/2-1 downto C_DBUS_WIDTH/2-8) then
|
326 |
|
|
DMA_Leng_sub(3) <= '0';
|
327 |
|
|
else
|
328 |
|
|
DMA_Leng_sub(3) <= '1';
|
329 |
|
|
end if;
|
330 |
|
|
if DMA_Length(C_DBUS_WIDTH/2-9 downto C_DBUS_WIDTH/2-16)
|
331 |
|
|
=C_ALL_ZEROS(C_DBUS_WIDTH/2-9 downto C_DBUS_WIDTH/2-16) then
|
332 |
|
|
DMA_Leng_sub(2) <= '0';
|
333 |
|
|
else
|
334 |
|
|
DMA_Leng_sub(2) <= '1';
|
335 |
|
|
end if;
|
336 |
|
|
if DMA_Length(C_DBUS_WIDTH/2-17 downto C_DBUS_WIDTH/2-24)
|
337 |
|
|
=C_ALL_ZEROS(C_DBUS_WIDTH/2-17 downto C_DBUS_WIDTH/2-24) then
|
338 |
|
|
DMA_Leng_sub(1) <= '0';
|
339 |
|
|
else
|
340 |
|
|
DMA_Leng_sub(1) <= '1';
|
341 |
|
|
end if;
|
342 |
|
|
if DMA_Length(C_DBUS_WIDTH/2-25 downto 2)
|
343 |
|
|
=C_ALL_ZEROS(C_DBUS_WIDTH/2-25 downto 2) then
|
344 |
|
|
DMA_Leng_sub(0) <= '0';
|
345 |
|
|
else
|
346 |
|
|
DMA_Leng_sub(0) <= '1';
|
347 |
|
|
end if;
|
348 |
|
|
|
349 |
|
|
if DMA_Start_r1 ='1' or DMA_Start2_r1 ='1' then
|
350 |
|
|
if DMA_Leng_sub=C_ALL_ZEROS(4-1 downto 0) then
|
351 |
|
|
DMA_0_Leng_i <= '1';
|
352 |
|
|
else
|
353 |
|
|
DMA_0_Leng_i <= '0';
|
354 |
|
|
end if;
|
355 |
|
|
else
|
356 |
|
|
DMA_0_Leng_i <= DMA_0_Leng_i;
|
357 |
|
|
end if;
|
358 |
|
|
|
359 |
|
|
end if;
|
360 |
|
|
end process;
|
361 |
|
|
|
362 |
|
|
|
363 |
|
|
-- Addr_Inc_i <= DMA_Control_i(CINT_BIT_DMA_CTRL_AINC);
|
364 |
|
|
-- use_PA <= DMA_Control_i(CINT_BIT_DMA_CTRL_UPA);
|
365 |
|
|
-- Dex_is_Last <= DMA_Control_i(CINT_BIT_DMA_CTRL_LAST);
|
366 |
|
|
-- Engine_Ends <= DMA_Control_i(CINT_BIT_DMA_CTRL_END);
|
367 |
|
|
-- use_Irpt_Done <= not DMA_Control_i(CINT_BIT_DMA_CTRL_EDI);
|
368 |
|
|
|
369 |
|
|
|
370 |
|
|
-- Means there is consecutive descriptor(s)
|
371 |
|
|
ThereIs_Dex_i <= not Dex_is_Last and not Engine_Ends;
|
372 |
|
|
|
373 |
|
|
|
374 |
|
|
-- ---------------------------------------------------------------
|
375 |
|
|
-- PA_i selection
|
376 |
|
|
--
|
377 |
|
|
Syn_Calc_DMA_PA:
|
378 |
|
|
process ( dma_clk, dma_reset)
|
379 |
|
|
begin
|
380 |
|
|
if dma_reset = '1' then
|
381 |
|
|
DMA_PA_current <= (Others=>'0');
|
382 |
|
|
PA_is_taken <= '0';
|
383 |
|
|
|
384 |
|
|
elsif dma_clk'event and dma_clk = '1' then
|
385 |
|
|
|
386 |
|
|
if DMA_Start = '1' and PA_is_taken='0' then
|
387 |
|
|
DMA_PA_current <= DMA_PA_i(C_DBUS_WIDTH-1 downto 2) &"00";
|
388 |
|
|
PA_is_taken <= '1';
|
389 |
|
|
elsif DMA_Start2 = '1' and PA_is_taken='0' and DMA_Control_i(CINT_BIT_DMA_CTRL_UPA) = '1' then
|
390 |
|
|
DMA_PA_current <= DMA_PA_i(C_DBUS_WIDTH-1 downto 2) &"00";
|
391 |
|
|
PA_is_taken <= '1';
|
392 |
|
|
elsif DMA_Start2 = '1' and PA_is_taken='0' and DMA_Control_i(CINT_BIT_DMA_CTRL_UPA) = '0' then
|
393 |
|
|
DMA_PA_current(C_DBUS_WIDTH-1 downto 0) <= DMA_PA_next;
|
394 |
|
|
PA_is_taken <= '1';
|
395 |
|
|
else
|
396 |
|
|
DMA_PA_current <= DMA_PA_current;
|
397 |
|
|
if DMA_Start='0' and DMA_Start2='0' then
|
398 |
|
|
PA_is_taken <= '0';
|
399 |
|
|
else
|
400 |
|
|
PA_is_taken <= PA_is_taken;
|
401 |
|
|
end if;
|
402 |
|
|
end if;
|
403 |
|
|
|
404 |
|
|
end if;
|
405 |
|
|
|
406 |
|
|
end process;
|
407 |
|
|
|
408 |
|
|
|
409 |
|
|
-- ---------------------------------------------------------------
|
410 |
|
|
-- PA_next Calculation
|
411 |
|
|
--
|
412 |
|
|
Syn_Calc_DMA_PA_next:
|
413 |
|
|
process ( dma_clk, dma_reset)
|
414 |
|
|
begin
|
415 |
|
|
if dma_reset = '1' then
|
416 |
|
|
DMA_PA_next <= (Others=>'0');
|
417 |
|
|
|
418 |
|
|
elsif dma_clk'event and dma_clk = '1' then
|
419 |
|
|
|
420 |
|
|
if DMA_Start = '1' and PA_is_taken='0' then
|
421 |
|
|
if DMA_Control_i(CINT_BIT_DMA_CTRL_AINC) = '1' then
|
422 |
|
|
DMA_PA_next(CBIT_CARRY-1 downto 0) <= Carry_PA_plus_Leng(CBIT_CARRY-1 downto 0);
|
423 |
|
|
DMA_PA_next(C_DBUS_WIDTH-1 downto CBIT_CARRY) <= Leng_Hi_plus_PA_Hi
|
424 |
|
|
+ Carry_PA_plus_Leng(CBIT_CARRY);
|
425 |
|
|
else
|
426 |
|
|
DMA_PA_next <= DMA_PA_i(C_DBUS_WIDTH-1 downto 2) &"00";
|
427 |
|
|
end if;
|
428 |
|
|
|
429 |
|
|
elsif DMA_Start2 = '1' and PA_is_taken='0' then
|
430 |
|
|
if DMA_Control_i(CINT_BIT_DMA_CTRL_AINC) = '1' then
|
431 |
|
|
DMA_PA_next(CBIT_CARRY-1 downto 0) <= Carry_PAx_plus_Leng(CBIT_CARRY-1 downto 0);
|
432 |
|
|
DMA_PA_next(C_DBUS_WIDTH-1 downto CBIT_CARRY) <= Leng_Hi_plus_PAx_Hi
|
433 |
|
|
+ Carry_PAx_plus_Leng(CBIT_CARRY);
|
434 |
|
|
else
|
435 |
|
|
DMA_PA_next <= DMA_PA_next;
|
436 |
|
|
end if;
|
437 |
|
|
else
|
438 |
|
|
DMA_PA_next <= DMA_PA_next;
|
439 |
|
|
end if;
|
440 |
|
|
|
441 |
|
|
end if;
|
442 |
|
|
|
443 |
|
|
end process;
|
444 |
|
|
|
445 |
|
|
|
446 |
|
|
-- ---------------------------------------------------------------
|
447 |
|
|
-- Carry_PA_plus_Leng(16 downto 0)
|
448 |
|
|
--
|
449 |
|
|
Syn_Calc_Carry_PA_plus_Leng:
|
450 |
|
|
process ( dma_clk, dma_reset)
|
451 |
|
|
begin
|
452 |
|
|
if dma_reset = '1' then
|
453 |
|
|
Carry_PA_plus_Leng <= (Others=>'0');
|
454 |
|
|
|
455 |
|
|
elsif dma_clk'event and dma_clk = '1' then
|
456 |
|
|
Carry_PA_plus_Leng <= ('0'& DMA_PA_i(CBIT_CARRY-1 downto 2) &"00")
|
457 |
|
|
+ ('0'& DMA_Length_i(CBIT_CARRY-1 downto 2) &"00");
|
458 |
|
|
end if;
|
459 |
|
|
|
460 |
|
|
end process;
|
461 |
|
|
|
462 |
|
|
|
463 |
|
|
-- ---------------------------------------------------------------
|
464 |
|
|
-- Carry_PAx_plus_Leng(16 downto 0)
|
465 |
|
|
--
|
466 |
|
|
Syn_Calc_Carry_PAx_plus_Leng:
|
467 |
|
|
process ( dma_clk, dma_reset)
|
468 |
|
|
begin
|
469 |
|
|
if dma_reset = '1' then
|
470 |
|
|
Carry_PAx_plus_Leng <= (Others=>'0');
|
471 |
|
|
|
472 |
|
|
elsif dma_clk'event and dma_clk = '1' then
|
473 |
|
|
Carry_PAx_plus_Leng <= ('0'& DMA_PA_next (CBIT_CARRY-1 downto 2) &"00")
|
474 |
|
|
+ ('0'& DMA_Length_i(CBIT_CARRY-1 downto 2) &"00");
|
475 |
|
|
end if;
|
476 |
|
|
|
477 |
|
|
end process;
|
478 |
|
|
|
479 |
|
|
|
480 |
|
|
-- ---------------------------------------------------------------
|
481 |
|
|
-- Leng_Hi_plus_PA_Hi(31 downto 16)
|
482 |
|
|
--
|
483 |
|
|
Syn_Calc_Leng_Hi_plus_PA_Hi:
|
484 |
|
|
process ( dma_clk, dma_reset)
|
485 |
|
|
begin
|
486 |
|
|
if dma_reset = '1' then
|
487 |
|
|
Leng_Hi_plus_PA_Hi <= (Others=>'0');
|
488 |
|
|
|
489 |
|
|
elsif dma_clk'event and dma_clk = '1' then
|
490 |
|
|
Leng_Hi_plus_PA_Hi <= DMA_Length_i(C_DBUS_WIDTH-1 downto CBIT_CARRY)
|
491 |
|
|
+ DMA_PA_i(C_DBUS_WIDTH-1 downto CBIT_CARRY);
|
492 |
|
|
|
493 |
|
|
end if;
|
494 |
|
|
|
495 |
|
|
end process;
|
496 |
|
|
|
497 |
|
|
|
498 |
|
|
-- ---------------------------------------------------------------
|
499 |
|
|
-- Leng_Hi_plus_PAx_Hi(31 downto 16)
|
500 |
|
|
--
|
501 |
|
|
Syn_Calc_Leng_Hi_plus_PAx_Hi:
|
502 |
|
|
process ( dma_clk, dma_reset)
|
503 |
|
|
begin
|
504 |
|
|
if dma_reset = '1' then
|
505 |
|
|
Leng_Hi_plus_PAx_Hi <= (Others=>'0');
|
506 |
|
|
|
507 |
|
|
elsif dma_clk'event and dma_clk = '1' then
|
508 |
|
|
Leng_Hi_plus_PAx_Hi <= DMA_Length_i(C_DBUS_WIDTH-1 downto CBIT_CARRY)
|
509 |
|
|
+ DMA_PA_next(C_DBUS_WIDTH-1 downto CBIT_CARRY);
|
510 |
|
|
|
511 |
|
|
end if;
|
512 |
|
|
|
513 |
|
|
end process;
|
514 |
|
|
|
515 |
|
|
|
516 |
|
|
-- -----------------------------------------------------------------------------------------------------------------------------------
|
517 |
|
|
DMA_Leng_Left_Msk <= DMA_Length_i(C_MAXSIZE_FLD_BIT_TOP downto C_MAXSIZE_FLD_BIT_BOT) and mxsz_left;
|
518 |
|
|
DMA_Leng_Mid_Msk <= DMA_Length_i(C_MAXSIZE_FLD_BIT_TOP downto C_MAXSIZE_FLD_BIT_BOT) and mxsz_mid;
|
519 |
|
|
DMA_Leng_Right_Msk <= DMA_Length_i(C_MAXSIZE_FLD_BIT_TOP downto C_MAXSIZE_FLD_BIT_BOT) and mxsz_right;
|
520 |
|
|
|
521 |
|
|
-- -----------------------------------------------------------------------------------------------------------------------------------
|
522 |
|
|
DMA_HA_Msk <= (DMA_HA_i(C_MAXSIZE_FLD_BIT_TOP downto C_MAXSIZE_FLD_BIT_BOT) and mxsz_right)
|
523 |
|
|
& DMA_HA_i(C_MAXSIZE_FLD_BIT_BOT-1 downto 2)
|
524 |
|
|
& "00";
|
525 |
|
|
DMA_Length_Msk <= (DMA_Length_i(C_MAXSIZE_FLD_BIT_TOP downto C_MAXSIZE_FLD_BIT_BOT) and mxsz_right)
|
526 |
|
|
& DMA_Length_i(C_MAXSIZE_FLD_BIT_BOT-1 downto 2)
|
527 |
|
|
& "00";
|
528 |
|
|
|
529 |
|
|
-- -----------------------------------------------------------------------------------------------------------------------------------
|
530 |
|
|
Lo_Leng_Left_Msk_is_True <= '0' when DMA_Leng_Left_Msk =C_ALL_ZEROS(C_MAXSIZE_FLD_BIT_TOP downto C_MAXSIZE_FLD_BIT_BOT) else '1';
|
531 |
|
|
Lo_Leng_Mid_Msk_is_True <= '0' when DMA_Leng_Mid_Msk =C_ALL_ZEROS(C_MAXSIZE_FLD_BIT_TOP downto C_MAXSIZE_FLD_BIT_BOT) else '1';
|
532 |
|
|
Lo_Leng_Right_Msk_is_True <= '0' when DMA_Leng_Right_Msk=C_ALL_ZEROS(C_MAXSIZE_FLD_BIT_TOP downto C_MAXSIZE_FLD_BIT_BOT) else '1';
|
533 |
|
|
|
534 |
|
|
|
535 |
|
|
-- ----------------------------------------------------------
|
536 |
|
|
-- Synchronous Register: Leng_Info(Compressed Length Information)
|
537 |
|
|
---
|
538 |
|
|
Syn_Calc_Parameter_Leng_Info:
|
539 |
|
|
process ( dma_clk, dma_reset)
|
540 |
|
|
begin
|
541 |
|
|
if dma_reset = '1' then
|
542 |
|
|
Leng_Two <= '0';
|
543 |
|
|
Leng_One <= '0';
|
544 |
|
|
Leng_nint <= '0';
|
545 |
|
|
|
546 |
|
|
elsif dma_clk'event and dma_clk = '1' then
|
547 |
|
|
Leng_Two <= Leng_Hi19b_True or Lo_Leng_Left_Msk_is_True;
|
548 |
|
|
Leng_One <= Lo_Leng_Mid_Msk_is_True;
|
549 |
|
|
Leng_nint <= Leng_Lo7b_True or Lo_Leng_Right_Msk_is_True;
|
550 |
|
|
|
551 |
|
|
end if;
|
552 |
|
|
end process;
|
553 |
|
|
|
554 |
|
|
|
555 |
|
|
-- -----------------------------------------------------------------------------------------------------------------------------------
|
556 |
|
|
ALc_B_wire <= '0' when (ALc(C_MAXSIZE_FLD_BIT_TOP downto C_MAXSIZE_FLD_BIT_BOT) and mxsz_mid)=C_ALL_ZEROS(C_MAXSIZE_FLD_BIT_TOP downto C_MAXSIZE_FLD_BIT_BOT)
|
557 |
|
|
else '1';
|
558 |
|
|
ALc_T_wire <= '0' when (ALc(C_MAXSIZE_FLD_BIT_TOP downto C_MAXSIZE_FLD_BIT_BOT) and mxsz_right)=C_ALL_ZEROS(C_MAXSIZE_FLD_BIT_TOP downto C_MAXSIZE_FLD_BIT_BOT)
|
559 |
|
|
and ALc(C_MAXSIZE_FLD_BIT_BOT-1 downto 0)=C_ALL_ZEROS(C_MAXSIZE_FLD_BIT_BOT-1 downto 0)
|
560 |
|
|
else '1';
|
561 |
|
|
-- -----------------------------------------------------------------------------------------------------------------------------------
|
562 |
|
|
|
563 |
|
|
-- -------------------------------------------------------
|
564 |
|
|
-- Synchronous Register: ALc (Address-Length combination)
|
565 |
|
|
---
|
566 |
|
|
Syn_Calc_Parameter_ALc:
|
567 |
|
|
process ( dma_clk, dma_reset)
|
568 |
|
|
begin
|
569 |
|
|
if dma_reset = '1' then
|
570 |
|
|
ALc <= (Others=>'0');
|
571 |
|
|
ALc_B <= '0';
|
572 |
|
|
ALc_T <= '0';
|
573 |
|
|
|
574 |
|
|
elsif dma_clk'event and dma_clk = '1' then
|
575 |
|
|
|
576 |
|
|
ALc <= DMA_Length_Msk + DMA_HA_Msk;
|
577 |
|
|
ALc_B <= ALc_B_wire;
|
578 |
|
|
ALc_T <= ALc_T_wire;
|
579 |
|
|
|
580 |
|
|
end if;
|
581 |
|
|
|
582 |
|
|
end process;
|
583 |
|
|
|
584 |
|
|
|
585 |
|
|
-- concatenation of the Length information
|
586 |
|
|
Length_analysis <= Leng_Two & Leng_One & Leng_nint;
|
587 |
|
|
|
588 |
|
|
-- -------------------------------------------
|
589 |
|
|
-- Analysis on the DMA division
|
590 |
|
|
-- truth-table expressions
|
591 |
|
|
--
|
592 |
|
|
Comb_S_B_T:
|
593 |
|
|
process (
|
594 |
|
|
Length_analysis
|
595 |
|
|
, ALc_B
|
596 |
|
|
, ALc_T
|
597 |
|
|
)
|
598 |
|
|
begin
|
599 |
|
|
case Length_analysis is
|
600 |
|
|
|
601 |
|
|
-- Zero-length DMA, nothing to send
|
602 |
|
|
when "000" =>
|
603 |
|
|
Snout_Body_Tail <= "000";
|
604 |
|
|
|
605 |
|
|
-- Length < Max_Size. Always Snout and never Body, Tail depends on ALc.
|
606 |
|
|
when "001" =>
|
607 |
|
|
Snout_Body_Tail <= '1' & '0' & (ALc_B and ALc_T);
|
608 |
|
|
|
609 |
|
|
-- Length = Max_Size. Division depends only on ALc-Tail.
|
610 |
|
|
when "010" =>
|
611 |
|
|
Snout_Body_Tail <= ALc_T & not ALc_T & ALc_T;
|
612 |
|
|
-- Length = (k+1) Max_Size, k>=1. Always Body. Snout and Tail depend on ALc-Tail.
|
613 |
|
|
-- Body = Leng_Two or not ALc_T
|
614 |
|
|
when "100" =>
|
615 |
|
|
Snout_Body_Tail <= ALc_T & '1' & ALc_T;
|
616 |
|
|
when "110" =>
|
617 |
|
|
Snout_Body_Tail <= ALc_T & '1' & ALc_T;
|
618 |
|
|
|
619 |
|
|
-- Length = (1+d) Max_Size, 0<d<1. Always Snout. Body and Tail copy ALc.
|
620 |
|
|
when "011" =>
|
621 |
|
|
Snout_Body_Tail <= '1' & ALc_B & ALc_T;
|
622 |
|
|
-- Length = (k+1+d) Max_Size, k>=1, 0<d<1. Always Snout and Body. Tail copies ALc-Tail.
|
623 |
|
|
-- Body = Leng_Two or ALc_B
|
624 |
|
|
when "101" =>
|
625 |
|
|
Snout_Body_Tail <= '1' & '1' & ALc_T;
|
626 |
|
|
when "111" =>
|
627 |
|
|
Snout_Body_Tail <= '1' & '1' & ALc_T;
|
628 |
|
|
|
629 |
|
|
-- dealt as zero-length DMA
|
630 |
|
|
when Others =>
|
631 |
|
|
Snout_Body_Tail <= "000";
|
632 |
|
|
|
633 |
|
|
end case;
|
634 |
|
|
|
635 |
|
|
end process;
|
636 |
|
|
|
637 |
|
|
-- -----------------------------------------------
|
638 |
|
|
-- Synchronous Register:
|
639 |
|
|
-- ThereIs_Snout
|
640 |
|
|
-- ThereIs_Body
|
641 |
|
|
-- ThereIs_Tail
|
642 |
|
|
--
|
643 |
|
|
Syn_Calc_Parameters_SBT:
|
644 |
|
|
process ( dma_clk, dma_reset)
|
645 |
|
|
begin
|
646 |
|
|
if dma_reset = '1' then
|
647 |
|
|
ThereIs_Snout_i <= '0';
|
648 |
|
|
ThereIs_Body_i <= '0';
|
649 |
|
|
ThereIs_Tail_i <= '0';
|
650 |
|
|
|
651 |
|
|
Snout_Only <= '0';
|
652 |
|
|
|
653 |
|
|
elsif dma_clk'event and dma_clk = '1' then
|
654 |
|
|
|
655 |
|
|
ThereIs_Snout_i <= Snout_Body_Tail(2);
|
656 |
|
|
ThereIs_Body_i <= Snout_Body_Tail(1);
|
657 |
|
|
ThereIs_Tail_i <= Snout_Body_Tail(0);
|
658 |
|
|
|
659 |
|
|
Snout_Only <= ALc_T and not Snout_Body_Tail(0);
|
660 |
|
|
|
661 |
|
|
end if;
|
662 |
|
|
|
663 |
|
|
end process;
|
664 |
|
|
|
665 |
|
|
|
666 |
|
|
-- -------------------------------------------------------------
|
667 |
|
|
-- Synchronous reg:
|
668 |
|
|
-- HA_gap
|
669 |
|
|
--
|
670 |
|
|
Syn_Calc_HA_gap:
|
671 |
|
|
process ( dma_clk, dma_reset)
|
672 |
|
|
begin
|
673 |
|
|
if dma_reset = '1' then
|
674 |
|
|
HA_gap <= (OTHERS =>'0');
|
675 |
|
|
|
676 |
|
|
elsif dma_clk'event and dma_clk = '1' then
|
677 |
|
|
HA_gap <= Max_TLP_Size - DMA_HA_Msk;
|
678 |
|
|
end if;
|
679 |
|
|
end process;
|
680 |
|
|
|
681 |
|
|
|
682 |
|
|
-- -------------------------------------------------------------
|
683 |
|
|
-- Synchronous reg:
|
684 |
|
|
-- DMA_PA_Snout_Carry
|
685 |
|
|
--
|
686 |
|
|
FSM_Calc_DMA_PA_Snout_Carry:
|
687 |
|
|
process ( dma_clk, dma_reset)
|
688 |
|
|
begin
|
689 |
|
|
if dma_reset = '1' then
|
690 |
|
|
DMA_PA_Snout_Carry <= (OTHERS =>'0');
|
691 |
|
|
|
692 |
|
|
elsif dma_clk'event and dma_clk = '1' then
|
693 |
|
|
DMA_PA_Snout_Carry <= ('0'& DMA_PA_current(CBIT_CARRY-1 downto 0)) + HA_gap;
|
694 |
|
|
|
695 |
|
|
end if;
|
696 |
|
|
end process;
|
697 |
|
|
|
698 |
|
|
|
699 |
|
|
-- -------------------------------------------------------------
|
700 |
|
|
-- Synchronous reg:
|
701 |
|
|
-- DMA_PA_Body_Carry
|
702 |
|
|
--
|
703 |
|
|
FSM_Calc_DMA_PA_Body_Carry:
|
704 |
|
|
process ( dma_clk, dma_reset)
|
705 |
|
|
begin
|
706 |
|
|
if dma_reset = '1' then
|
707 |
|
|
DMA_PA_Body_Carry <= (OTHERS =>'0');
|
708 |
|
|
|
709 |
|
|
elsif dma_clk'event and dma_clk = '1' then
|
710 |
|
|
DMA_PA_Body_Carry <= ('0'& DMA_PA_Var_i(CBIT_CARRY-1 downto 0)) + Max_TLP_Size;
|
711 |
|
|
end if;
|
712 |
|
|
end process;
|
713 |
|
|
|
714 |
|
|
|
715 |
|
|
-- ------------------------------------------------------------------
|
716 |
|
|
-- Synchronous Register: Length_minus
|
717 |
|
|
--
|
718 |
|
|
Sync_Calc_Length_minus:
|
719 |
|
|
process ( dma_clk, dma_reset)
|
720 |
|
|
begin
|
721 |
|
|
if dma_reset = '1' then
|
722 |
|
|
Length_minus <= (OTHERS =>'0');
|
723 |
|
|
|
724 |
|
|
elsif dma_clk'event and dma_clk = '1' then
|
725 |
|
|
Length_minus <= DMA_Length_i - Max_TLP_Size;
|
726 |
|
|
|
727 |
|
|
end if;
|
728 |
|
|
end process;
|
729 |
|
|
|
730 |
|
|
|
731 |
|
|
-- -------------------------------------------------------------
|
732 |
|
|
-- Synchronous reg:
|
733 |
|
|
-- DMA_BC_Carry
|
734 |
|
|
--
|
735 |
|
|
FSM_Calc_DMA_BC_Carry:
|
736 |
|
|
process ( dma_clk, dma_reset)
|
737 |
|
|
begin
|
738 |
|
|
if dma_reset = '1' then
|
739 |
|
|
DMA_BC_Carry <= (OTHERS =>'0');
|
740 |
|
|
|
741 |
|
|
elsif dma_clk'event and dma_clk = '1' then
|
742 |
|
|
DMA_BC_Carry <= ('0'& DMA_Byte_Counter(CBIT_CARRY-1 downto 0)) - Max_TLP_Size;
|
743 |
|
|
|
744 |
|
|
end if;
|
745 |
|
|
end process;
|
746 |
|
|
|
747 |
|
|
|
748 |
|
|
-- --------------------------------------------
|
749 |
|
|
-- Synchronous reg: DMA_Snout_Length
|
750 |
|
|
-- DMA_Tail_Length
|
751 |
|
|
--
|
752 |
|
|
FSM_Calc_DMA_Snout_Tail_Lengths:
|
753 |
|
|
process ( dma_clk, dma_reset)
|
754 |
|
|
begin
|
755 |
|
|
if dma_reset = '1' then
|
756 |
|
|
DMA_Snout_Length_i <= (OTHERS =>'0');
|
757 |
|
|
DMA_Tail_Length_i <= (OTHERS =>'0');
|
758 |
|
|
raw_Tail_Length <= (OTHERS =>'0');
|
759 |
|
|
|
760 |
|
|
elsif dma_clk'event and dma_clk = '1' then
|
761 |
|
|
|
762 |
|
|
DMA_Tail_Length_i(C_TLP_FLD_WIDTH_OF_LENG+1 downto 0) <= (raw_Tail_Length(C_TLP_FLD_WIDTH_OF_LENG+1 downto C_MAXSIZE_FLD_BIT_BOT)
|
763 |
|
|
and mxsz_right(C_TLP_FLD_WIDTH_OF_LENG+1 downto C_MAXSIZE_FLD_BIT_BOT)
|
764 |
|
|
) & raw_Tail_Length( C_MAXSIZE_FLD_BIT_BOT-1 downto 0);
|
765 |
|
|
if State_Is_LoadParam ='1' then
|
766 |
|
|
raw_Tail_Length(C_TLP_FLD_WIDTH_OF_LENG+1 downto 0) <= DMA_Length_Msk(C_TLP_FLD_WIDTH_OF_LENG+1 downto 0)
|
767 |
|
|
+ DMA_HA_Msk(C_TLP_FLD_WIDTH_OF_LENG+1 downto 0);
|
768 |
|
|
if Snout_Only='1' then
|
769 |
|
|
DMA_Snout_Length_i <= DMA_Length_i(C_MAXSIZE_FLD_BIT_TOP downto 2) &"00";
|
770 |
|
|
else
|
771 |
|
|
DMA_Snout_Length_i <= Max_TLP_Size - DMA_HA_Msk;
|
772 |
|
|
end if;
|
773 |
|
|
|
774 |
|
|
else
|
775 |
|
|
DMA_Snout_Length_i <= DMA_Snout_Length_i;
|
776 |
|
|
raw_Tail_Length <= raw_Tail_Length;
|
777 |
|
|
|
778 |
|
|
end if;
|
779 |
|
|
|
780 |
|
|
end if;
|
781 |
|
|
end process;
|
782 |
|
|
|
783 |
|
|
|
784 |
|
|
-- -------------------------------------------------------------
|
785 |
|
|
-- Synchronous Delays:
|
786 |
|
|
-- State_Is_Snout_r1
|
787 |
|
|
-- State_Is_Body_r1
|
788 |
|
|
--
|
789 |
|
|
Syn_Delay_State_is_x:
|
790 |
|
|
process ( dma_clk )
|
791 |
|
|
begin
|
792 |
|
|
if dma_clk'event and dma_clk = '1' then
|
793 |
|
|
State_Is_Snout_r1 <= State_Is_Snout;
|
794 |
|
|
State_Is_Body_r1 <= State_Is_Body;
|
795 |
|
|
end if;
|
796 |
|
|
|
797 |
|
|
end process;
|
798 |
|
|
|
799 |
|
|
|
800 |
|
|
-- -------------------------------------------------------------
|
801 |
|
|
-- Synchronous reg:
|
802 |
|
|
-- DMA_HA_Carry32
|
803 |
|
|
--
|
804 |
|
|
FSM_Calc_DMA_HA_Carry32:
|
805 |
|
|
process ( dma_clk, dma_reset)
|
806 |
|
|
begin
|
807 |
|
|
if dma_reset = '1' then
|
808 |
|
|
DMA_HA_Carry32 <= (OTHERS =>'0');
|
809 |
|
|
|
810 |
|
|
elsif dma_clk'event and dma_clk = '1' then
|
811 |
|
|
|
812 |
|
|
if State_Is_LoadParam = '1' then
|
813 |
|
|
DMA_HA_Carry32 <= '0' & DMA_HA_i(C_DBUS_WIDTH/2-1 downto 2) & "00"; -- temp
|
814 |
|
|
|
815 |
|
|
elsif State_Is_Snout = '1' or State_Is_Body = '1' then
|
816 |
|
|
DMA_HA_Carry32(C_DBUS_WIDTH/2 downto C_MAXSIZE_FLD_BIT_BOT) <= ('0'& DMA_HA_Var_i(C_DBUS_WIDTH/2-1 downto C_MAXSIZE_FLD_BIT_TOP+1) &
|
817 |
|
|
(DMA_HA_Var_i(C_MAXSIZE_FLD_BIT_TOP downto C_MAXSIZE_FLD_BIT_BOT) and not mxsz_right)
|
818 |
|
|
) + mxsz_mid;
|
819 |
|
|
|
820 |
|
|
else
|
821 |
|
|
DMA_HA_Carry32 <= DMA_HA_Carry32;
|
822 |
|
|
|
823 |
|
|
end if;
|
824 |
|
|
|
825 |
|
|
end if;
|
826 |
|
|
end process;
|
827 |
|
|
|
828 |
|
|
|
829 |
|
|
|
830 |
|
|
-- -------------------------------------------------------------
|
831 |
|
|
-- Synchronous reg:
|
832 |
|
|
-- DMA_HA_Var
|
833 |
|
|
--
|
834 |
|
|
FSM_Calc_DMA_HA_Var:
|
835 |
|
|
process ( dma_clk, dma_reset)
|
836 |
|
|
begin
|
837 |
|
|
if dma_reset = '1' then
|
838 |
|
|
DMA_HA_Var_i <= (OTHERS =>'0');
|
839 |
|
|
|
840 |
|
|
elsif dma_clk'event and dma_clk = '1' then
|
841 |
|
|
|
842 |
|
|
if State_Is_LoadParam = '1' then
|
843 |
|
|
DMA_HA_Var_i <= DMA_HA_i(C_DBUS_WIDTH-1 downto 2) & "00"; -- temp
|
844 |
|
|
|
845 |
|
|
elsif State_Is_Snout_r1 = '1' or State_Is_Body_r1 = '1' then
|
846 |
|
|
-- elsif State_Is_Snout = '1' or State_Is_Body = '1' then
|
847 |
|
|
DMA_HA_Var_i(C_DBUS_WIDTH-1 downto C_DBUS_WIDTH/2) <= DMA_HA_Var_i(C_DBUS_WIDTH-1 downto C_DBUS_WIDTH/2)
|
848 |
|
|
+ DMA_HA_Carry32(C_DBUS_WIDTH/2);
|
849 |
|
|
|
850 |
|
|
DMA_HA_Var_i(C_DBUS_WIDTH-1 downto C_MAXSIZE_FLD_BIT_BOT) <= (DMA_HA_Var_i(C_DBUS_WIDTH-1 downto C_MAXSIZE_FLD_BIT_TOP+1)
|
851 |
|
|
& (DMA_HA_Var_i(C_MAXSIZE_FLD_BIT_TOP downto C_MAXSIZE_FLD_BIT_BOT) and not mxsz_right))
|
852 |
|
|
+ mxsz_mid;
|
853 |
|
|
DMA_HA_Var_i(C_MAXSIZE_FLD_BIT_BOT-1 downto 0) <= (Others => '0'); -- MaxSize aligned
|
854 |
|
|
|
855 |
|
|
else
|
856 |
|
|
DMA_HA_Var_i <= DMA_HA_Var_i;
|
857 |
|
|
|
858 |
|
|
end if;
|
859 |
|
|
|
860 |
|
|
end if;
|
861 |
|
|
end process;
|
862 |
|
|
|
863 |
|
|
|
864 |
|
|
-- -------------------------------------------------------------
|
865 |
|
|
-- Synchronous reg:
|
866 |
|
|
-- HA64bit
|
867 |
|
|
--
|
868 |
|
|
FSM_Calc_HA64bit:
|
869 |
|
|
process ( dma_clk, dma_reset)
|
870 |
|
|
begin
|
871 |
|
|
if dma_reset = '1' then
|
872 |
|
|
HA64bit_i <= '0';
|
873 |
|
|
|
874 |
|
|
elsif dma_clk'event and dma_clk = '1' then
|
875 |
|
|
|
876 |
|
|
if State_Is_LoadParam = '1' then
|
877 |
|
|
HA64bit_i <= HA_is_64b;
|
878 |
|
|
elsif DMA_HA_Carry32(C_DBUS_WIDTH/2) = '1' then
|
879 |
|
|
HA64bit_i <= '1';
|
880 |
|
|
else
|
881 |
|
|
HA64bit_i <= HA64bit_i;
|
882 |
|
|
end if;
|
883 |
|
|
|
884 |
|
|
end if;
|
885 |
|
|
end process;
|
886 |
|
|
|
887 |
|
|
|
888 |
|
|
-- -------------------------------------------------------------
|
889 |
|
|
-- Synchronous reg:
|
890 |
|
|
-- DMA_PA_Var
|
891 |
|
|
--
|
892 |
|
|
FSM_Calc_DMA_PA_Var:
|
893 |
|
|
process ( dma_clk, dma_reset)
|
894 |
|
|
begin
|
895 |
|
|
if dma_reset = '1' then
|
896 |
|
|
DMA_PA_Var_i <= (OTHERS =>'0');
|
897 |
|
|
|
898 |
|
|
elsif dma_clk'event and dma_clk = '1' then
|
899 |
|
|
|
900 |
|
|
if State_Is_LoadParam = '1' then
|
901 |
|
|
if Addr_Inc_i='1' and ThereIs_Snout_i='1' then
|
902 |
|
|
DMA_PA_Var_i(CBIT_CARRY-1 downto 0) <= DMA_PA_current(CBIT_CARRY-1 downto 0)
|
903 |
|
|
+ HA_gap(C_MAXSIZE_FLD_BIT_TOP downto 0);
|
904 |
|
|
DMA_PA_Var_i(C_DBUS_WIDTH-1 downto CBIT_CARRY) <= DMA_PA_current(C_DBUS_WIDTH-1 downto CBIT_CARRY);
|
905 |
|
|
else
|
906 |
|
|
DMA_PA_Var_i(C_DBUS_WIDTH-1 downto 0) <= DMA_PA_current(C_DBUS_WIDTH-1 downto 0);
|
907 |
|
|
end if;
|
908 |
|
|
|
909 |
|
|
elsif State_Is_Snout_r1 = '1' then
|
910 |
|
|
---- elsif State_Is_Snout = '1' then
|
911 |
|
|
if Addr_Inc_i= '1' then
|
912 |
|
|
DMA_PA_Var_i(CBIT_CARRY-1 downto 0) <= DMA_PA_Var_i(CBIT_CARRY-1 downto 0);
|
913 |
|
|
DMA_PA_Var_i(C_DBUS_WIDTH-1 downto CBIT_CARRY) <= DMA_PA_Var_i(C_DBUS_WIDTH-1 downto CBIT_CARRY)
|
914 |
|
|
+ DMA_PA_Snout_Carry(CBIT_CARRY);
|
915 |
|
|
else
|
916 |
|
|
DMA_PA_Var_i <= DMA_PA_Var_i;
|
917 |
|
|
end if;
|
918 |
|
|
|
919 |
|
|
elsif State_Is_Body_r1 = '1' then
|
920 |
|
|
---- elsif State_Is_Body = '1' then
|
921 |
|
|
if Addr_Inc_i= '1' then
|
922 |
|
|
DMA_PA_Var_i(CBIT_CARRY-1 downto 0) <= DMA_PA_Body_Carry(CBIT_CARRY-1 downto 0);
|
923 |
|
|
DMA_PA_Var_i(C_DBUS_WIDTH-1 downto CBIT_CARRY) <= DMA_PA_Var_i(C_DBUS_WIDTH-1 downto CBIT_CARRY)
|
924 |
|
|
+ DMA_PA_Body_Carry(CBIT_CARRY);
|
925 |
|
|
else
|
926 |
|
|
DMA_PA_Var_i <= DMA_PA_Var_i;
|
927 |
|
|
end if;
|
928 |
|
|
|
929 |
|
|
else
|
930 |
|
|
DMA_PA_Var_i <= DMA_PA_Var_i;
|
931 |
|
|
|
932 |
|
|
end if;
|
933 |
|
|
|
934 |
|
|
end if;
|
935 |
|
|
end process;
|
936 |
|
|
|
937 |
|
|
|
938 |
|
|
-- -------------------------------------------------------------
|
939 |
|
|
-- Synchronous reg:
|
940 |
|
|
-- DMA_PA_Loaded_i
|
941 |
|
|
--
|
942 |
|
|
FSM_Calc_DMA_PA_Loaded_i:
|
943 |
|
|
process ( dma_clk, dma_reset)
|
944 |
|
|
begin
|
945 |
|
|
if dma_reset = '1' then
|
946 |
|
|
DMA_PA_Loaded_i <= (OTHERS =>'0');
|
947 |
|
|
|
948 |
|
|
elsif dma_clk'event and dma_clk = '1' then
|
949 |
|
|
|
950 |
|
|
if State_Is_LoadParam = '1' then
|
951 |
|
|
DMA_PA_Loaded_i <= DMA_PA_current(C_DBUS_WIDTH-1 downto 0);
|
952 |
|
|
else
|
953 |
|
|
DMA_PA_Loaded_i <= DMA_PA_Loaded_i;
|
954 |
|
|
end if;
|
955 |
|
|
|
956 |
|
|
end if;
|
957 |
|
|
end process;
|
958 |
|
|
|
959 |
|
|
|
960 |
|
|
-- -------------------------------------------------------------
|
961 |
|
|
-- Synchronous reg: DMA_Byte_Counter
|
962 |
|
|
---
|
963 |
|
|
FSM_Calc_DMA_Byte_Counter:
|
964 |
|
|
process ( dma_clk, dma_reset)
|
965 |
|
|
begin
|
966 |
|
|
if dma_reset = '1' then
|
967 |
|
|
DMA_Byte_Counter <= (OTHERS =>'0');
|
968 |
|
|
|
969 |
|
|
elsif dma_clk'event and dma_clk = '1' then
|
970 |
|
|
|
971 |
|
|
if State_Is_LoadParam = '1' then
|
972 |
|
|
if ALc_B='0' and ALc_T='1' then
|
973 |
|
|
DMA_Byte_Counter <= Length_minus;
|
974 |
|
|
else
|
975 |
|
|
DMA_Byte_Counter <= DMA_Length_i(C_DBUS_WIDTH-1 downto 2) & "00";
|
976 |
|
|
end if;
|
977 |
|
|
|
978 |
|
|
-- elsif State_Is_Body_r1 = '1' then
|
979 |
|
|
elsif State_Is_Body = '1' then
|
980 |
|
|
DMA_Byte_Counter(C_DBUS_WIDTH-1 downto CBIT_CARRY) <= DMA_Byte_Counter(C_DBUS_WIDTH-1 downto CBIT_CARRY)
|
981 |
|
|
- DMA_BC_Carry(CBIT_CARRY);
|
982 |
|
|
DMA_Byte_Counter(CBIT_CARRY-1 downto C_MAXSIZE_FLD_BIT_BOT) <= DMA_BC_Carry(CBIT_CARRY-1 downto C_MAXSIZE_FLD_BIT_BOT);
|
983 |
|
|
else
|
984 |
|
|
DMA_Byte_Counter <= DMA_Byte_Counter;
|
985 |
|
|
end if;
|
986 |
|
|
|
987 |
|
|
end if;
|
988 |
|
|
end process;
|
989 |
|
|
|
990 |
|
|
|
991 |
|
|
-- -------------------------------------------------------------
|
992 |
|
|
-- Synchronous reg: No_More_Bodies
|
993 |
|
|
---
|
994 |
|
|
FSM_Calc_No_More_Bodies:
|
995 |
|
|
process ( dma_clk, dma_reset)
|
996 |
|
|
begin
|
997 |
|
|
if dma_reset = '1' then
|
998 |
|
|
No_More_Bodies_i <= '0';
|
999 |
|
|
|
1000 |
|
|
elsif dma_clk'event and dma_clk = '1' then
|
1001 |
|
|
|
1002 |
|
|
if State_Is_LoadParam = '1' then
|
1003 |
|
|
No_More_Bodies_i <= not ThereIs_Body_i;
|
1004 |
|
|
|
1005 |
|
|
-- elsif State_Is_Body_r1 = '1' then
|
1006 |
|
|
elsif State_Is_Body = '1' then
|
1007 |
|
|
if DMA_Byte_Counter(C_DBUS_WIDTH-1 downto C_MAXSIZE_FLD_BIT_TOP+1)=C_ALL_ZEROS(C_DBUS_WIDTH-1 downto C_MAXSIZE_FLD_BIT_TOP+1)
|
1008 |
|
|
and (DMA_Byte_Counter(C_MAXSIZE_FLD_BIT_TOP downto C_MAXSIZE_FLD_BIT_BOT) and mxsz_left)=C_ALL_ZEROS(C_MAXSIZE_FLD_BIT_TOP downto C_MAXSIZE_FLD_BIT_BOT)
|
1009 |
|
|
and (DMA_Byte_Counter(C_MAXSIZE_FLD_BIT_TOP downto C_MAXSIZE_FLD_BIT_BOT) and mxsz_mid)/=C_ALL_ZEROS(C_MAXSIZE_FLD_BIT_TOP downto C_MAXSIZE_FLD_BIT_BOT)
|
1010 |
|
|
then
|
1011 |
|
|
No_More_Bodies_i <= '1';
|
1012 |
|
|
else
|
1013 |
|
|
No_More_Bodies_i <= '0';
|
1014 |
|
|
end if;
|
1015 |
|
|
|
1016 |
|
|
else
|
1017 |
|
|
No_More_Bodies_i <= No_More_Bodies_i;
|
1018 |
|
|
end if;
|
1019 |
|
|
|
1020 |
|
|
end if;
|
1021 |
|
|
end process;
|
1022 |
|
|
|
1023 |
|
|
|
1024 |
|
|
-- ------------------------------------------
|
1025 |
|
|
-- Configuration pamameters: Param_Max_Cfg
|
1026 |
|
|
--
|
1027 |
|
|
Syn_Config_Param_Max_Cfg:
|
1028 |
|
|
process ( dma_clk, dma_reset)
|
1029 |
|
|
begin
|
1030 |
|
|
if dma_reset = '1' then -- 0x0080 Bytes
|
1031 |
|
|
mxsz_left <= "111110"; -- 6 bits
|
1032 |
|
|
mxsz_mid <= "000001"; -- 6 bits
|
1033 |
|
|
mxsz_right <= "000000"; -- 6 bits
|
1034 |
|
|
|
1035 |
|
|
elsif dma_clk'event and dma_clk = '1' then
|
1036 |
|
|
|
1037 |
|
|
case Param_Max_Cfg is
|
1038 |
|
|
|
1039 |
|
|
when "000" => -- 0x0080 Bytes
|
1040 |
|
|
mxsz_left <= "111110";
|
1041 |
|
|
mxsz_mid <= "000001";
|
1042 |
|
|
mxsz_right <= "000000";
|
1043 |
|
|
|
1044 |
|
|
when "001" => -- 0x0100 Bytes
|
1045 |
|
|
mxsz_left <= "111100";
|
1046 |
|
|
mxsz_mid <= "000010";
|
1047 |
|
|
mxsz_right <= "000001";
|
1048 |
|
|
|
1049 |
|
|
when "010" => -- 0x0200 Bytes
|
1050 |
|
|
mxsz_left <= "111000";
|
1051 |
|
|
mxsz_mid <= "000100";
|
1052 |
|
|
mxsz_right <= "000011";
|
1053 |
|
|
|
1054 |
|
|
when "011" => -- 0x0400 Bytes
|
1055 |
|
|
mxsz_left <= "110000";
|
1056 |
|
|
mxsz_mid <= "001000";
|
1057 |
|
|
mxsz_right <= "000111";
|
1058 |
|
|
|
1059 |
|
|
when "100" => -- 0x0800 Bytes
|
1060 |
|
|
mxsz_left <= "100000";
|
1061 |
|
|
mxsz_mid <= "010000";
|
1062 |
|
|
mxsz_right <= "001111";
|
1063 |
|
|
|
1064 |
|
|
when "101" => -- 0x1000 Bytes
|
1065 |
|
|
mxsz_left <= "000000";
|
1066 |
|
|
mxsz_mid <= "100000";
|
1067 |
|
|
mxsz_right <= "011111";
|
1068 |
|
|
|
1069 |
|
|
when Others => -- as 0x0080 Bytes
|
1070 |
|
|
mxsz_left <= "111110";
|
1071 |
|
|
mxsz_mid <= "000001";
|
1072 |
|
|
mxsz_right <= "000000";
|
1073 |
|
|
|
1074 |
|
|
end case;
|
1075 |
|
|
|
1076 |
|
|
end if;
|
1077 |
|
|
end process;
|
1078 |
|
|
|
1079 |
|
|
Max_TLP_Size <= mxsz_mid & CONV_STD_LOGIC_VECTOR(0, C_MAXSIZE_FLD_BIT_BOT);
|
1080 |
|
|
|
1081 |
|
|
|
1082 |
|
|
end architecture Behavioral;
|