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weng_ziti |
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-- Company: ziti, Uni. HD
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-- Engineer: wgao
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--
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-- Design Name:
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-- Module Name: DMA_FSM - Behavioral
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-- Project Name:
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-- Target Devices:
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-- Tool versions:
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-- Description:
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-- The state machine controls the DMA routine, writes the channel
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-- buffer, as well as outputs DMA stata.
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--
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-- Dependencies:
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--
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-- Revision 1.00 - first release. 25.07.2007
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--
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-- Additional Comments:
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--
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----------------------------------------------------------------------------------
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library IEEE;
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use IEEE.STD_LOGIC_1164.ALL;
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use IEEE.STD_LOGIC_ARITH.ALL;
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use IEEE.STD_LOGIC_UNSIGNED.ALL;
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library work;
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use work.abb64Package.all;
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-- Uncomment the following library declaration if instantiating
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-- any Xilinx primitives in this code.
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--library UNISIM;
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--use UNISIM.VComponents.all;
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entity DMA_FSM is
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port (
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-- Fixed word for 1st header of TLP: MRd/MWr
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TLP_Has_Payload : IN std_logic;
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TLP_Hdr_is_4DW : IN std_logic;
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DMA_Addr_Inc : IN std_logic;
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DMA_BAR_Number : IN std_logic_vector(C_ENCODE_BAR_NUMBER-1 downto 0);
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-- FSM control signals
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DMA_Start : IN std_logic;
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DMA_Start2 : IN std_logic;
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DMA_Stop : IN std_logic;
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DMA_Stop2 : IN std_logic;
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No_More_Bodies : IN std_logic;
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ThereIs_Snout : IN std_logic;
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ThereIs_Body : IN std_logic;
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ThereIs_Tail : IN std_logic;
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ThereIs_Dex : IN std_logic;
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-- Parameters to be written into ChBuf
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DMA_PA_Loaded : IN std_logic_vector(C_DBUS_WIDTH-1 downto 0);
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DMA_PA_Var : IN std_logic_vector(C_DBUS_WIDTH-1 downto 0);
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DMA_HA_Var : IN std_logic_vector(C_DBUS_WIDTH-1 downto 0);
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DMA_BDA_fsm : IN std_logic_vector(C_DBUS_WIDTH-1 downto 0);
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BDA_is_64b_fsm : IN std_logic;
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DMA_Snout_Length : IN std_logic_vector(C_MAXSIZE_FLD_BIT_TOP downto 0);
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DMA_Body_Length : IN std_logic_vector(C_MAXSIZE_FLD_BIT_TOP downto 0);
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DMA_Tail_Length : IN std_logic_vector(C_TLP_FLD_WIDTH_OF_LENG+1 downto 0);
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-- Busy/Done conditions
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Done_Condition_1 : IN std_logic;
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Done_Condition_2 : IN std_logic;
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Done_Condition_3 : IN std_logic;
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Done_Condition_4 : IN std_logic;
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Done_Condition_5 : IN std_logic;
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Done_Condition_6 : IN std_logic;
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-- Channel buffer write
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us_MWr_Param_Vec : IN std_logic_vector(6-1 downto 0);
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ChBuf_aFull : IN std_logic;
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ChBuf_WrEn : OUT std_logic;
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ChBuf_WrDin : OUT std_logic_vector(C_CHANNEL_BUF_WIDTH-1 downto 0);
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-- FSM indicators
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State_Is_LoadParam : OUT std_logic;
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State_Is_Snout : OUT std_logic;
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State_Is_Body : OUT std_logic;
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State_Is_Tail : OUT std_logic;
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DMA_Cmd_Ack : OUT std_logic;
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-- To Tx Port
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ChBuf_ValidRd : IN std_logic;
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BDA_nAligned : OUT std_logic;
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DMA_TimeOut : OUT std_logic;
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DMA_Busy : OUT std_logic;
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DMA_Done : OUT std_logic;
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-- DMA_Done_Rise : OUT std_logic;
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-- Tags
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Pkt_Tag : IN std_logic_vector(C_TAG_WIDTH-1 downto 0);
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Dex_Tag : IN std_logic_vector(C_TAG_WIDTH-1 downto 0);
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-- Common ports
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dma_clk : IN std_logic;
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dma_reset : IN std_logic
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);
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end entity DMA_FSM;
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architecture Behavioral of DMA_FSM is
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-- DMA operation control FSM
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type DMAStates is (
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-- dmaST_Init: Initial state at reset.
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dmaST_Init
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-- dmaST_Load_Param: Load DMA parameters (PA, HA, BDA and Leng).
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, dmaST_Load_Param
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-- dmaST_Snout: 1st TLP might be non-integeral of MAX_SIZE.
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, dmaST_Snout
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-- dmaST_Stomp: after every ChBuf write, pause a clock before taking
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-- next write. This state checks the availability of
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-- the ChBuf (channel buffer) for write.
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, dmaST_Stomp
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-- dmaST_Body: TLP's in the middle, always integeral of MAX_SIZE.
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, dmaST_Body
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-- dmaST_Tail: the last TLP, similar with the 1st one, whose size
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-- should be specially calculated.
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, dmaST_Tail
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-- -- dmaST_Before_Dex: before writing the MRd TLP (for next descriptor)
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-- -- information for the next descriptor (if any),
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-- -- a pause is needed to wait for the ChBuf available.
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-- , dmaST_Before_Dex
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-- dmaST_NextDex: writing the descriptor MRd TLP information to
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-- the ChBuf.
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, dmaST_NextDex
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-- dmaST_Await_Dex: after MRd(descriptor) info is written in the ChBuf,
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-- the state machine waits for the descriptor's
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-- arrival.
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, dmaST_Await_Dex
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);
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signal DMA_NextState : DMAStates;
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signal DMA_State : DMAStates;
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-- Busy/Done state bits generation
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type FSM_BusyDone is (
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FSM_Idle
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, FSM_Busy1
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, FSM_Busy2
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, FSM_Busy3
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, FSM_Busy4
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, FSM_Busy5
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, FSM_Busy6
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, FSM_Done
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);
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signal BusyDone_NextState : FSM_BusyDone;
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signal BusyDone_State : FSM_BusyDone;
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-- Time-out state
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type FSM_Time_Out is (
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toutSt_Idle
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, toutSt_CountUp
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, toutSt_Pause
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);
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signal DMA_TimeOut_State : FSM_Time_Out;
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-- DMA Start command from MWr channel
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signal DMA_Start_r1 : std_logic;
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-- DMA Start command from CplD channel
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signal DMA_Start2_r1 : std_logic;
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-- Registered Dex indicator
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signal ThereIs_Dex_reg : std_logic;
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signal ThereIs_Snout_reg : std_logic;
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signal ThereIs_Body_reg : std_logic;
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signal ThereIs_Tail_reg : std_logic;
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-- DMA Stutus monitor
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signal BDA_nAligned_i : std_logic;
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signal DMA_Busy_i : std_logic;
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signal DMA_Done_i : std_logic;
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-- FSM state indicators
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signal State_Is_LoadParam_i : std_logic;
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signal State_Is_Snout_i : std_logic;
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signal State_Is_Body_i : std_logic;
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signal State_Is_Tail_i : std_logic;
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signal State_Is_AwaitDex_i : std_logic;
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-- Acknowledge for DMA_Start command
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signal DMA_Cmd_Ack_i : std_logic;
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-- channel FIFO Write control
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signal ChBuf_WrDin_i : std_logic_vector(C_CHANNEL_BUF_WIDTH-1 downto 0);
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signal ChBuf_WrEn_i : std_logic;
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signal ChBuf_aFull_i : std_logic;
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-- ---------------------------------------------------------------------------------
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-- Time-out calculation : invisible to the user, so moved out of the abbPackage
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-- ---------------------------------------------------------------------------------
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signal cnt_DMA_TO : std_logic_vector(C_TOUT_WIDTH-1 downto 0);
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signal Tout_Lo_Carry : std_logic;
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signal DMA_TimeOut_i : std_logic;
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-- Carry bit, only for better timing
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Constant CBIT_TOUT_CARRY : integer := C_TOUT_WIDTH/2;
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begin
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-- As DMA Statuses
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BDA_nAligned <= '0' ; -- BDA_nAligned_i ;
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DMA_Busy <= DMA_Busy_i ;
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DMA_Done <= DMA_Done_i ;
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-- DMA_Done_Rise <= DMA_Done_Rise_i;
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DMA_TimeOut <= DMA_TimeOut_i ;
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-- Abstract buffer write control
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ChBuf_WrEn <= ChBuf_WrEn_i;
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ChBuf_WrDin <= ChBuf_WrDin_i;
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ChBuf_aFull_i <= ChBuf_aFull;
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-- FSM State indicators
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State_Is_LoadParam <= State_Is_LoadParam_i;
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State_Is_Snout <= State_Is_Snout_i;
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State_Is_Body <= State_Is_Body_i;
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State_Is_Tail <= State_Is_Tail_i;
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DMA_Cmd_Ack <= DMA_Cmd_Ack_i;
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-- -----------------------------------------
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-- Syn_Delay: DMA_Start
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-- DMA_Start2
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--
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Syn_Delay_DMA_Starts:
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process ( dma_clk)
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begin
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if dma_clk'event and dma_clk = '1' then
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DMA_Start_r1 <= DMA_Start;
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DMA_Start2_r1 <= DMA_Start2;
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end if;
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end process;
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---- -----------------------------------------
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---- -----------------------------------------
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----
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-- States synchronous: DMA
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----
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Syn_DMA_States:
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process ( dma_clk, dma_reset)
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begin
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if dma_reset = '1' then
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DMA_State <= dmaST_Init;
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elsif dma_clk'event and dma_clk = '1' then
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DMA_State <= DMA_NextState;
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end if;
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end process;
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-- Next States: DMA
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Comb_DMA_NextState:
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process (
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DMA_State
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, DMA_Start_r1
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, DMA_Start2_r1
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, ChBuf_aFull_i
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, No_More_Bodies
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, ThereIs_Snout --_reg
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-- , ThereIs_Body
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, ThereIs_Tail_reg
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, ThereIs_Dex_reg
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)
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begin
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case DMA_State is
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when dmaST_Init =>
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if DMA_Start_r1 = '1' then
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DMA_NextState <= dmaST_Load_Param;
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else
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DMA_NextState <= dmaST_Init;
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end if;
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when dmaST_Load_Param =>
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if ChBuf_aFull_i = '1' then
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DMA_NextState <= dmaST_Load_Param;
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elsif ThereIs_Dex_reg = '1' then
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DMA_NextState <= dmaST_NextDex;
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elsif ThereIs_Snout = '1' then
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DMA_NextState <= dmaST_Snout;
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-- elsif ThereIs_Body = '1' then
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-- DMA_NextState <= dmaST_Stomp;
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else
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DMA_NextState <= dmaST_Stomp;
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end if;
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when dmaST_NextDex =>
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if ThereIs_Snout = '1' then
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DMA_NextState <= dmaST_Snout;
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elsif No_More_Bodies = '0' then
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DMA_NextState <= dmaST_Body;
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else
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DMA_NextState <= dmaST_Await_Dex;
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end if;
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when dmaST_Snout =>
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DMA_NextState <= dmaST_Stomp;
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when dmaST_Stomp =>
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if ChBuf_aFull_i = '1' then
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DMA_NextState <= dmaST_Stomp;
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elsif No_More_Bodies= '0' then
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DMA_NextState <= dmaST_Body;
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elsif ThereIs_Tail_reg= '1' then
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DMA_NextState <= dmaST_Tail;
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elsif ThereIs_Dex_reg= '1' then
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DMA_NextState <= dmaST_Await_Dex;
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else
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DMA_NextState <= dmaST_Init;
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end if;
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when dmaST_Body =>
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DMA_NextState <= dmaST_Stomp;
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when dmaST_Tail =>
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if ThereIs_Dex_reg = '1' then
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DMA_NextState <= dmaST_Await_Dex;
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else
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DMA_NextState <= dmaST_Init;
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end if;
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when dmaST_Await_Dex =>
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if DMA_Start2_r1 = '1' then
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DMA_NextState <= dmaST_Load_Param;
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else
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|
|
DMA_NextState <= dmaST_Await_Dex;
|
368 |
|
|
end if;
|
369 |
|
|
|
370 |
|
|
|
371 |
|
|
when Others =>
|
372 |
|
|
DMA_NextState <= dmaST_Init;
|
373 |
|
|
|
374 |
|
|
|
375 |
|
|
end case; -- DMA_State
|
376 |
|
|
|
377 |
|
|
end process;
|
378 |
|
|
|
379 |
|
|
|
380 |
|
|
|
381 |
|
|
-- ----------------------------------------------------
|
382 |
|
|
-- States synchronous: DMA_Cmd_Ack
|
383 |
|
|
-- equivalent to State_Is_LoadParam
|
384 |
|
|
--
|
385 |
|
|
Syn_DMA_Cmd_Ack:
|
386 |
|
|
process ( dma_clk, dma_reset)
|
387 |
|
|
begin
|
388 |
|
|
if dma_reset = '1' then
|
389 |
|
|
DMA_Cmd_Ack_i <= '0';
|
390 |
|
|
elsif dma_clk'event and dma_clk = '1' then
|
391 |
|
|
|
392 |
|
|
if DMA_NextState = dmaST_Load_Param then
|
393 |
|
|
DMA_Cmd_Ack_i <= '1';
|
394 |
|
|
else
|
395 |
|
|
DMA_Cmd_Ack_i <= '0';
|
396 |
|
|
end if;
|
397 |
|
|
end if;
|
398 |
|
|
|
399 |
|
|
end process;
|
400 |
|
|
|
401 |
|
|
|
402 |
|
|
-- ----------------------------------------------------
|
403 |
|
|
-- States synchronous: ThereIs_Dex_reg
|
404 |
|
|
--
|
405 |
|
|
Syn_ThereIs_Dex_reg:
|
406 |
|
|
process ( dma_clk, dma_reset)
|
407 |
|
|
begin
|
408 |
|
|
if dma_reset = '1' then
|
409 |
|
|
ThereIs_Dex_reg <= '0';
|
410 |
|
|
ThereIs_Snout_reg <= '0';
|
411 |
|
|
ThereIs_Body_reg <= '0';
|
412 |
|
|
ThereIs_Tail_reg <= '0';
|
413 |
|
|
|
414 |
|
|
elsif dma_clk'event and dma_clk = '1' then
|
415 |
|
|
|
416 |
|
|
if DMA_Start = '1'
|
417 |
|
|
or State_Is_LoadParam_i = '1'
|
418 |
|
|
or State_Is_AwaitDex_i ='1'
|
419 |
|
|
then
|
420 |
|
|
ThereIs_Dex_reg <= ThereIs_Dex;
|
421 |
|
|
ThereIs_Snout_reg <= ThereIs_Snout;
|
422 |
|
|
ThereIs_Body_reg <= ThereIs_Body;
|
423 |
|
|
ThereIs_Tail_reg <= ThereIs_Tail;
|
424 |
|
|
else
|
425 |
|
|
ThereIs_Dex_reg <= ThereIs_Dex_reg;
|
426 |
|
|
ThereIs_Snout_reg <= ThereIs_Snout_reg;
|
427 |
|
|
ThereIs_Body_reg <= ThereIs_Body_reg;
|
428 |
|
|
ThereIs_Tail_reg <= ThereIs_Tail_reg;
|
429 |
|
|
end if;
|
430 |
|
|
end if;
|
431 |
|
|
|
432 |
|
|
end process;
|
433 |
|
|
|
434 |
|
|
|
435 |
|
|
|
436 |
|
|
-- -------------------------------------------------------------
|
437 |
|
|
-- Synchronous reg:
|
438 |
|
|
-- State_Is_LoadParam
|
439 |
|
|
-- State_Is_Snout
|
440 |
|
|
-- State_Is_Body
|
441 |
|
|
-- State_Is_Tail
|
442 |
|
|
-- State_Is_AwaitDex
|
443 |
|
|
--
|
444 |
|
|
FSM_State_Is_i:
|
445 |
|
|
process ( dma_clk, dma_reset)
|
446 |
|
|
begin
|
447 |
|
|
if dma_reset = '1' then
|
448 |
|
|
State_Is_LoadParam_i <= '0';
|
449 |
|
|
State_Is_Snout_i <= '0';
|
450 |
|
|
State_Is_Body_i <= '0';
|
451 |
|
|
State_Is_Tail_i <= '0';
|
452 |
|
|
State_Is_AwaitDex_i <= '0';
|
453 |
|
|
|
454 |
|
|
elsif dma_clk'event and dma_clk = '1' then
|
455 |
|
|
|
456 |
|
|
if DMA_NextState= dmaST_Load_Param then
|
457 |
|
|
State_Is_LoadParam_i <= '1';
|
458 |
|
|
else
|
459 |
|
|
State_Is_LoadParam_i <= '0';
|
460 |
|
|
end if;
|
461 |
|
|
|
462 |
|
|
if DMA_NextState= dmaST_Snout then
|
463 |
|
|
State_Is_Snout_i <= '1';
|
464 |
|
|
else
|
465 |
|
|
State_Is_Snout_i <= '0';
|
466 |
|
|
end if;
|
467 |
|
|
|
468 |
|
|
if DMA_NextState= dmaST_Body then
|
469 |
|
|
State_Is_Body_i <= '1';
|
470 |
|
|
else
|
471 |
|
|
State_Is_Body_i <= '0';
|
472 |
|
|
end if;
|
473 |
|
|
|
474 |
|
|
if DMA_NextState= dmaST_Tail then
|
475 |
|
|
State_Is_Tail_i <= '1';
|
476 |
|
|
else
|
477 |
|
|
State_Is_Tail_i <= '0';
|
478 |
|
|
end if;
|
479 |
|
|
|
480 |
|
|
if DMA_NextState= dmaST_Await_Dex then
|
481 |
|
|
State_Is_AwaitDex_i <= '1';
|
482 |
|
|
else
|
483 |
|
|
State_Is_AwaitDex_i <= '0';
|
484 |
|
|
end if;
|
485 |
|
|
|
486 |
|
|
end if;
|
487 |
|
|
end process;
|
488 |
|
|
|
489 |
|
|
|
490 |
|
|
|
491 |
|
|
-------------------------------------------------------------------
|
492 |
|
|
-- Synchronous Output: DMA_Abstract_Buffer_Write
|
493 |
|
|
--
|
494 |
|
|
-- DMA Channel (downstream and upstream) Buffers (128-bit) definition:
|
495 |
|
|
-- Note: Type not shows in this buffer
|
496 |
|
|
--
|
497 |
|
|
-- 127 ~ xxx : Peripheral address
|
498 |
|
|
-- xxy ~ 96 : reserved
|
499 |
|
|
-- 95 : Address increments
|
500 |
|
|
-- 94 : Valid
|
501 |
|
|
-- 93 ~ 30 : Host Address
|
502 |
|
|
-- 29 ~ 27 : BAR number
|
503 |
|
|
-- 26 ~ 19 : Tag
|
504 |
|
|
--
|
505 |
|
|
-- 18 ~ 17 : Format
|
506 |
|
|
-- 16 ~ 14 : TC
|
507 |
|
|
-- 13 : TD
|
508 |
|
|
-- 12 : EP
|
509 |
|
|
-- 11 ~ 10 : Attribute
|
510 |
|
|
-- 9 ~ 0 : Length
|
511 |
|
|
--
|
512 |
|
|
FSM_DMA_Abstract_Buffer_Write:
|
513 |
|
|
process ( dma_clk, dma_reset)
|
514 |
|
|
begin
|
515 |
|
|
if dma_reset = '1' then
|
516 |
|
|
ChBuf_WrEn_i <= '0';
|
517 |
|
|
ChBuf_WrDin_i <= (OTHERS =>'0');
|
518 |
|
|
|
519 |
|
|
elsif dma_clk'event and dma_clk = '1' then
|
520 |
|
|
|
521 |
|
|
case DMA_State is
|
522 |
|
|
|
523 |
|
|
when dmaST_NextDex =>
|
524 |
|
|
ChBuf_WrEn_i <= '1';
|
525 |
|
|
|
526 |
|
|
ChBuf_WrDin_i <= (OTHERS=>'0'); -- must be the first argument
|
527 |
|
|
ChBuf_WrDin_i(C_CHBUF_HA_BIT_TOP downto C_CHBUF_HA_BIT_BOT) <= DMA_BDA_fsm;
|
528 |
|
|
ChBuf_WrDin_i(C_CHBUF_MA_BIT_TOP downto C_CHBUF_MA_BIT_BOT) <= C_ALL_ZEROS(C_CHBUF_MA_BIT_TOP downto C_CHBUF_MA_BIT_BOT); -- any value
|
529 |
|
|
ChBuf_WrDin_i(C_CHBUF_TAG_BIT_TOP downto C_CHBUF_TAG_BIT_BOT) <= Dex_Tag;
|
530 |
|
|
ChBuf_WrDin_i(C_CHBUF_DMA_BAR_BIT_TOP downto C_CHBUF_DMA_BAR_BIT_BOT) <= DMA_BAR_Number;
|
531 |
|
|
|
532 |
|
|
ChBuf_WrDin_i(C_CHBUF_FMT_BIT_TOP) <= C_TLP_HAS_NO_DATA; --C_MRD_HEAD0_WORD(C_TLP_FMT_BIT_TOP);
|
533 |
|
|
ChBuf_WrDin_i(C_CHBUF_FMT_BIT_BOT) <= BDA_is_64b_fsm;
|
534 |
|
|
ChBuf_WrDin_i(C_CHBUF_LENG_BIT_TOP downto C_CHBUF_LENG_BIT_BOT) <= C_NEXT_BD_LENGTH(C_TLP_FLD_WIDTH_OF_LENG+1 downto 2);
|
535 |
|
|
|
536 |
|
|
ChBuf_WrDin_i(C_CHBUF_QVALID_BIT) <= '1';
|
537 |
|
|
ChBuf_WrDin_i(C_CHBUF_AINC_BIT) <= DMA_Addr_Inc; -- any value
|
538 |
|
|
|
539 |
|
|
ChBuf_WrDin_i(C_CHBUF_ATTR_BIT_TOP downto C_CHBUF_ATTR_BIT_BOT) <= C_RELAXED_ORDERING & C_NO_SNOOP;
|
540 |
|
|
|
541 |
|
|
when dmaST_Snout =>
|
542 |
|
|
ChBuf_WrEn_i <= '1';
|
543 |
|
|
|
544 |
|
|
ChBuf_WrDin_i <= (OTHERS=>'0'); -- must be the first argument
|
545 |
|
|
ChBuf_WrDin_i(C_CHBUF_HA_BIT_TOP downto C_CHBUF_HA_BIT_BOT) <= DMA_HA_Var;
|
546 |
|
|
if DMA_BAR_Number=CONV_STD_LOGIC_VECTOR(CINT_FIFO_SPACE_BAR, C_ENCODE_BAR_NUMBER) then
|
547 |
|
|
ChBuf_WrDin_i(C_CHBUF_PA_BIT_TOP downto C_CHBUF_PA_BIT_BOT) <= DMA_PA_Loaded(C_EP_AWIDTH-1 downto 0);
|
548 |
|
|
elsif DMA_BAR_Number=CONV_STD_LOGIC_VECTOR(CINT_BRAM_SPACE_BAR, C_ENCODE_BAR_NUMBER) then
|
549 |
|
|
ChBuf_WrDin_i(C_CHBUF_MA_BIT_TOP downto C_CHBUF_MA_BIT_BOT) <= DMA_PA_Loaded(C_PRAM_AWIDTH-1+2 downto 0);
|
550 |
|
|
elsif DMA_BAR_Number=CONV_STD_LOGIC_VECTOR(CINT_DDR_SPACE_BAR, C_ENCODE_BAR_NUMBER) then
|
551 |
|
|
ChBuf_WrDin_i(C_CHBUF_DDA_BIT_TOP downto C_CHBUF_DDA_BIT_BOT) <= DMA_PA_Loaded(C_DDR_IAWIDTH-1 downto 0);
|
552 |
|
|
else
|
553 |
|
|
ChBuf_WrDin_i(C_CHBUF_MA_BIT_TOP downto C_CHBUF_MA_BIT_BOT) <= C_ALL_ZEROS(C_CHBUF_MA_BIT_TOP downto C_CHBUF_MA_BIT_BOT);
|
554 |
|
|
end if;
|
555 |
|
|
|
556 |
|
|
ChBuf_WrDin_i(C_CHBUF_TAG_BIT_TOP downto C_CHBUF_TAG_BIT_BOT) <= Pkt_Tag;
|
557 |
|
|
ChBuf_WrDin_i(C_CHBUF_DMA_BAR_BIT_TOP downto C_CHBUF_DMA_BAR_BIT_BOT) <= DMA_BAR_Number;
|
558 |
|
|
|
559 |
|
|
ChBuf_WrDin_i(C_CHBUF_FMT_BIT_TOP) <= TLP_Has_Payload;
|
560 |
|
|
ChBuf_WrDin_i(C_CHBUF_FMT_BIT_BOT) <= TLP_Hdr_is_4DW;
|
561 |
|
|
|
562 |
|
|
if DMA_BAR_Number=CONV_STD_LOGIC_VECTOR(CINT_FIFO_SPACE_BAR, C_ENCODE_BAR_NUMBER) then
|
563 |
|
|
ChBuf_WrDin_i(C_CHBUF_LENG_BIT_TOP downto C_CHBUF_LENG_BIT_BOT) <= DMA_Snout_Length(C_TLP_FLD_WIDTH_OF_LENG+1 downto 3) & '0';
|
564 |
|
|
else
|
565 |
|
|
ChBuf_WrDin_i(C_CHBUF_LENG_BIT_TOP downto C_CHBUF_LENG_BIT_BOT) <= DMA_Snout_Length(C_TLP_FLD_WIDTH_OF_LENG+1 downto 2);
|
566 |
|
|
end if;
|
567 |
|
|
|
568 |
|
|
ChBuf_WrDin_i(C_CHBUF_QVALID_BIT) <= '1';
|
569 |
|
|
ChBuf_WrDin_i(C_CHBUF_AINC_BIT) <= DMA_Addr_Inc;
|
570 |
|
|
|
571 |
|
|
ChBuf_WrDin_i(C_CHBUF_TC_BIT_TOP downto C_CHBUF_TC_BIT_BOT) <= us_MWr_Param_Vec(2 downto 0);
|
572 |
|
|
ChBuf_WrDin_i(C_CHBUF_ATTR_BIT_TOP downto C_CHBUF_ATTR_BIT_BOT) <= us_MWr_Param_Vec(5 downto 4); -- C_RELAXED_ORDERING & C_NO_SNOOP;
|
573 |
|
|
|
574 |
|
|
when dmaST_Body =>
|
575 |
|
|
ChBuf_WrEn_i <= '1';
|
576 |
|
|
|
577 |
|
|
ChBuf_WrDin_i <= (OTHERS=>'0'); -- must be the first argument
|
578 |
|
|
ChBuf_WrDin_i(C_CHBUF_HA_BIT_TOP downto C_CHBUF_HA_BIT_BOT) <= DMA_HA_Var;
|
579 |
|
|
if DMA_BAR_Number=CONV_STD_LOGIC_VECTOR(CINT_FIFO_SPACE_BAR, C_ENCODE_BAR_NUMBER) then
|
580 |
|
|
ChBuf_WrDin_i(C_CHBUF_PA_BIT_TOP downto C_CHBUF_PA_BIT_BOT) <= DMA_PA_Var(C_EP_AWIDTH-1 downto 0);
|
581 |
|
|
elsif DMA_BAR_Number=CONV_STD_LOGIC_VECTOR(CINT_BRAM_SPACE_BAR, C_ENCODE_BAR_NUMBER) then
|
582 |
|
|
ChBuf_WrDin_i(C_CHBUF_MA_BIT_TOP downto C_CHBUF_MA_BIT_BOT) <= DMA_PA_Var(C_PRAM_AWIDTH-1+2 downto 0);
|
583 |
|
|
elsif DMA_BAR_Number=CONV_STD_LOGIC_VECTOR(CINT_DDR_SPACE_BAR, C_ENCODE_BAR_NUMBER) then
|
584 |
|
|
ChBuf_WrDin_i(C_CHBUF_DDA_BIT_TOP downto C_CHBUF_DDA_BIT_BOT) <= DMA_PA_Var(C_DDR_IAWIDTH-1 downto 0);
|
585 |
|
|
else
|
586 |
|
|
ChBuf_WrDin_i(C_CHBUF_MA_BIT_TOP downto C_CHBUF_MA_BIT_BOT) <= C_ALL_ZEROS(C_CHBUF_MA_BIT_TOP downto C_CHBUF_MA_BIT_BOT);
|
587 |
|
|
end if;
|
588 |
|
|
|
589 |
|
|
ChBuf_WrDin_i(C_CHBUF_TAG_BIT_TOP downto C_CHBUF_TAG_BIT_BOT) <= Pkt_Tag;
|
590 |
|
|
ChBuf_WrDin_i(C_CHBUF_DMA_BAR_BIT_TOP downto C_CHBUF_DMA_BAR_BIT_BOT) <= DMA_BAR_Number;
|
591 |
|
|
|
592 |
|
|
ChBuf_WrDin_i(C_CHBUF_FMT_BIT_TOP) <= TLP_Has_Payload;
|
593 |
|
|
ChBuf_WrDin_i(C_CHBUF_FMT_BIT_BOT) <= TLP_Hdr_is_4DW;
|
594 |
|
|
|
595 |
|
|
if DMA_BAR_Number=CONV_STD_LOGIC_VECTOR(CINT_FIFO_SPACE_BAR, C_ENCODE_BAR_NUMBER) then
|
596 |
|
|
ChBuf_WrDin_i(C_CHBUF_LENG_BIT_TOP downto C_CHBUF_LENG_BIT_BOT) <= DMA_Body_Length(C_TLP_FLD_WIDTH_OF_LENG+1 downto 3) & '0';
|
597 |
|
|
else
|
598 |
|
|
ChBuf_WrDin_i(C_CHBUF_LENG_BIT_TOP downto C_CHBUF_LENG_BIT_BOT) <= DMA_Body_Length(C_TLP_FLD_WIDTH_OF_LENG+1 downto 2);
|
599 |
|
|
end if;
|
600 |
|
|
|
601 |
|
|
ChBuf_WrDin_i(C_CHBUF_QVALID_BIT) <= '1';
|
602 |
|
|
ChBuf_WrDin_i(C_CHBUF_AINC_BIT) <= DMA_Addr_Inc;
|
603 |
|
|
|
604 |
|
|
ChBuf_WrDin_i(C_CHBUF_TC_BIT_TOP downto C_CHBUF_TC_BIT_BOT) <= us_MWr_Param_Vec(2 downto 0);
|
605 |
|
|
ChBuf_WrDin_i(C_CHBUF_ATTR_BIT_TOP downto C_CHBUF_ATTR_BIT_BOT) <= us_MWr_Param_Vec(5 downto 4); -- C_RELAXED_ORDERING & C_NO_SNOOP;
|
606 |
|
|
|
607 |
|
|
|
608 |
|
|
when dmaST_Tail =>
|
609 |
|
|
ChBuf_WrEn_i <= '1';
|
610 |
|
|
|
611 |
|
|
ChBuf_WrDin_i <= (OTHERS=>'0'); -- must be the first argument
|
612 |
|
|
ChBuf_WrDin_i(C_CHBUF_HA_BIT_TOP downto C_CHBUF_HA_BIT_BOT) <= DMA_HA_Var;
|
613 |
|
|
if DMA_BAR_Number=CONV_STD_LOGIC_VECTOR(CINT_FIFO_SPACE_BAR, C_ENCODE_BAR_NUMBER) then
|
614 |
|
|
ChBuf_WrDin_i(C_CHBUF_PA_BIT_TOP downto C_CHBUF_PA_BIT_BOT) <= DMA_PA_Var(C_EP_AWIDTH-1 downto 0);
|
615 |
|
|
elsif DMA_BAR_Number=CONV_STD_LOGIC_VECTOR(CINT_BRAM_SPACE_BAR, C_ENCODE_BAR_NUMBER) then
|
616 |
|
|
ChBuf_WrDin_i(C_CHBUF_MA_BIT_TOP downto C_CHBUF_MA_BIT_BOT) <= DMA_PA_Var(C_PRAM_AWIDTH-1+2 downto 0);
|
617 |
|
|
elsif DMA_BAR_Number=CONV_STD_LOGIC_VECTOR(CINT_DDR_SPACE_BAR, C_ENCODE_BAR_NUMBER) then
|
618 |
|
|
ChBuf_WrDin_i(C_CHBUF_DDA_BIT_TOP downto C_CHBUF_DDA_BIT_BOT) <= DMA_PA_Var(C_DDR_IAWIDTH-1 downto 0);
|
619 |
|
|
else
|
620 |
|
|
ChBuf_WrDin_i(C_CHBUF_MA_BIT_TOP downto C_CHBUF_MA_BIT_BOT) <= C_ALL_ZEROS(C_CHBUF_MA_BIT_TOP downto C_CHBUF_MA_BIT_BOT);
|
621 |
|
|
end if;
|
622 |
|
|
|
623 |
|
|
ChBuf_WrDin_i(C_CHBUF_TAG_BIT_TOP downto C_CHBUF_TAG_BIT_BOT) <= Pkt_Tag;
|
624 |
|
|
ChBuf_WrDin_i(C_CHBUF_DMA_BAR_BIT_TOP downto C_CHBUF_DMA_BAR_BIT_BOT) <= DMA_BAR_Number;
|
625 |
|
|
|
626 |
|
|
ChBuf_WrDin_i(C_CHBUF_FMT_BIT_TOP) <= TLP_Has_Payload;
|
627 |
|
|
ChBuf_WrDin_i(C_CHBUF_FMT_BIT_BOT) <= TLP_Hdr_is_4DW;
|
628 |
|
|
|
629 |
|
|
if DMA_BAR_Number=CONV_STD_LOGIC_VECTOR(CINT_FIFO_SPACE_BAR, C_ENCODE_BAR_NUMBER) then
|
630 |
|
|
ChBuf_WrDin_i(C_CHBUF_LENG_BIT_TOP downto C_CHBUF_LENG_BIT_BOT) <= DMA_Tail_Length(C_TLP_FLD_WIDTH_OF_LENG+1 downto 3) & '0';
|
631 |
|
|
else
|
632 |
|
|
ChBuf_WrDin_i(C_CHBUF_LENG_BIT_TOP downto C_CHBUF_LENG_BIT_BOT) <= DMA_Tail_Length(C_TLP_FLD_WIDTH_OF_LENG+1 downto 2);
|
633 |
|
|
end if;
|
634 |
|
|
|
635 |
|
|
ChBuf_WrDin_i(C_CHBUF_QVALID_BIT) <= '1';
|
636 |
|
|
ChBuf_WrDin_i(C_CHBUF_AINC_BIT) <= DMA_Addr_Inc;
|
637 |
|
|
|
638 |
|
|
ChBuf_WrDin_i(C_CHBUF_TC_BIT_TOP downto C_CHBUF_TC_BIT_BOT) <= us_MWr_Param_Vec(2 downto 0);
|
639 |
|
|
ChBuf_WrDin_i(C_CHBUF_ATTR_BIT_TOP downto C_CHBUF_ATTR_BIT_BOT) <= us_MWr_Param_Vec(5 downto 4); -- C_RELAXED_ORDERING & C_NO_SNOOP;
|
640 |
|
|
|
641 |
|
|
|
642 |
|
|
when OTHERS =>
|
643 |
|
|
ChBuf_WrEn_i <= '0';
|
644 |
|
|
ChBuf_WrDin_i <= ChBuf_WrDin_i;
|
645 |
|
|
|
646 |
|
|
end case;
|
647 |
|
|
|
648 |
|
|
end if;
|
649 |
|
|
end process;
|
650 |
|
|
|
651 |
|
|
|
652 |
|
|
|
653 |
|
|
-- ----------------------------------------------
|
654 |
|
|
-- Synchronous Latch: BDA_nAligned_i
|
655 |
|
|
-- : Capture design defect
|
656 |
|
|
--
|
657 |
|
|
Latch_BDA_nAligned:
|
658 |
|
|
process ( dma_clk, dma_reset)
|
659 |
|
|
begin
|
660 |
|
|
if dma_reset = '1' then
|
661 |
|
|
BDA_nAligned_i <= '0';
|
662 |
|
|
|
663 |
|
|
elsif dma_clk'event and dma_clk = '1' then
|
664 |
|
|
-- If the lowest 2 bits are not zero, error bit set accordingly,
|
665 |
|
|
-- because the logic can not deal with this situation.
|
666 |
|
|
-- can be removed.
|
667 |
|
|
|
668 |
|
|
if DMA_BDA_fsm(1) ='1' or DMA_BDA_fsm(0) ='1' then
|
669 |
|
|
BDA_nAligned_i <= '1';
|
670 |
|
|
else
|
671 |
|
|
BDA_nAligned_i <= BDA_nAligned_i;
|
672 |
|
|
end if;
|
673 |
|
|
|
674 |
|
|
end if;
|
675 |
|
|
end process;
|
676 |
|
|
|
677 |
|
|
|
678 |
|
|
-- States synchronous: BusyDone_States
|
679 |
|
|
Syn_BusyDone_States:
|
680 |
|
|
process ( dma_clk, dma_reset)
|
681 |
|
|
begin
|
682 |
|
|
if dma_reset = '1' then
|
683 |
|
|
BusyDone_State <= FSM_Idle;
|
684 |
|
|
elsif dma_clk'event and dma_clk = '1' then
|
685 |
|
|
BusyDone_State <= BusyDone_NextState;
|
686 |
|
|
end if;
|
687 |
|
|
|
688 |
|
|
end process;
|
689 |
|
|
|
690 |
|
|
|
691 |
|
|
-- Next States: BusyDone_State
|
692 |
|
|
Comb_BusyDone_State:
|
693 |
|
|
process (
|
694 |
|
|
BusyDone_State
|
695 |
|
|
, DMA_State
|
696 |
|
|
-- , Done_Condition_1
|
697 |
|
|
, Done_Condition_2
|
698 |
|
|
, Done_Condition_3
|
699 |
|
|
, Done_Condition_4
|
700 |
|
|
, Done_Condition_5
|
701 |
|
|
, Done_Condition_6
|
702 |
|
|
)
|
703 |
|
|
begin
|
704 |
|
|
case BusyDone_State is
|
705 |
|
|
|
706 |
|
|
when FSM_Idle =>
|
707 |
|
|
if DMA_State = dmaST_Load_Param then
|
708 |
|
|
BusyDone_NextState <= FSM_Busy1;
|
709 |
|
|
else
|
710 |
|
|
BusyDone_NextState <= FSM_Idle;
|
711 |
|
|
end if;
|
712 |
|
|
|
713 |
|
|
when FSM_Busy1 =>
|
714 |
|
|
if DMA_State = dmaST_Init --- Done_Condition_1='1'
|
715 |
|
|
then
|
716 |
|
|
BusyDone_NextState <= FSM_Busy2;
|
717 |
|
|
else
|
718 |
|
|
BusyDone_NextState <= FSM_Busy1;
|
719 |
|
|
end if;
|
720 |
|
|
|
721 |
|
|
when FSM_Busy2 =>
|
722 |
|
|
if Done_Condition_2='1'
|
723 |
|
|
then
|
724 |
|
|
BusyDone_NextState <= FSM_Busy3;
|
725 |
|
|
else
|
726 |
|
|
BusyDone_NextState <= FSM_Busy2;
|
727 |
|
|
end if;
|
728 |
|
|
|
729 |
|
|
when FSM_Busy3 =>
|
730 |
|
|
if Done_Condition_3='1'
|
731 |
|
|
then
|
732 |
|
|
BusyDone_NextState <= FSM_Busy4;
|
733 |
|
|
else
|
734 |
|
|
BusyDone_NextState <= FSM_Busy3;
|
735 |
|
|
end if;
|
736 |
|
|
|
737 |
|
|
when FSM_Busy4 =>
|
738 |
|
|
if Done_Condition_4='1'
|
739 |
|
|
then
|
740 |
|
|
BusyDone_NextState <= FSM_Busy5;
|
741 |
|
|
else
|
742 |
|
|
BusyDone_NextState <= FSM_Busy4;
|
743 |
|
|
end if;
|
744 |
|
|
|
745 |
|
|
when FSM_Busy5 =>
|
746 |
|
|
if Done_Condition_5='1'
|
747 |
|
|
then
|
748 |
|
|
BusyDone_NextState <= FSM_Busy6;
|
749 |
|
|
else
|
750 |
|
|
BusyDone_NextState <= FSM_Busy5;
|
751 |
|
|
end if;
|
752 |
|
|
|
753 |
|
|
when FSM_Busy6 =>
|
754 |
|
|
if Done_Condition_6='1'
|
755 |
|
|
then
|
756 |
|
|
BusyDone_NextState <= FSM_Done;
|
757 |
|
|
else
|
758 |
|
|
BusyDone_NextState <= FSM_Busy6;
|
759 |
|
|
end if;
|
760 |
|
|
|
761 |
|
|
when FSM_Done =>
|
762 |
|
|
if DMA_State = dmaST_Init then
|
763 |
|
|
BusyDone_NextState <= FSM_Idle;
|
764 |
|
|
else
|
765 |
|
|
BusyDone_NextState <= FSM_Done;
|
766 |
|
|
end if;
|
767 |
|
|
|
768 |
|
|
when Others =>
|
769 |
|
|
BusyDone_NextState <= FSM_Idle;
|
770 |
|
|
|
771 |
|
|
end case; -- BusyDone_State
|
772 |
|
|
|
773 |
|
|
end process;
|
774 |
|
|
|
775 |
|
|
|
776 |
|
|
|
777 |
|
|
-- Synchronous Output: DMA_Busy_i
|
778 |
|
|
FSM_Output_DMA_Busy:
|
779 |
|
|
process ( dma_clk, dma_reset)
|
780 |
|
|
begin
|
781 |
|
|
if dma_reset = '1' then
|
782 |
|
|
DMA_Busy_i <= '0';
|
783 |
|
|
elsif dma_clk'event and dma_clk = '1' then
|
784 |
|
|
|
785 |
|
|
case BusyDone_State is
|
786 |
|
|
|
787 |
|
|
when FSM_Idle =>
|
788 |
|
|
DMA_Busy_i <= '0';
|
789 |
|
|
|
790 |
|
|
when FSM_Busy1 =>
|
791 |
|
|
DMA_Busy_i <= '1';
|
792 |
|
|
|
793 |
|
|
when FSM_Busy2 =>
|
794 |
|
|
DMA_Busy_i <= '1';
|
795 |
|
|
|
796 |
|
|
when FSM_Busy3 =>
|
797 |
|
|
DMA_Busy_i <= '1';
|
798 |
|
|
|
799 |
|
|
when FSM_Busy4 =>
|
800 |
|
|
DMA_Busy_i <= '1';
|
801 |
|
|
|
802 |
|
|
when FSM_Busy5 =>
|
803 |
|
|
DMA_Busy_i <= '1';
|
804 |
|
|
|
805 |
|
|
when FSM_Busy6 =>
|
806 |
|
|
DMA_Busy_i <= '1';
|
807 |
|
|
|
808 |
|
|
when FSM_Done =>
|
809 |
|
|
DMA_Busy_i <= '0';
|
810 |
|
|
|
811 |
|
|
when Others =>
|
812 |
|
|
DMA_Busy_i <= '0';
|
813 |
|
|
|
814 |
|
|
end case; -- BusyDone_State
|
815 |
|
|
|
816 |
|
|
end if;
|
817 |
|
|
end process;
|
818 |
|
|
|
819 |
|
|
|
820 |
|
|
-- Synchronous Output: DMA_Done_i
|
821 |
|
|
FSM_Output_DMA_Done:
|
822 |
|
|
process ( dma_clk, dma_reset)
|
823 |
|
|
begin
|
824 |
|
|
if dma_reset = '1' then
|
825 |
|
|
DMA_Done_i <= '0';
|
826 |
|
|
elsif dma_clk'event and dma_clk = '1' then
|
827 |
|
|
|
828 |
|
|
case BusyDone_State is
|
829 |
|
|
|
830 |
|
|
-- when FSM_Busy1 =>
|
831 |
|
|
-- DMA_Done_i <= '0';
|
832 |
|
|
--
|
833 |
|
|
-- when FSM_Busy2 =>
|
834 |
|
|
-- DMA_Done_i <= '0';
|
835 |
|
|
--
|
836 |
|
|
-- when FSM_Busy3 =>
|
837 |
|
|
-- DMA_Done_i <= '0';
|
838 |
|
|
--
|
839 |
|
|
when FSM_Done =>
|
840 |
|
|
DMA_Done_i <= '1';
|
841 |
|
|
|
842 |
|
|
when Others =>
|
843 |
|
|
DMA_Done_i <= DMA_Done_i;
|
844 |
|
|
|
845 |
|
|
end case; -- BusyDone_State
|
846 |
|
|
|
847 |
|
|
end if;
|
848 |
|
|
end process;
|
849 |
|
|
|
850 |
|
|
|
851 |
|
|
|
852 |
|
|
-- ----------------------------------------------
|
853 |
|
|
-- Time out counter
|
854 |
|
|
-- Synchronous Output: Counter_DMA_TimeOut_i
|
855 |
|
|
FSM_Counter_DMA_TimeOut_i:
|
856 |
|
|
process ( dma_clk, dma_reset)
|
857 |
|
|
begin
|
858 |
|
|
if dma_reset = '1' then
|
859 |
|
|
cnt_DMA_TO <= (Others=>'0');
|
860 |
|
|
Tout_Lo_Carry <= '0';
|
861 |
|
|
DMA_TimeOut_State <= toutSt_Idle;
|
862 |
|
|
|
863 |
|
|
elsif dma_clk'event and dma_clk = '1' then
|
864 |
|
|
|
865 |
|
|
case DMA_TimeOut_State is
|
866 |
|
|
|
867 |
|
|
when toutSt_Idle =>
|
868 |
|
|
cnt_DMA_TO <= (Others=>'0');
|
869 |
|
|
Tout_Lo_Carry <= '0';
|
870 |
|
|
if DMA_Start='1' then
|
871 |
|
|
DMA_TimeOut_State <= toutSt_CountUp;
|
872 |
|
|
else
|
873 |
|
|
DMA_TimeOut_State <= toutSt_Idle;
|
874 |
|
|
end if;
|
875 |
|
|
|
876 |
|
|
when toutSt_CountUp =>
|
877 |
|
|
if DMA_Done_i='1' or DMA_Start='1' then
|
878 |
|
|
cnt_DMA_TO <= (Others=>'0');
|
879 |
|
|
Tout_Lo_Carry <= '0';
|
880 |
|
|
DMA_TimeOut_State <= toutSt_Idle;
|
881 |
|
|
elsif DMA_Stop='1' then
|
882 |
|
|
cnt_DMA_TO <= cnt_DMA_TO;
|
883 |
|
|
Tout_Lo_Carry <= Tout_Lo_Carry;
|
884 |
|
|
DMA_TimeOut_State <= toutSt_Pause;
|
885 |
|
|
elsif ChBuf_ValidRd='1' then
|
886 |
|
|
cnt_DMA_TO <= (Others=>'0');
|
887 |
|
|
Tout_Lo_Carry <= '0';
|
888 |
|
|
DMA_TimeOut_State <= toutSt_CountUp;
|
889 |
|
|
else
|
890 |
|
|
cnt_DMA_TO(CBIT_TOUT_CARRY-1 downto 0) <= cnt_DMA_TO(CBIT_TOUT_CARRY-1 downto 0) + '1';
|
891 |
|
|
if cnt_DMA_TO(CBIT_TOUT_CARRY-1 downto 0)=C_ALL_ONES(CBIT_TOUT_CARRY-1 downto 0) then
|
892 |
|
|
Tout_Lo_Carry <= '1';
|
893 |
|
|
else
|
894 |
|
|
Tout_Lo_Carry <= '0';
|
895 |
|
|
end if;
|
896 |
|
|
if Tout_Lo_Carry='1' then
|
897 |
|
|
cnt_DMA_TO(C_TOUT_WIDTH-1 downto CBIT_TOUT_CARRY) <= cnt_DMA_TO(C_TOUT_WIDTH-1 downto CBIT_TOUT_CARRY) + '1';
|
898 |
|
|
else
|
899 |
|
|
cnt_DMA_TO(C_TOUT_WIDTH-1 downto CBIT_TOUT_CARRY) <= cnt_DMA_TO(C_TOUT_WIDTH-1 downto CBIT_TOUT_CARRY);
|
900 |
|
|
end if;
|
901 |
|
|
DMA_TimeOut_State <= toutSt_CountUp;
|
902 |
|
|
end if;
|
903 |
|
|
|
904 |
|
|
when toutSt_Pause =>
|
905 |
|
|
cnt_DMA_TO <= cnt_DMA_TO;
|
906 |
|
|
Tout_Lo_Carry <= Tout_Lo_Carry;
|
907 |
|
|
if DMA_Start='1' then
|
908 |
|
|
DMA_TimeOut_State <= toutSt_CountUp;
|
909 |
|
|
elsif DMA_Done_i='1' then
|
910 |
|
|
DMA_TimeOut_State <= toutSt_Idle;
|
911 |
|
|
else
|
912 |
|
|
DMA_TimeOut_State <= toutSt_Pause;
|
913 |
|
|
end if;
|
914 |
|
|
|
915 |
|
|
when Others =>
|
916 |
|
|
cnt_DMA_TO <= cnt_DMA_TO;
|
917 |
|
|
Tout_Lo_Carry <= Tout_Lo_Carry;
|
918 |
|
|
DMA_TimeOut_State <= toutSt_Idle;
|
919 |
|
|
|
920 |
|
|
end case;
|
921 |
|
|
|
922 |
|
|
|
923 |
|
|
|
924 |
|
|
-- case DMA_State is
|
925 |
|
|
--
|
926 |
|
|
-- when dmaST_Init =>
|
927 |
|
|
-- cnt_DMA_TO <= (Others=>'0');
|
928 |
|
|
-- Tout_Lo_Carry <= '0';
|
929 |
|
|
--
|
930 |
|
|
-- when dmaST_Snout =>
|
931 |
|
|
-- cnt_DMA_TO <= (Others=>'0');
|
932 |
|
|
-- Tout_Lo_Carry <= '0';
|
933 |
|
|
--
|
934 |
|
|
--
|
935 |
|
|
-- when Others =>
|
936 |
|
|
-- cnt_DMA_TO(CBIT_CARRY-1 downto 0) <= cnt_DMA_TO(CBIT_CARRY-1 downto 0) + '1';
|
937 |
|
|
--
|
938 |
|
|
-- if cnt_DMA_TO(CBIT_CARRY-1 downto 0)=C_ALL_ONES(CBIT_CARRY-1 downto 0) then
|
939 |
|
|
-- Tout_Lo_Carry <= '1';
|
940 |
|
|
-- else
|
941 |
|
|
-- Tout_Lo_Carry <= '0';
|
942 |
|
|
-- end if;
|
943 |
|
|
--
|
944 |
|
|
-- if Tout_Lo_Carry='1' then
|
945 |
|
|
-- cnt_DMA_TO(C_TOUT_WIDTH-1 downto CBIT_CARRY) <= cnt_DMA_TO(C_TOUT_WIDTH-1 downto CBIT_CARRY) + '1';
|
946 |
|
|
-- else
|
947 |
|
|
-- cnt_DMA_TO(C_TOUT_WIDTH-1 downto CBIT_CARRY) <= cnt_DMA_TO(C_TOUT_WIDTH-1 downto CBIT_CARRY);
|
948 |
|
|
-- end if;
|
949 |
|
|
--
|
950 |
|
|
-- end case;
|
951 |
|
|
|
952 |
|
|
end if;
|
953 |
|
|
end process;
|
954 |
|
|
|
955 |
|
|
|
956 |
|
|
-- ----------------------------------------------
|
957 |
|
|
-- Time out state bit
|
958 |
|
|
-- Synchronous Output: DMA_TimeOut_i
|
959 |
|
|
FSM_DMA_TimeOut:
|
960 |
|
|
process ( dma_clk, dma_reset)
|
961 |
|
|
begin
|
962 |
|
|
if dma_reset = '1' then
|
963 |
|
|
DMA_TimeOut_i <= '0';
|
964 |
|
|
elsif dma_clk'event and dma_clk = '1' then
|
965 |
|
|
-- Capture the time-out trigger
|
966 |
|
|
-- if cnt_DMA_TO(CBIT_TOUT_BOT downto 0) = C_TIME_OUT_VALUE then
|
967 |
|
|
if cnt_DMA_TO(C_TOUT_WIDTH-1 downto CBIT_TOUT_BOT) = C_TIME_OUT_VALUE then
|
968 |
|
|
DMA_TimeOut_i <= '1';
|
969 |
|
|
else
|
970 |
|
|
DMA_TimeOut_i <= DMA_TimeOut_i;
|
971 |
|
|
end if;
|
972 |
|
|
|
973 |
|
|
end if;
|
974 |
|
|
end process;
|
975 |
|
|
|
976 |
|
|
|
977 |
|
|
end architecture Behavioral;
|