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[/] [pcie_sg_dma/] [trunk/] [rtl/] [Registers.vhd] - Blame information for rev 2

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Line No. Rev Author Line
1 2 weng_ziti 
----------------------------------------------------------------------------------
2 
-- Company:  ziti, Uni. HD
3 
-- Engineer:  wgao
4 
--
5 
-- Design Name:
6 
-- Module Name:    Regs_Group - Behavioral
7 
-- Project Name:
8 
-- Target Devices:
9 
-- Tool versions:
10 
-- Description:
11 
--
12 
-- Dependencies:
13 
--
14 
-- Revision:
15 
--
16 
-- Revision 1.00 - first release.  06.02.2007
17 
--
18 
-- Additional Comments:
19 
--
20 
----------------------------------------------------------------------------------
21 
 
22 
library IEEE;
23 
use IEEE.STD_LOGIC_1164.ALL;
24 
use IEEE.STD_LOGIC_ARITH.ALL;
25 
use IEEE.STD_LOGIC_UNSIGNED.ALL;
26 
 
27 
 
28 
library work;
29 
use work.abb64Package.all;
30 
 
31 
---- Uncomment the following library declaration if instantiating
32 
---- any Xilinx primitives in this code.
33 
library UNISIM;
34 
use UNISIM.VComponents.all;
35 
 
36 
entity Regs_Group is
37 
    port (
38 
 
39 
      -- DCB protocol interface
40 
      protocol_link_act        : IN  std_logic_vector(2-1 downto 0);
41 
      protocol_rst             : OUT std_logic;
42 
 
43 
      -- Fabric side: CTL Rx
44 
      ctl_rv                   : OUT std_logic;
45 
      ctl_rd                   : OUT std_logic_vector(C_DBUS_WIDTH/2-1 downto 0);
46 
 
47 
      -- Fabric side: CTL Tx
48 
      ctl_ttake                : OUT std_logic;
49 
      ctl_tv                   : IN  std_logic;
50 
      ctl_td                   : IN  std_logic_vector(C_DBUS_WIDTH/2-1 downto 0);
51 
      ctl_tstop                : OUT std_logic;
52 
 
53 
      ctl_reset                : OUT std_logic;
54 
      ctl_status               : IN  std_logic_vector(C_DBUS_WIDTH/2-1 downto 0);
55 
 
56 
      -- Fabric side: DLM Rx
57 
      dlm_tv                   : OUT std_logic;
58 
      dlm_td                   : OUT std_logic_vector(C_DBUS_WIDTH/2-1 downto 0);
59 
 
60 
      -- Fabric side: DLM Tx
61 
      dlm_rv                   : IN  std_logic;
62 
      dlm_rd                   : IN  std_logic_vector(C_DBUS_WIDTH/2-1 downto 0);
63 
 
64 
      -- Event Buffer status + reset
65 
      eb_FIFO_Status           : IN  std_logic_vector(C_DBUS_WIDTH-1 downto 0);
66 
      eb_FIFO_Rst              : OUT std_logic;
67 
      eb_FIFO_ow               : IN  std_logic;
68 
 
69 
      self_feed_daq            : OUT std_logic;
70 
 
71 
      -- Write interface
72 
      Regs_WrEnA               : IN  std_logic;
73 
      Regs_WrMaskA             : IN  std_logic_vector(2-1 downto 0);
74 
      Regs_WrAddrA             : IN  std_logic_vector(C_EP_AWIDTH-1 downto 0);
75 
      Regs_WrDinA              : IN  std_logic_vector(C_DBUS_WIDTH-1 downto 0);
76 
 
77 
      Regs_WrEnB               : IN  std_logic;
78 
      Regs_WrMaskB             : IN  std_logic_vector(2-1 downto 0);
79 
      Regs_WrAddrB             : IN  std_logic_vector(C_EP_AWIDTH-1 downto 0);
80 
      Regs_WrDinB              : IN  std_logic_vector(C_DBUS_WIDTH-1 downto 0);
81 
 
82 
      -- Register Read interface
83 
      Regs_RdAddr              : IN  std_logic_vector(C_EP_AWIDTH-1 downto 0);
84 
      Regs_RdQout              : OUT std_logic_vector(C_DBUS_WIDTH-1 downto 0);
85 
 
86 
      -- Downstream DMA transferred bytes count up
87 
      ds_DMA_Bytes_Add         : IN  std_logic;
88 
      ds_DMA_Bytes             : IN  std_logic_vector(C_TLP_FLD_WIDTH_OF_LENG+2 downto 0);
89 
 
90 
     -- Registers to/from Downstream Engine
91 
      DMA_ds_PA                : OUT std_logic_vector(C_DBUS_WIDTH-1 downto 0);
92 
      DMA_ds_HA                : OUT std_logic_vector(C_DBUS_WIDTH-1 downto 0);
93 
      DMA_ds_BDA               : OUT std_logic_vector(C_DBUS_WIDTH-1 downto 0);
94 
      DMA_ds_Length            : OUT std_logic_vector(C_DBUS_WIDTH-1 downto 0);
95 
      DMA_ds_Control           : OUT std_logic_vector(C_DBUS_WIDTH-1 downto 0);
96 
      dsDMA_BDA_eq_Null        : OUT std_logic;      -- obsolete
97 
      DMA_ds_Status            : IN  std_logic_vector(C_DBUS_WIDTH-1 downto 0);
98 
      DMA_ds_Done              : IN  std_logic;
99 
      DMA_ds_Tout              : IN  std_logic;
100 
 
101 
      -- Calculation in advance, for better timing
102 
      dsHA_is_64b              : OUT std_logic;
103 
      dsBDA_is_64b             : OUT std_logic;
104 
 
105 
      -- Calculation in advance, for better timing
106 
      dsLeng_Hi19b_True        : OUT std_logic;
107 
      dsLeng_Lo7b_True         : OUT std_logic;
108 
 
109 
      -- Downstream Control Signals
110 
      dsDMA_Start              : OUT std_logic;
111 
      dsDMA_Stop               : OUT std_logic;
112 
      dsDMA_Start2             : OUT std_logic;
113 
      dsDMA_Stop2              : OUT std_logic;
114 
      dsDMA_Channel_Rst        : OUT std_logic;
115 
      dsDMA_Cmd_Ack            : IN  std_logic;
116 
 
117 
 
118 
      -- Upstream DMA transferred bytes count up
119 
      us_DMA_Bytes_Add         : IN  std_logic;
120 
      us_DMA_Bytes             : IN  std_logic_vector(C_TLP_FLD_WIDTH_OF_LENG+2 downto 0);
121 
 
122 
      -- Registers to/from Upstream Engine
123 
      DMA_us_PA                : OUT std_logic_vector(C_DBUS_WIDTH-1 downto 0);
124 
      DMA_us_HA                : OUT std_logic_vector(C_DBUS_WIDTH-1 downto 0);
125 
      DMA_us_BDA               : OUT std_logic_vector(C_DBUS_WIDTH-1 downto 0);
126 
      DMA_us_Length            : OUT std_logic_vector(C_DBUS_WIDTH-1 downto 0);
127 
      DMA_us_Control           : OUT std_logic_vector(C_DBUS_WIDTH-1 downto 0);
128 
      usDMA_BDA_eq_Null        : OUT std_logic;      -- obsolete
129 
      us_MWr_Param_Vec         : OUT std_logic_vector(6-1 downto 0);
130 
      DMA_us_Status            : IN  std_logic_vector(C_DBUS_WIDTH-1 downto 0);
131 
      DMA_us_Done              : IN  std_logic;
132 
      DMA_us_Tout              : IN  std_logic;
133 
 
134 
      -- Calculation in advance, for better timing
135 
      usHA_is_64b              : OUT std_logic;
136 
      usBDA_is_64b             : OUT std_logic;
137 
 
138 
      -- Calculation in advance, for better timing
139 
      usLeng_Hi19b_True        : OUT std_logic;
140 
      usLeng_Lo7b_True         : OUT std_logic;
141 
 
142 
      -- Upstream Control Signals
143 
      usDMA_Start              : OUT std_logic;
144 
      usDMA_Stop               : OUT std_logic;
145 
      usDMA_Start2             : OUT std_logic;
146 
      usDMA_Stop2              : OUT std_logic;
147 
      usDMA_Channel_Rst        : OUT std_logic;
148 
      usDMA_Cmd_Ack            : IN  std_logic;
149 
 
150 
      -- MRd Channel Reset
151 
      MRd_Channel_Rst          : OUT std_logic;
152 
 
153 
      -- Tx module reset
154 
      Tx_Reset                 : OUT std_logic;
155 
 
156 
                -- to Interrupts Module
157 
      Sys_IRQ                  : OUT std_logic_vector(C_DBUS_WIDTH-1 downto 0);
158 
      DAQ_irq                  : IN  std_logic;
159 
      CTL_irq                  : IN  std_logic;
160 
      DLM_irq                  : IN  std_logic;
161 
 
162 
      -- System error and info
163 
      Tx_TimeOut               : IN  std_logic;
164 
      Tx_eb_TimeOut            : IN  std_logic;
165 
      Msg_Routing              : OUT std_logic_vector(C_GCR_MSG_ROUT_BIT_TOP-C_GCR_MSG_ROUT_BIT_BOT downto 0);
166 
      pcie_link_width          : IN  std_logic_vector(CINT_BIT_LWIDTH_IN_GSR_TOP-CINT_BIT_LWIDTH_IN_GSR_BOT downto 0);
167 
      cfg_dcommand             : IN  std_logic_vector(16-1 downto 0);
168 
 
169 
      -- Interrupt Generation Signals
170 
      IG_Reset                 : OUT std_logic;
171 
      IG_Host_Clear            : OUT std_logic;
172 
      IG_Latency               : OUT std_logic_vector(C_DBUS_WIDTH-1 downto 0);
173 
      IG_Num_Assert            : IN  std_logic_vector(C_DBUS_WIDTH-1 downto 0);
174 
      IG_Num_Deassert          : IN  std_logic_vector(C_DBUS_WIDTH-1 downto 0);
175 
      IG_Asserting             : IN  std_logic;
176 
 
177 
      -- Data generator control
178 
      DG_is_Running            : IN  std_logic;
179 
      DG_Reset                 : OUT std_logic;
180 
      DG_Mask                  : OUT std_logic;
181 
 
182 
      -- Clock and reset
183 
      trn_clk                  : IN  std_logic;
184 
      trn_lnk_up_n             : IN  std_logic;
185 
      trn_reset_n              : IN  std_logic
186 
 
187 
    );
188 
end Regs_Group;
189 
 
190 
 
191 
architecture Behavioral of Regs_Group is
192 
 
193 
  type    icapStates is        ( icapST_Reset
194 
                               , icapST_Idle
195 
                               , icapST_Access
196 
                               , icapST_Abort
197 
                               );
198 
 
199 
  -- State variables of ICAP
200 
  signal  FSM_icap             : icapStates;
201 
 
202 
 
203 
  ----------------------------------------------------------------------------
204 
  ----------------------------------------------------------------------------
205 
  signal  Regs_WrDin_i         : std_logic_vector(C_DBUS_WIDTH-1   downto 0);
206 
  signal  Regs_WrAddr_i        : std_logic_vector(C_EP_AWIDTH-1   downto 0);
207 
  signal  Regs_WrMask_i        : std_logic_vector(2-1   downto 0);
208 
 
209 
  ------  Delay signals
210 
  signal  Regs_WrEn_r1         : std_logic;
211 
  signal  Regs_WrAddr_r1       : std_logic_vector(C_EP_AWIDTH-1   downto 0);
212 
  signal  Regs_WrMask_r1       : std_logic_vector(2-1   downto 0);
213 
  signal  Regs_WrDin_r1        : std_logic_vector(C_DBUS_WIDTH-1   downto 0);
214 
  signal  Regs_WrEn_r2         : std_logic;
215 
  signal  Regs_WrDin_r2        : std_logic_vector(C_DBUS_WIDTH-1   downto 0);
216 
  signal  Regs_Wr_dma_V_hi_r2     : std_logic;
217 
  signal  Regs_Wr_dma_nV_hi_r2    : std_logic;
218 
  signal  Regs_Wr_dma_V_nE_hi_r2  : std_logic;
219 
  signal  Regs_Wr_dma_V_lo_r2     : std_logic;
220 
  signal  Regs_Wr_dma_nV_lo_r2    : std_logic;
221 
  signal  Regs_Wr_dma_V_nE_lo_r2  : std_logic;
222 
  signal  WrDin_r1_not_Zero_Hi    : std_logic_vector(4-1 downto 0);
223 
  signal  WrDin_r2_not_Zero_Hi    : std_logic;
224 
  signal  WrDin_r1_not_Zero_Lo    : std_logic_vector(4-1 downto 0);
225 
  signal  WrDin_r2_not_Zero_Lo    : std_logic;
226 
 
227 
  --      Calculation in advance, just for better timing
228 
  signal  Regs_WrDin_Hi19b_True_hq_r2 : std_logic;
229 
  signal  Regs_WrDin_Lo7b_True_hq_r2  : std_logic;
230 
  signal  Regs_WrDin_Hi19b_True_lq_r2 : std_logic;
231 
  signal  Regs_WrDin_Lo7b_True_lq_r2  : std_logic;
232 
 
233 
  signal  Regs_WrEnA_r1           : std_logic;
234 
  signal  Regs_WrEnB_r1           : std_logic;
235 
  signal  Regs_WrEnA_r2           : std_logic;
236 
  signal  Regs_WrEnB_r2           : std_logic;
237 
 
238 
  --      Register write mux signals
239 
  signal  Reg_WrMuxer_Hi          : std_logic_vector(C_NUM_OF_ADDRESSES-1 downto 0);
240 
  signal  Reg_WrMuxer_Lo          : std_logic_vector(C_NUM_OF_ADDRESSES-1 downto 0);
241 
 
242 
 
243 
  -- Signals for Tx reading
244 
  signal  Regs_RdAddr_i           : std_logic_vector(C_EP_AWIDTH-1   downto 0);
245 
  signal  Regs_RdQout_i           : std_logic_vector(C_DBUS_WIDTH-1   downto 0);
246 
 
247 
  --      Register read mux signals
248 
  signal  Reg_RdMuxer_Hi          : std_logic_vector(C_NUM_OF_ADDRESSES-1 downto 0);
249 
  signal  Reg_RdMuxer_Lo          : std_logic_vector(C_NUM_OF_ADDRESSES-1 downto 0);
250 
 
251 
  -- Optical Link status
252 
  signal  Opto_Link_Status_i      : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
253 
  signal  Opto_Link_Status_o_Hi   : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
254 
  signal  Opto_Link_Status_o_Lo   : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
255 
  -- Event Buffer
256 
  signal  eb_FIFO_Status_r1       : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
257 
  signal  eb_FIFO_Status_o_Hi     : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
258 
  signal  eb_FIFO_Status_o_Lo     : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
259 
  signal  eb_FIFO_Rst_i           : std_logic;
260 
  signal  eb_FIFO_Rst_b1          : std_logic;
261 
  signal  eb_FIFO_Rst_b2          : std_logic;
262 
  signal  eb_FIFO_Rst_b3          : std_logic;
263 
  signal  eb_FIFO_OverWritten     : std_logic;
264 
 
265 
  -- Downstream DMA registers
266 
  signal  DMA_ds_PA_o_Hi          : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
267 
  signal  DMA_ds_HA_o_Hi          : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
268 
  signal  DMA_ds_BDA_o_Hi         : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
269 
  signal  DMA_ds_Length_o_Hi      : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
270 
  signal  DMA_ds_Control_o_Hi     : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
271 
  signal  DMA_ds_Status_o_Hi      : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
272 
  signal  DMA_ds_Transf_Bytes_o_Hi      : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
273 
  signal  DMA_ds_PA_o_Lo          : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
274 
  signal  DMA_ds_HA_o_Lo          : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
275 
  signal  DMA_ds_BDA_o_Lo         : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
276 
  signal  DMA_ds_Length_o_Lo      : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
277 
  signal  DMA_ds_Control_o_Lo     : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
278 
  signal  DMA_ds_Status_o_Lo      : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
279 
  signal  DMA_ds_Transf_Bytes_o_Lo      : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
280 
 
281 
  -- Upstream DMA registers
282 
  signal  DMA_us_PA_o_Hi          : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
283 
  signal  DMA_us_HA_o_Hi          : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
284 
  signal  DMA_us_BDA_o_Hi         : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
285 
  signal  DMA_us_Length_o_Hi      : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
286 
  signal  DMA_us_Control_o_Hi     : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
287 
  signal  DMA_us_Status_o_Hi      : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
288 
  signal  DMA_us_Transf_Bytes_o_Hi      : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
289 
  signal  DMA_us_PA_o_Lo          : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
290 
  signal  DMA_us_HA_o_Lo          : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
291 
  signal  DMA_us_BDA_o_Lo         : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
292 
  signal  DMA_us_Length_o_Lo      : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
293 
  signal  DMA_us_Control_o_Lo     : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
294 
  signal  DMA_us_Status_o_Lo      : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
295 
  signal  DMA_us_Transf_Bytes_o_Lo      : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
296 
 
297 
 
298 
  -- System Interrupt Status/Control
299 
  signal  Sys_IRQ_i               : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
300 
  signal  Sys_Int_Status_i        : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
301 
  signal  Sys_Int_Status_o_Hi     : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
302 
  signal  Sys_Int_Status_o_Lo     : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
303 
 
304 
  signal  Sys_Int_Enable_i        : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
305 
  signal  Sys_Int_Enable_o_Hi     : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
306 
  signal  Sys_Int_Enable_o_Lo     : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
307 
 
308 
 
309 
  -- Data generator control
310 
  signal  DG_Reset_i              : std_logic;
311 
  signal  DG_Mask_i               : std_logic;
312 
  signal  DG_is_Available         : std_logic;
313 
  signal  DG_Rst_Counter          : std_logic_vector(8-1 downto 0);
314 
  signal  DG_Status_i             : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
315 
  signal  DG_Status_o_Hi          : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
316 
  signal  DG_Status_o_Lo          : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
317 
 
318 
  -- General Control and Status
319 
  signal  Sys_Error_i             : std_logic_vector(C_DBUS_WIDTH-1   downto 0);
320 
  signal  Sys_Error_o_Hi          : std_logic_vector(C_DBUS_WIDTH-1   downto 0);
321 
  signal  Sys_Error_o_Lo          : std_logic_vector(C_DBUS_WIDTH-1   downto 0);
322 
 
323 
  signal  General_Control_i       : std_logic_vector(C_DBUS_WIDTH-1   downto 0);
324 
  signal  General_Control_o_Hi    : std_logic_vector(C_DBUS_WIDTH-1   downto 0);
325 
  signal  General_Control_o_Lo    : std_logic_vector(C_DBUS_WIDTH-1   downto 0);
326 
 
327 
  signal  General_Status_i        : std_logic_vector(C_DBUS_WIDTH-1   downto 0);
328 
  signal  General_Status_o_Hi     : std_logic_vector(C_DBUS_WIDTH-1   downto 0);
329 
  signal  General_Status_o_Lo     : std_logic_vector(C_DBUS_WIDTH-1   downto 0);
330 
 
331 
  -- Hardward version
332 
  signal  HW_Version_o_Hi         : std_logic_vector(C_DBUS_WIDTH-1   downto 0);
333 
  signal  HW_Version_o_Lo         : std_logic_vector(C_DBUS_WIDTH-1   downto 0);
334 
 
335 
  -- Signal as the source of interrupts
336 
  signal  IG_Host_Clear_i         : std_logic;
337 
  signal  IG_Reset_i              : std_logic;
338 
 
339 
  -- Interrupt Generator Control
340 
  signal  IG_Control_i            : std_logic_vector(C_DBUS_WIDTH-1   downto 0);
341 
 
342 
  -- Interrupt Generator Latency
343 
  signal  IG_Latency_i            : std_logic_vector(C_DBUS_WIDTH-1   downto 0);
344 
  signal  IG_Latency_o_Hi         : std_logic_vector(C_DBUS_WIDTH-1   downto 0);
345 
  signal  IG_Latency_o_Lo         : std_logic_vector(C_DBUS_WIDTH-1   downto 0);
346 
 
347 
  -- Interrupt Generator Statistic: Assert number
348 
  signal  IG_Num_Assert_i         : std_logic_vector(C_DBUS_WIDTH-1   downto 0);
349 
  signal  IG_Num_Assert_o_Hi      : std_logic_vector(C_DBUS_WIDTH-1   downto 0);
350 
  signal  IG_Num_Assert_o_Lo      : std_logic_vector(C_DBUS_WIDTH-1   downto 0);
351 
 
352 
  -- Interrupt Generator Statistic: Deassert number
353 
  signal  IG_Num_Deassert_i       : std_logic_vector(C_DBUS_WIDTH-1   downto 0);
354 
  signal  IG_Num_Deassert_o_Hi    : std_logic_vector(C_DBUS_WIDTH-1   downto 0);
355 
  signal  IG_Num_Deassert_o_Lo    : std_logic_vector(C_DBUS_WIDTH-1   downto 0);
356 
 
357 
  -- IntClr character is written
358 
  signal  Command_is_Host_iClr_Hi : std_logic;
359 
  signal  Command_is_Host_iClr_Lo : std_logic;
360 
 
361 
  -- Downstream Registers
362 
  signal  DMA_ds_PA_i          : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
363 
  signal  DMA_ds_HA_i          : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
364 
  signal  DMA_ds_BDA_i         : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
365 
  signal  DMA_ds_Length_i      : std_logic_vector(C_DBUS_WIDTH-1   downto 0);
366 
  signal  DMA_ds_Control_i     : std_logic_vector(C_DBUS_WIDTH-1   downto 0);
367 
  signal  DMA_ds_Status_i      : std_logic_vector(C_DBUS_WIDTH-1   downto 0);
368 
  signal  DMA_ds_Transf_Bytes_i      : std_logic_vector(C_DBUS_WIDTH-1   downto 0);
369 
 
370 
  signal  Last_Ctrl_Word_ds    : std_logic_vector(C_DBUS_WIDTH-1   downto 0);
371 
 
372 
  -- Calculation in advance, for better timing
373 
  signal  dsHA_is_64b_i        : std_logic;
374 
  signal  dsBDA_is_64b_i       : std_logic;
375 
 
376 
  -- Calculation in advance, for better timing
377 
  signal  dsLeng_Hi19b_True_i  : std_logic;
378 
  signal  dsLeng_Lo7b_True_i   : std_logic;
379 
 
380 
  -- Downstream Control Signals
381 
  signal  dsDMA_Start_i        : std_logic;
382 
  signal  dsDMA_Stop_i         : std_logic;
383 
  signal  dsDMA_Start2_i       : std_logic;
384 
  signal  dsDMA_Start2_r1      : std_logic;
385 
  signal  dsDMA_Stop2_i        : std_logic;
386 
  signal  dsDMA_Channel_Rst_i  : std_logic;
387 
  signal  ds_Param_Modified    : std_logic;
388 
 
389 
 
390 
  -- Upstream Registers
391 
  signal  DMA_us_PA_i          : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
392 
  signal  DMA_us_HA_i          : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
393 
  signal  DMA_us_BDA_i         : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
394 
  signal  DMA_us_Length_i      : std_logic_vector(C_DBUS_WIDTH-1   downto 0);
395 
  signal  DMA_us_Control_i     : std_logic_vector(C_DBUS_WIDTH-1   downto 0);
396 
  signal  DMA_us_Status_i      : std_logic_vector(C_DBUS_WIDTH-1   downto 0);
397 
  signal  DMA_us_Transf_Bytes_i      : std_logic_vector(C_DBUS_WIDTH-1   downto 0);
398 
 
399 
  signal  Last_Ctrl_Word_us    : std_logic_vector(C_DBUS_WIDTH-1   downto 0);
400 
 
401 
  -- Calculation in advance, for better timing
402 
  signal  usHA_is_64b_i        : std_logic;
403 
  signal  usBDA_is_64b_i       : std_logic;
404 
 
405 
  -- Calculation in advance, for better timing
406 
  signal  usLeng_Hi19b_True_i  : std_logic;
407 
  signal  usLeng_Lo7b_True_i   : std_logic;
408 
 
409 
 
410 
  -- Upstream Control Signals
411 
  signal  usDMA_Start_i        : std_logic;
412 
  signal  usDMA_Stop_i         : std_logic;
413 
  signal  usDMA_Start2_i       : std_logic;
414 
  signal  usDMA_Start2_r1      : std_logic;
415 
  signal  usDMA_Stop2_i        : std_logic;
416 
  signal  usDMA_Channel_Rst_i  : std_logic;
417 
  signal  us_Param_Modified    : std_logic;
418 
 
419 
  -- Reset character is written
420 
  signal  Command_is_Reset_Hi  : std_logic;
421 
  signal  Command_is_Reset_Lo  : std_logic;
422 
 
423 
  -- MRd channel reset
424 
  signal  MRd_Channel_Rst_i    : std_logic;
425 
 
426 
  -- Tx module reset
427 
  signal  Tx_Reset_i           : std_logic;
428 
 
429 
 
430 
  -- ICAP
431 
  signal  icap_CLK             : std_logic;
432 
  signal  icap_I               : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
433 
  signal  icap_CE              : std_logic;
434 
  signal  icap_Write           : std_logic;
435 
  signal  icap_O               : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
436 
  signal  icap_O_o_Hi          : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
437 
  signal  icap_O_o_Lo          : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
438 
  signal  icap_BUSY            : std_logic;
439 
 
440 
  -- DCB protocol interface
441 
  signal  protocol_rst_i       : std_logic;
442 
  signal  protocol_rst_b1      : std_logic;
443 
  signal  protocol_rst_b2      : std_logic;
444 
 
445 
  -- Protocol : CTL
446 
  signal  ctl_rv_i             : std_logic;
447 
  signal  ctl_rd_i             : std_logic_vector(C_DBUS_WIDTH/2-1 downto 0);
448 
 
449 
  signal  class_CTL_Status_i   : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
450 
  signal  class_CTL_Status_o_Hi: std_logic_vector(C_DBUS_WIDTH-1 downto 0);
451 
  signal  class_CTL_Status_o_Lo: std_logic_vector(C_DBUS_WIDTH-1 downto 0);
452 
 
453 
  signal  ctl_td_o_Hi          : std_logic_vector(C_DBUS_WIDTH/2-1 downto 0);
454 
  signal  ctl_td_o_Lo          : std_logic_vector(C_DBUS_WIDTH/2-1 downto 0);
455 
  signal  ctl_td_r             : std_logic_vector(C_DBUS_WIDTH/2-1 downto 0);
456 
 
457 
  signal  ctl_reset_i          : std_logic;
458 
  signal  ctl_ttake_i          : std_logic;
459 
  signal  ctl_tstop_i          : std_logic;
460 
  signal  ctl_t_read_Hi_r1     : std_logic;
461 
  signal  ctl_t_read_Lo_r1     : std_logic;
462 
  signal  CTL_read_counter     : std_logic_vector(6-1 downto 0);
463 
 
464 
  -- Protocol : DLM
465 
  signal  dlm_tv_i             : std_logic;
466 
  signal  dlm_td_i             : std_logic_vector(C_DBUS_WIDTH/2-1 downto 0);
467 
 
468 
  signal  dlm_rd_o_Hi          : std_logic_vector(C_DBUS_WIDTH/2-1 downto 0);
469 
  signal  dlm_rd_o_Lo          : std_logic_vector(C_DBUS_WIDTH/2-1 downto 0);
470 
  signal  dlm_rd_r             : std_logic_vector(C_DBUS_WIDTH/2-1 downto 0);
471 
 
472 
begin
473 
 
474 
 
475 
   DG_is_Available   <= '0';
476 
 
477 
   -- protocol interface reset
478 
   protocol_rst         <= protocol_rst_i;
479 
 
480 
   ctl_rv               <= ctl_rv_i;
481 
   ctl_rd               <= ctl_rd_i;
482 
 
483 
   ctl_ttake            <= ctl_ttake_i;
484 
   ctl_tstop            <= ctl_tstop_i;
485 
   ctl_reset            <= ctl_reset_i;
486 
 
487 
   ctl_tstop_i          <= '0';   -- ???
488 
 
489 
   dlm_tv               <= dlm_tv_i;
490 
   dlm_td               <= dlm_td_i;
491 
 
492 
   -- Data generator control
493 
   DG_Reset             <= DG_Reset_i;
494 
   DG_Mask              <= DG_Mask_i;
495 
 
496 
   -- Event buffer reset
497 
   eb_FIFO_Rst          <= eb_FIFO_Rst_i;
498 
 
499 
   -- MRd channel reset
500 
   MRd_Channel_Rst      <= MRd_Channel_Rst_i;
501 
 
502 
   -- Tx module reset
503 
   Tx_Reset             <= Tx_Reset_i;
504 
 
505 
   -- Upstream DMA engine reset
506 
   usDMA_Channel_Rst    <= usDMA_Channel_Rst_i;
507 
 
508 
   -- Downstream DMA engine reset
509 
   dsDMA_Channel_Rst    <= dsDMA_Channel_Rst_i;
510 
 
511 
 
512 
   -- Upstream DMA registers
513 
   DMA_us_PA            <= DMA_us_PA_i;
514 
   DMA_us_HA            <= DMA_us_HA_i;
515 
   DMA_us_BDA           <= DMA_us_BDA_i;
516 
   DMA_us_Length        <= DMA_us_Length_i;
517 
   DMA_us_Control       <= DMA_us_Control_i;
518 
   usDMA_BDA_eq_Null    <= '0';
519 
   DMA_us_Status_i      <= DMA_us_Status;
520 
 
521 
   usHA_is_64b          <= usHA_is_64b_i;
522 
   usBDA_is_64b         <= usBDA_is_64b_i;
523 
 
524 
   usLeng_Hi19b_True    <= usLeng_Hi19b_True_i;
525 
   usLeng_Lo7b_True     <= usLeng_Lo7b_True_i;
526 
 
527 
   usDMA_Start          <= usDMA_Start_i;
528 
   usDMA_Stop           <= usDMA_Stop_i;
529 
   usDMA_Start2         <= usDMA_Start2_r1;
530 
--   usDMA_Start2         <= usDMA_Start2_i;
531 
   usDMA_Stop2          <= usDMA_Stop2_i;
532 
 
533 
   -- Downstream DMA registers
534 
   DMA_ds_PA            <= DMA_ds_PA_i;
535 
   DMA_ds_HA            <= DMA_ds_HA_i;
536 
   DMA_ds_BDA           <= DMA_ds_BDA_i;
537 
   DMA_ds_Length        <= DMA_ds_Length_i;
538 
   DMA_ds_Control       <= DMA_ds_Control_i;
539 
   dsDMA_BDA_eq_Null    <= '0';
540 
   DMA_ds_Status_i      <= DMA_ds_Status;
541 
 
542 
   dsHA_is_64b          <= dsHA_is_64b_i;
543 
   dsBDA_is_64b         <= dsBDA_is_64b_i;
544 
 
545 
   dsLeng_Hi19b_True    <= dsLeng_Hi19b_True_i;
546 
   dsLeng_Lo7b_True     <= dsLeng_Lo7b_True_i;
547 
 
548 
   dsDMA_Start          <= dsDMA_Start_i;
549 
   dsDMA_Stop           <= dsDMA_Stop_i;
550 
   dsDMA_Start2         <= dsDMA_Start2_r1;
551 
--   dsDMA_Start2         <= dsDMA_Start2_i;
552 
   dsDMA_Stop2          <= dsDMA_Stop2_i;
553 
 
554 
 
555 
   -- Register to Interrupt handler module
556 
   Sys_IRQ              <= Sys_IRQ_i;
557 
 
558 
   -- Message routing method
559 
   Msg_Routing          <= General_Control_i(C_GCR_MSG_ROUT_BIT_TOP downto C_GCR_MSG_ROUT_BIT_BOT);
560 
 
561 
   -- us_MWr_TLP_Param
562 
   us_MWr_Param_Vec     <= General_Control_i(13 downto 8);
563 
 
564 
   self_feed_daq        <= General_Control_i(16);
565 
 
566 
 
567 
   -- -------------   Interrupt generator generation    ----------------------
568 
   Gen_IG:  if IMP_INT_GENERATOR generate
569 
 
570 
   IG_Reset             <= IG_Reset_i;
571 
   IG_Host_Clear        <= IG_Host_Clear_i;  -- and Sys_Int_Enable_i(CINT_BIT_INTGEN_IN_ISR);
572 
   IG_Latency           <= IG_Latency_i;
573 
   IG_Num_Assert_i      <= IG_Num_Assert;
574 
   IG_Num_Deassert_i    <= IG_Num_Deassert;
575 
 
576 
 
577 
-- -----------------------------------------------
578 
-- Synchronous Registered: IG_Control_i
579 
   SysReg_IntGen_Control:
580 
   process ( trn_clk, trn_lnk_up_n)
581 
   begin
582 
      if trn_lnk_up_n = '1' then
583 
         IG_Control_i          <= (OTHERS => '0');
584 
         IG_Reset_i            <= '1';
585 
         IG_Host_Clear_i       <= '0';
586 
 
587 
      elsif trn_clk'event and trn_clk = '1' then
588 
 
589 
        if Regs_WrEn_r2='1'
590 
                    and Reg_WrMuxer_Hi(CINT_ADDR_IG_CONTROL)='1'
591 
                         then
592 
            IG_Control_i(32-1 downto 0)       <=  Regs_WrDin_r2(64-1 downto 32);
593 
            IG_Reset_i         <=  Command_is_Reset_Hi;
594 
            IG_Host_Clear_i    <=  Command_is_Host_iClr_Hi;
595 
        elsif Regs_WrEn_r2='1'
596 
                    and Reg_WrMuxer_Lo(CINT_ADDR_IG_CONTROL)='1'
597 
                         then
598 
            IG_Control_i(32-1 downto 0)       <=  Regs_WrDin_r2(32-1 downto 0);
599 
            IG_Reset_i         <=  Command_is_Reset_Lo;
600 
            IG_Host_Clear_i    <=  Command_is_Host_iClr_Lo;
601 
        else
602 
            IG_Control_i       <=  IG_Control_i;
603 
            IG_Reset_i         <=  '0';
604 
            IG_Host_Clear_i    <=  '0';
605 
        end if;
606 
 
607 
      end if;
608 
   end process;
609 
 
610 
 
611 
-- -----------------------------------------------
612 
-- Synchronous Registered: IG_Latency_i
613 
   SysReg_IntGen_Latency:
614 
   process ( trn_clk, trn_lnk_up_n)
615 
   begin
616 
      if trn_lnk_up_n = '1' then
617 
         IG_Latency_i       <= (OTHERS => '0');
618 
 
619 
      elsif trn_clk'event and trn_clk = '1' then
620 
 
621 
        if IG_Reset_i='1' then
622 
            IG_Latency_i    <=  (OTHERS => '0');
623 
        elsif Regs_WrEn_r2='1'
624 
                    and Reg_WrMuxer_Hi(CINT_ADDR_IG_LATENCY)='1'
625 
                         then
626 
            IG_Latency_i(32-1 downto 0)    <=  Regs_WrDin_r2(64-1 downto 32);
627 
        elsif Regs_WrEn_r2='1'
628 
                    and Reg_WrMuxer_Lo(CINT_ADDR_IG_LATENCY)='1'
629 
                         then
630 
            IG_Latency_i(32-1 downto 0)    <=  Regs_WrDin_r2(32-1 downto 0);
631 
        else
632 
            IG_Latency_i    <=  IG_Latency_i;
633 
        end if;
634 
 
635 
      end if;
636 
   end process;
637 
 
638 
   end generate;
639 
 
640 
   NotGen_IG:  if not IMP_INT_GENERATOR generate
641 
 
642 
   IG_Reset             <= '0';
643 
   IG_Host_Clear        <= '0';
644 
   IG_Latency           <= (OTHERS=>'0');
645 
   IG_Num_Assert_i      <= (OTHERS=>'0');
646 
   IG_Num_Deassert_i    <= (OTHERS=>'0');
647 
 
648 
   IG_Control_i         <= (OTHERS=>'0');
649 
   IG_Reset_i           <= '0';
650 
   IG_Host_Clear_i      <= '0';
651 
   IG_Latency_i         <= (OTHERS=>'0');
652 
 
653 
   end generate;
654 
 
655 
 
656 
 
657 
-- ----------------------------------------------
658 
-- Synchronous Delay : Sys_IRQ_i
659 
--
660 
   Synch_Delay_Sys_IRQ:
661 
   process ( trn_clk, trn_lnk_up_n )
662 
   begin
663 
      if trn_lnk_up_n = '1' then
664 
         Sys_IRQ_i   <=  (OTHERS=>'0');
665 
 
666 
      elsif trn_clk'event and trn_clk = '1' then
667 
         Sys_IRQ_i(C_NUM_OF_INTERRUPTS-1 downto 0)
668 
                     <= Sys_Int_Enable_i(C_NUM_OF_INTERRUPTS-1 downto 0)
669 
                    and Sys_Int_Status_i(C_NUM_OF_INTERRUPTS-1 downto 0);
670 
 
671 
      end if;
672 
   end process;
673 
 
674 
 
675 
-- ----------------------------------------------
676 
-- Registers writing
677 
--
678 
   Regs_WrAddr_i        <= Regs_WrAddrA and Regs_WrAddrB;
679 
   Regs_WrMask_i        <= Regs_WrMaskA or  Regs_WrMaskB;
680 
   Regs_WrDin_i         <= Regs_WrDinA  or  Regs_WrDinB;
681 
 
682 
-- ----------------------------------------------
683 
-- Registers reading
684 
--
685 
   Regs_RdAddr_i        <= Regs_RdAddr;
686 
   Regs_RdQout          <= Regs_RdQout_i;
687 
 
688 
-- ----------------------------------------------
689 
-- Synchronous Delay : Regs_WrEn
690 
--
691 
   Synch_Delay_Regs_WrEn:
692 
   process ( trn_clk )
693 
   begin
694 
      if trn_clk'event and trn_clk = '1' then
695 
         Regs_WrEn_r1   <= Regs_WrEnA or Regs_WrEnB;
696 
         Regs_WrEn_r2   <= Regs_WrEn_r1;
697 
 
698 
         Regs_WrEnA_r1  <= Regs_WrEnA;
699 
         Regs_WrEnA_r2  <= Regs_WrEnA_r1;
700 
 
701 
         Regs_WrEnB_r1  <= Regs_WrEnB;
702 
         Regs_WrEnB_r2  <= Regs_WrEnB_r1;
703 
 
704 
      end if;
705 
   end process;
706 
 
707 
-- ----------------------------------------------
708 
-- Synchronous Delay : Opto_Link_Status
709 
--
710 
   Synch_Delay_Opto_Link_Status:
711 
   process ( trn_clk )
712 
   begin
713 
      if trn_clk'event and trn_clk = '1' then
714 
         Opto_Link_Status_i(C_DBUS_WIDTH-1 downto 2)   <= (OTHERS=>'0');
715 
         Opto_Link_Status_i(2-1 downto 0)   <= protocol_link_act;
716 
      end if;
717 
   end process;
718 
 
719 
-- ----------------------------------------------
720 
-- Synchronous Delay : eb_FIFO_Status
721 
--
722 
   Synch_Delay_eb_FIFO_Status:
723 
   process ( trn_clk )
724 
   begin
725 
      if trn_clk'event and trn_clk = '1' then
726 
         eb_FIFO_Status_r1   <= eb_FIFO_Status;
727 
      end if;
728 
   end process;
729 
 
730 
-- ----------------------------------------------
731 
-- Synchronous Delay : Regs_WrAddr
732 
--
733 
   Synch_Delay_Regs_WrAddr:
734 
   process ( trn_clk )
735 
   begin
736 
      if trn_clk'event and trn_clk = '1' then
737 
         Regs_WrAddr_r1   <= Regs_WrAddr_i;
738 
         Regs_WrMask_r1   <= Regs_WrMask_i;
739 
      end if;
740 
   end process;
741 
 
742 
-- ----------------------------------------------------
743 
-- Synchronous Delay : dsDMA_Start2
744 
--                     usDMA_Start2
745 
--   (Special recipe for 64-bit successive descriptors)
746 
--
747 
   Synch_Delay_DMA_Start2:
748 
   process ( trn_clk )
749 
   begin
750 
      if trn_clk'event and trn_clk = '1' then
751 
         dsDMA_Start2_r1   <= dsDMA_Start2_i and not dsDMA_Cmd_Ack;
752 
         usDMA_Start2_r1   <= usDMA_Start2_i and not usDMA_Cmd_Ack;
753 
      end if;
754 
   end process;
755 
 
756 
 
757 
-- ----------------------------------------------
758 
-- Synchronous Delay : Regs_WrDin_i
759 
--
760 
   Synch_Delay_Regs_WrDin:
761 
   process ( trn_clk )
762 
   begin
763 
      if trn_clk'event and trn_clk = '1' then
764 
         Regs_WrDin_r1   <= Regs_WrDin_i;
765 
         Regs_WrDin_r2   <= Regs_WrDin_r1;
766 
 
767 
         if Regs_WrDin_i(31+32 downto 24+32) = C_ALL_ZEROS(31+32 downto 24+32) then
768 
            WrDin_r1_not_Zero_Hi(3) <= '0';
769 
         else
770 
            WrDin_r1_not_Zero_Hi(3) <= '1';
771 
         end if;
772 
         if Regs_WrDin_i(23+32 downto 16+32) = C_ALL_ZEROS(23+32 downto 16+32) then
773 
            WrDin_r1_not_Zero_Hi(2) <= '0';
774 
         else
775 
            WrDin_r1_not_Zero_Hi(2) <= '1';
776 
         end if;
777 
         if Regs_WrDin_i(15+32 downto 8+32) = C_ALL_ZEROS(15+32 downto 8+32) then
778 
            WrDin_r1_not_Zero_Hi(1) <= '0';
779 
         else
780 
            WrDin_r1_not_Zero_Hi(1) <= '1';
781 
         end if;
782 
         if Regs_WrDin_i(7+32 downto 0+32) = C_ALL_ZEROS(7+32 downto 0+32) then
783 
            WrDin_r1_not_Zero_Hi(0) <= '0';
784 
         else
785 
            WrDin_r1_not_Zero_Hi(0) <= '1';
786 
         end if;
787 
 
788 
         if WrDin_r1_not_Zero_Hi = C_ALL_ZEROS(3 downto 0) then
789 
            WrDin_r2_not_Zero_Hi <= '0';
790 
         else
791 
            WrDin_r2_not_Zero_Hi <= '1';
792 
         end if;
793 
 
794 
 
795 
         if Regs_WrDin_i(31 downto 24) = C_ALL_ZEROS(31 downto 24) then
796 
            WrDin_r1_not_Zero_Lo(3) <= '0';
797 
         else
798 
            WrDin_r1_not_Zero_Lo(3) <= '1';
799 
         end if;
800 
         if Regs_WrDin_i(23 downto 16) = C_ALL_ZEROS(23 downto 16) then
801 
            WrDin_r1_not_Zero_Lo(2) <= '0';
802 
         else
803 
            WrDin_r1_not_Zero_Lo(2) <= '1';
804 
         end if;
805 
         if Regs_WrDin_i(15 downto 8) = C_ALL_ZEROS(15 downto 8) then
806 
            WrDin_r1_not_Zero_Lo(1) <= '0';
807 
         else
808 
            WrDin_r1_not_Zero_Lo(1) <= '1';
809 
         end if;
810 
         if Regs_WrDin_i(7 downto 0) = C_ALL_ZEROS(7 downto 0) then
811 
            WrDin_r1_not_Zero_Lo(0) <= '0';
812 
         else
813 
            WrDin_r1_not_Zero_Lo(0) <= '1';
814 
         end if;
815 
 
816 
         if WrDin_r1_not_Zero_Lo = C_ALL_ZEROS(3 downto 0) then
817 
            WrDin_r2_not_Zero_Lo <= '0';
818 
         else
819 
            WrDin_r2_not_Zero_Lo <= '1';
820 
         end if;
821 
      end if;
822 
   end process;
823 
 
824 
 
825 
-- -----------------------------------------------------------
826 
-- Synchronous Delay : DMA Commands Write Valid and not End
827 
--
828 
   Synch_Delay_dmaCmd_Wr_Valid_and_End:
829 
   process ( trn_clk )
830 
   begin
831 
      if trn_clk'event and trn_clk = '1' then
832 
         Regs_Wr_dma_V_hi_r2      <= Regs_WrEn_r1
833 
                               and Regs_WrDin_r1(CINT_BIT_DMA_CTRL_VALID+32)
834 
                               ;
835 
         Regs_Wr_dma_nV_hi_r2     <= Regs_WrEn_r1
836 
                               and not Regs_WrDin_r1(CINT_BIT_DMA_CTRL_VALID+32)
837 
                               ;
838 
         Regs_Wr_dma_V_nE_hi_r2   <= Regs_WrEn_r1
839 
                               and Regs_WrDin_r1(CINT_BIT_DMA_CTRL_VALID+32)
840 
                               and not Regs_WrDin_r1(CINT_BIT_DMA_CTRL_END+32)
841 
                               ;
842 
 
843 
 
844 
         Regs_Wr_dma_V_lo_r2      <= Regs_WrEn_r1
845 
                               and Regs_WrDin_r1(CINT_BIT_DMA_CTRL_VALID)
846 
                               ;
847 
         Regs_Wr_dma_nV_lo_r2     <= Regs_WrEn_r1
848 
                               and not Regs_WrDin_r1(CINT_BIT_DMA_CTRL_VALID)
849 
                               ;
850 
         Regs_Wr_dma_V_nE_lo_r2   <= Regs_WrEn_r1
851 
                               and Regs_WrDin_r1(CINT_BIT_DMA_CTRL_VALID)
852 
                               and not Regs_WrDin_r1(CINT_BIT_DMA_CTRL_END)
853 
                               ;
854 
      end if;
855 
   end process;
856 
 
857 
 
858 
 
859 
-- ------------------------------------------------
860 
-- Synchronous Delay : Regs_WrDin_Hi19b_True_r2 x2
861 
--                     Regs_WrDin_Lo7b_True_r2 x2
862 
--
863 
   Synch_Delay_Regs_WrDin_Hi19b_and_Lo7b_True:
864 
   process ( trn_clk )
865 
   begin
866 
      if trn_clk'event and trn_clk = '1' then
867 
 
868 
         if Regs_WrDin_r1(C_DBUS_WIDTH-1 downto C_MAXSIZE_FLD_BIT_TOP+1+32)
869 
            = C_ALL_ZEROS(C_DBUS_WIDTH-1 downto C_MAXSIZE_FLD_BIT_TOP+1+32)
870 
            then
871 
            Regs_WrDin_Hi19b_True_hq_r2  <= '0';
872 
         else
873 
            Regs_WrDin_Hi19b_True_hq_r2  <= '1';
874 
         end if;
875 
 
876 
         if Regs_WrDin_r1(C_MAXSIZE_FLD_BIT_BOT-1+32 downto 2+32)
877 
            = C_ALL_ZEROS(C_MAXSIZE_FLD_BIT_BOT-1+32 downto 2+32)
878 
            then                               -- ! Lowest 2 bits ignored !
879 
            Regs_WrDin_Lo7b_True_hq_r2  <= '0';
880 
         else
881 
            Regs_WrDin_Lo7b_True_hq_r2  <= '1';
882 
         end if;
883 
 
884 
         if Regs_WrDin_r1(C_DBUS_WIDTH-1-32 downto C_MAXSIZE_FLD_BIT_TOP+1)
885 
            = C_ALL_ZEROS(C_DBUS_WIDTH-1-32 downto C_MAXSIZE_FLD_BIT_TOP+1)
886 
            then
887 
            Regs_WrDin_Hi19b_True_lq_r2  <= '0';
888 
         else
889 
            Regs_WrDin_Hi19b_True_lq_r2  <= '1';
890 
         end if;
891 
 
892 
         if Regs_WrDin_r1(C_MAXSIZE_FLD_BIT_BOT-1 downto 2)
893 
            = C_ALL_ZEROS(C_MAXSIZE_FLD_BIT_BOT-1 downto 2)
894 
            then                               -- ! Lowest 2 bits ignored !
895 
            Regs_WrDin_Lo7b_True_lq_r2  <= '0';
896 
         else
897 
            Regs_WrDin_Lo7b_True_lq_r2  <= '1';
898 
         end if;
899 
 
900 
      end if;
901 
   end process;
902 
 
903 
 
904 
 
905 
-- ---------------------------------------
906 
--
907 
   Write_DMA_Registers_Mux:
908 
   process ( trn_clk, trn_lnk_up_n)
909 
   begin
910 
      if trn_lnk_up_n = '1' then
911 
         Reg_WrMuxer_Hi <= (Others => '0');
912 
         Reg_WrMuxer_Lo <= (Others => '0');
913 
 
914 
      elsif trn_clk'event and trn_clk = '1' then
915 
 
916 
         if -- Regs_WrAddr_r1(C_DECODE_BIT_TOP downto C_DECODE_BIT_BOT)=C_REGS_BASE_ADDR(C_DECODE_BIT_TOP downto C_DECODE_BIT_BOT)
917 
            -- and
918 
            Regs_WrAddr_r1(C_DECODE_BIT_BOT-1 downto 2)=CONV_STD_LOGIC_VECTOR(0, C_DECODE_BIT_BOT-2)
919 
            -- and Regs_WrAddr_r1(2-1 downto 0)="00"
920 
            then
921 
            Reg_WrMuxer_Hi(0)   <= not Regs_WrMask_r1(1);
922 
         else
923 
            Reg_WrMuxer_Hi(0)   <= '0';
924 
         end if;
925 
 
926 
         FOR k IN 1 TO C_NUM_OF_ADDRESSES-1 LOOP
927 
 
928 
            if -- Regs_WrAddr_r1(C_DECODE_BIT_TOP downto C_DECODE_BIT_BOT)=C_REGS_BASE_ADDR(C_DECODE_BIT_TOP downto C_DECODE_BIT_BOT)
929 
               -- and
930 
               Regs_WrAddr_r1(C_DECODE_BIT_BOT-1 downto 2)=CONV_STD_LOGIC_VECTOR(k, C_DECODE_BIT_BOT-2)
931 
               -- and Regs_WrAddr_r1(2-1 downto 0)="00"
932 
               then
933 
               Reg_WrMuxer_Hi(k)   <= not Regs_WrMask_r1(1);
934 
            else
935 
               Reg_WrMuxer_Hi(k)   <= '0';
936 
            end if;
937 
 
938 
            if -- Regs_WrAddr_r1(C_DECODE_BIT_TOP downto C_DECODE_BIT_BOT)=C_REGS_BASE_ADDR(C_DECODE_BIT_TOP downto C_DECODE_BIT_BOT)
939 
               -- and
940 
               Regs_WrAddr_r1(C_DECODE_BIT_BOT-1 downto 2)=CONV_STD_LOGIC_VECTOR(k-1, C_DECODE_BIT_BOT-2)
941 
               -- and Regs_WrAddr_r1(2-1 downto 0)="00"
942 
               then
943 
               Reg_WrMuxer_Lo(k)   <= not Regs_WrMask_r1(0);
944 
            else
945 
               Reg_WrMuxer_Lo(k)   <= '0';
946 
            end if;
947 
 
948 
         END LOOP;
949 
 
950 
      end if;
951 
   end process;
952 
 
953 
 
954 
 
955 
--  -----------------------------------------------
956 
--  System Interrupt Status Control
957 
--  -----------------------------------------------
958 
 
959 
-- -------------------------------------------------------
960 
-- Synchronous Registered: Sys_Int_Enable_i
961 
   SysReg_Sys_Int_Enable:
962 
   process ( trn_clk, trn_lnk_up_n)
963 
   begin
964 
      if trn_lnk_up_n = '1' then
965 
         Sys_Int_Enable_i     <= (OTHERS => '0');
966 
      elsif trn_clk'event and trn_clk = '1' then
967 
 
968 
        if Regs_WrEn_r2='1'
969 
                    and Reg_WrMuxer_Hi(CINT_ADDR_IRQ_EN)='1'
970 
                         then
971 
            Sys_Int_Enable_i(32-1 downto 0) <=  Regs_WrDin_r2(64-1 downto 32);
972 
        elsif Regs_WrEn_r2='1'
973 
                    and Reg_WrMuxer_Lo(CINT_ADDR_IRQ_EN)='1'
974 
                         then
975 
            Sys_Int_Enable_i(32-1 downto 0) <=  Regs_WrDin_r2(32-1 downto 0);
976 
        else
977 
            Sys_Int_Enable_i <=  Sys_Int_Enable_i;
978 
        end if;
979 
 
980 
      end if;
981 
   end process;
982 
 
983 
 
984 
--  -----------------------------------------------
985 
--    System General Control Register
986 
--  -----------------------------------------------
987 
-- -----------------------------------------------
988 
-- Synchronous Registered: General_Control
989 
   SysReg_General_Control:
990 
   process ( trn_clk, trn_lnk_up_n)
991 
   begin
992 
      if trn_lnk_up_n = '1' then
993 
         General_Control_i     <= (OTHERS => '0');
994 
         General_Control_i(C_GCR_MSG_ROUT_BIT_TOP downto C_GCR_MSG_ROUT_BIT_BOT)
995 
                               <= C_TYPE_OF_MSG(C_TLP_TYPE_BIT_BOT+C_GCR_MSG_ROUT_BIT_TOP-C_GCR_MSG_ROUT_BIT_BOT
996 
                                  downto C_TLP_TYPE_BIT_BOT);
997 
 
998 
      elsif trn_clk'event and trn_clk = '1' then
999 
 
1000 
        if Regs_WrEn_r2='1'
1001 
           and Reg_WrMuxer_Hi(CINT_ADDR_CONTROL)='1'
1002 
           then
1003 
            General_Control_i(32-1 downto 0)  <=  Regs_WrDin_r2(64-1 downto 32);
1004 
        elsif Regs_WrEn_r2='1'
1005 
           and Reg_WrMuxer_Lo(CINT_ADDR_CONTROL)='1'
1006 
           then
1007 
            General_Control_i(32-1 downto 0)  <=  Regs_WrDin_r2(32-1 downto 0);
1008 
        else
1009 
            General_Control_i  <=  General_Control_i;
1010 
        end if;
1011 
 
1012 
      end if;
1013 
   end process;
1014 
 
1015 
-- -----------------------------------------------
1016 
-- Synchronous Registered: DG_Reset_i
1017 
   SysReg_DGen_Reset:
1018 
   process ( trn_clk, trn_lnk_up_n)
1019 
   begin
1020 
      if trn_lnk_up_n = '1' then
1021 
         DG_Reset_i            <= '1';
1022 
         DG_Rst_Counter        <= (OTHERS=>'0');
1023 
 
1024 
      elsif trn_clk'event and trn_clk = '1' then
1025 
 
1026 
        if DG_Rst_Counter=X"FF" then
1027 
           DG_Rst_Counter  <= DG_Rst_Counter;
1028 
        else
1029 
           DG_Rst_Counter  <= DG_Rst_Counter + '1';
1030 
        end if;
1031 
 
1032 
        if DG_Rst_Counter(7)='0' then
1033 
            DG_Reset_i         <=  '1';
1034 
        elsif Regs_WrEn_r2='1'
1035 
                    and Reg_WrMuxer_Hi(CINT_ADDR_DG_CTRL)='1'
1036 
                         then
1037 
            DG_Reset_i         <=  Command_is_Reset_Hi;
1038 
        elsif Regs_WrEn_r2='1'
1039 
                    and Reg_WrMuxer_Lo(CINT_ADDR_DG_CTRL)='1'
1040 
                         then
1041 
            DG_Reset_i         <=  Command_is_Reset_Lo;
1042 
        else
1043 
            DG_Reset_i         <=  '0';
1044 
        end if;
1045 
 
1046 
      end if;
1047 
   end process;
1048 
 
1049 
-- -----------------------------------------------
1050 
-- Synchronous Registered: DG_Mask_i
1051 
   SysReg_DGen_Mask:
1052 
   process ( trn_clk, trn_lnk_up_n)
1053 
   begin
1054 
      if trn_lnk_up_n = '1' then
1055 
         DG_Mask_i     <= '0';
1056 
      elsif trn_clk'event and trn_clk = '1' then
1057 
 
1058 
        if Regs_WrEn_r2='1'
1059 
           and Reg_WrMuxer_Hi(CINT_ADDR_DG_CTRL)='1'
1060 
           then
1061 
           DG_Mask_i  <=  Regs_WrDin_r2(32+CINT_BIT_DG_MASK);
1062 
        elsif Regs_WrEn_r2='1'
1063 
           and Reg_WrMuxer_Lo(CINT_ADDR_DG_CTRL)='1'
1064 
           then
1065 
           DG_Mask_i  <=  Regs_WrDin_r2(CINT_BIT_DG_MASK);
1066 
        else
1067 
           DG_Mask_i  <=  DG_Mask_i;
1068 
        end if;
1069 
 
1070 
      end if;
1071 
   end process;
1072 
 
1073 
--------------------------------------------------------------------------
1074 
--  Data generator status
1075 
--
1076 
   Synch_DG_Status_i:
1077 
   process ( trn_clk, DG_Reset_i )
1078 
   begin
1079 
     if DG_Reset_i = '1' then
1080 
        DG_Status_i    <= (OTHERS=>'0');
1081 
     elsif trn_clk'event and trn_clk = '1' then
1082 
        DG_Status_i(CINT_BIT_DG_MASK)    <= DG_Mask_i;
1083 
        DG_Status_i(CINT_BIT_DG_BUSY)    <= DG_is_Running;
1084 
     end if;
1085 
   end process;
1086 
 
1087 
-- -----------------------------------------------
1088 
-- Synchronous Registered: IG_Control_i
1089 
   SysReg_IntGen_Control:
1090 
   process ( trn_clk, trn_lnk_up_n)
1091 
   begin
1092 
      if trn_lnk_up_n = '1' then
1093 
         IG_Control_i          <= (OTHERS => '0');
1094 
         IG_Reset_i            <= '1';
1095 
         IG_Host_Clear_i       <= '0';
1096 
 
1097 
      elsif trn_clk'event and trn_clk = '1' then
1098 
 
1099 
        if Regs_WrEn_r2='1'
1100 
                    and Reg_WrMuxer_Hi(CINT_ADDR_IG_CONTROL)='1'
1101 
                         then
1102 
            IG_Control_i(32-1 downto 0)       <=  Regs_WrDin_r2(64-1 downto 32);
1103 
            IG_Reset_i         <=  Command_is_Reset_Hi;
1104 
            IG_Host_Clear_i    <=  Command_is_Host_iClr_Hi;
1105 
        elsif Regs_WrEn_r2='1'
1106 
                    and Reg_WrMuxer_Lo(CINT_ADDR_IG_CONTROL)='1'
1107 
                         then
1108 
            IG_Control_i(32-1 downto 0)       <=  Regs_WrDin_r2(32-1 downto 0);
1109 
            IG_Reset_i         <=  Command_is_Reset_Lo;
1110 
            IG_Host_Clear_i    <=  Command_is_Host_iClr_Lo;
1111 
        else
1112 
            IG_Control_i       <=  IG_Control_i;
1113 
            IG_Reset_i         <=  '0';
1114 
            IG_Host_Clear_i    <=  '0';
1115 
        end if;
1116 
 
1117 
      end if;
1118 
   end process;
1119 
 
1120 
 
1121 
-- -----------------------------------------------
1122 
-- Synchronous Registered: IG_Latency_i
1123 
   SysReg_IntGen_Latency:
1124 
   process ( trn_clk, trn_lnk_up_n)
1125 
   begin
1126 
      if trn_lnk_up_n = '1' then
1127 
         IG_Latency_i       <= (OTHERS => '0');
1128 
 
1129 
      elsif trn_clk'event and trn_clk = '1' then
1130 
 
1131 
        if IG_Reset_i='1' then
1132 
            IG_Latency_i    <=  (OTHERS => '0');
1133 
        elsif Regs_WrEn_r2='1'
1134 
                    and Reg_WrMuxer_Hi(CINT_ADDR_IG_LATENCY)='1'
1135 
                         then
1136 
            IG_Latency_i(32-1 downto 0)    <=  Regs_WrDin_r2(64-1 downto 32);
1137 
        elsif Regs_WrEn_r2='1'
1138 
                    and Reg_WrMuxer_Lo(CINT_ADDR_IG_LATENCY)='1'
1139 
                         then
1140 
            IG_Latency_i(32-1 downto 0)    <=  Regs_WrDin_r2(32-1 downto 0);
1141 
        else
1142 
            IG_Latency_i    <=  IG_Latency_i;
1143 
        end if;
1144 
 
1145 
      end if;
1146 
   end process;
1147 
 
1148 
 
1149 
 
1150 
 
1151 
--  ------------------------------------------------------
1152 
--      Protocol CTL interface
1153 
--  ------------------------------------------------------
1154 
 
1155 
-- -------------------------------------------------------
1156 
-- Synchronous Registered: ctl_rd
1157 
   Syn_CTL_rd:
1158 
   process ( trn_clk, trn_lnk_up_n)
1159 
   begin
1160 
      if trn_lnk_up_n = '1' then
1161 
         ctl_rd_i     <= (OTHERS => '0');
1162 
         ctl_rv_i     <= '0';
1163 
      elsif trn_clk'event and trn_clk = '1' then
1164 
 
1165 
         if Regs_WrEn_r2='1' and Reg_WrMuxer_Hi(CINT_ADDR_CTL_CLASS)='1' then
1166 
            ctl_rd_i     <= Regs_WrDin_r2(C_DBUS_WIDTH-1 downto 32);
1167 
            ctl_rv_i     <= '1';
1168 
         elsif Regs_WrEn_r2='1' and Reg_WrMuxer_Lo(CINT_ADDR_CTL_CLASS)='1' then
1169 
            ctl_rd_i     <= Regs_WrDin_r2(32-1 downto 0);
1170 
            ctl_rv_i     <= '1';
1171 
         else
1172 
            ctl_rd_i     <= ctl_rd_i;
1173 
            ctl_rv_i     <= '0';
1174 
         end if;
1175 
 
1176 
      end if;
1177 
   end process;
1178 
 
1179 
 
1180 
-- -----------------------------------------------
1181 
-- Synchronous Registered: ctl_reset
1182 
   SysReg_ctl_reset:
1183 
   process ( trn_clk, trn_lnk_up_n)
1184 
   begin
1185 
      if trn_lnk_up_n = '1' then
1186 
         ctl_reset_i            <= '1';
1187 
 
1188 
      elsif trn_clk'event and trn_clk = '1' then
1189 
 
1190 
        if Regs_WrEn_r2='1'
1191 
                    and Reg_WrMuxer_Hi(CINT_ADDR_TC_STATUS)='1'
1192 
                         then
1193 
            ctl_reset_i         <=  Command_is_Reset_Hi;
1194 
        elsif Regs_WrEn_r2='1'
1195 
                    and Reg_WrMuxer_Lo(CINT_ADDR_TC_STATUS)='1'
1196 
                         then
1197 
            ctl_reset_i         <=  Command_is_Reset_Lo;
1198 
        else
1199 
            ctl_reset_i         <=  '0';
1200 
        end if;
1201 
 
1202 
      end if;
1203 
   end process;
1204 
 
1205 
 
1206 
 
1207 
-- -------------------------------------------------------
1208 
-- Synchronous Registered: ctl_td
1209 
--    ++++++++++++ INT triggering  ++++++++++++++++++
1210 
   Syn_CTL_td:
1211 
   process ( trn_clk, trn_lnk_up_n)
1212 
   begin
1213 
      if trn_lnk_up_n = '1' then
1214 
         ctl_td_r     <= (OTHERS => '0');
1215 
      elsif trn_clk'event and trn_clk = '1' then
1216 
 
1217 
         if ctl_tv='1' then
1218 
            ctl_td_r     <= ctl_td;
1219 
         else
1220 
            ctl_td_r     <= ctl_td_r;
1221 
         end if;
1222 
 
1223 
      end if;
1224 
   end process;
1225 
 
1226 
 
1227 
 
1228 
--  ------------------------------------------------------
1229 
--      Protocol DLM interface
1230 
--  ------------------------------------------------------
1231 
 
1232 
-- -------------------------------------------------------
1233 
-- Synchronous Registered: dlm_td
1234 
   Syn_DLM_td:
1235 
   process ( trn_clk, trn_lnk_up_n)
1236 
   begin
1237 
      if trn_lnk_up_n = '1' then
1238 
         dlm_td_i     <= (OTHERS => '0');
1239 
         dlm_tv_i     <= '0';
1240 
      elsif trn_clk'event and trn_clk = '1' then
1241 
 
1242 
         if Regs_WrEn_r2='1' and Reg_WrMuxer_Hi(CINT_ADDR_DLM_CLASS)='1' then
1243 
            dlm_td_i     <= Regs_WrDin_r2(C_DBUS_WIDTH-1 downto 32);
1244 
            dlm_tv_i     <= '1';
1245 
         elsif Regs_WrEn_r2='1' and Reg_WrMuxer_Lo(CINT_ADDR_DLM_CLASS)='1' then
1246 
            dlm_td_i     <= Regs_WrDin_r2(32-1 downto 0);
1247 
            dlm_tv_i     <= '1';
1248 
         else
1249 
            dlm_td_i     <= dlm_td_i;
1250 
            dlm_tv_i     <= '0';
1251 
         end if;
1252 
 
1253 
      end if;
1254 
   end process;
1255 
 
1256 
 
1257 
-- -------------------------------------------------------
1258 
-- Synchronous Registered: dlm_rd
1259 
--    ++++++++++++ INT triggering  ++++++++++++++++++
1260 
   Syn_DLM_rd:
1261 
   process ( trn_clk, trn_lnk_up_n)
1262 
   begin
1263 
      if trn_lnk_up_n = '1' then
1264 
         dlm_rd_r     <= (OTHERS => '0');
1265 
      elsif trn_clk'event and trn_clk = '1' then
1266 
 
1267 
         if dlm_rv='1' then
1268 
            dlm_rd_r     <= dlm_rd;
1269 
         else
1270 
            dlm_rd_r     <= dlm_rd_r;
1271 
         end if;
1272 
 
1273 
      end if;
1274 
   end process;
1275 
 
1276 
 
1277 
--  ------------------------------------------------------
1278 
--  DMA Upstream Registers
1279 
--  ------------------------------------------------------
1280 
 
1281 
-- -------------------------------------------------------
1282 
-- Synchronous Registered: DMA_us_PA_i
1283 
   RxTrn_DMA_us_PA:
1284 
   process ( trn_clk, trn_lnk_up_n)
1285 
   begin
1286 
      if trn_lnk_up_n = '1' then
1287 
         DMA_us_PA_i  <= (OTHERS => '0');
1288 
      elsif trn_clk'event and trn_clk = '1' then
1289 
 
1290 
        if usDMA_Channel_Rst_i = '1' then
1291 
            DMA_us_PA_i <= (OTHERS => '0');
1292 
        else
1293 
 
1294 
          if Regs_WrEn_r2='1' and Reg_WrMuxer_Hi(CINT_ADDR_DMA_US_PAH)='1' then
1295 
            DMA_us_PA_i(C_DBUS_WIDTH-1 downto 32)  <= Regs_WrDin_r2(64-1 downto 32);
1296 
          elsif Regs_WrEn_r2='1' and Reg_WrMuxer_Lo(CINT_ADDR_DMA_US_PAH)='1' then
1297 
            DMA_us_PA_i(C_DBUS_WIDTH-1 downto 32)  <= Regs_WrDin_r2(32-1 downto 0);
1298 
          else
1299 
            DMA_us_PA_i(C_DBUS_WIDTH-1 downto 32)  <= DMA_us_PA_i(C_DBUS_WIDTH-1 downto 32);
1300 
          end if;
1301 
 
1302 
          if Regs_WrEn_r2='1' and Reg_WrMuxer_Hi(CINT_ADDR_DMA_US_PAL)='1' then
1303 
            DMA_us_PA_i(32-1 downto 0)  <= Regs_WrDin_r2(64-1 downto 32);
1304 
          elsif Regs_WrEn_r2='1' and Reg_WrMuxer_Lo(CINT_ADDR_DMA_US_PAL)='1' then
1305 
            DMA_us_PA_i(32-1 downto 0)  <= Regs_WrDin_r2(32-1 downto 0);
1306 
          else
1307 
            DMA_us_PA_i(32-1 downto 0)  <= DMA_us_PA_i(32-1 downto 0);
1308 
          end if;
1309 
 
1310 
        end if;
1311 
 
1312 
      end if;
1313 
   end process;
1314 
 
1315 
 
1316 
-- -------------------------------------------------------
1317 
-- Synchronous Registered: DMA_us_HA_i
1318 
   RxTrn_DMA_us_HA:
1319 
   process ( trn_clk, trn_lnk_up_n)
1320 
   begin
1321 
      if trn_lnk_up_n = '1' then
1322 
         DMA_us_HA_i     <= (OTHERS => '1');
1323 
         usHA_is_64b_i   <= '0';
1324 
 
1325 
      elsif trn_clk'event and trn_clk = '1' then
1326 
 
1327 
        if usDMA_Channel_Rst_i = '1' then
1328 
            DMA_us_HA_i <= (OTHERS => '1');
1329 
            usHA_is_64b_i <= '0';
1330 
        else
1331 
 
1332 
          if Regs_WrEn_r2='1' and Reg_WrMuxer_Hi(CINT_ADDR_DMA_US_HAH)='1' then
1333 
            DMA_us_HA_i(C_DBUS_WIDTH-1 downto 32)  <= Regs_WrDin_r2(64-1 downto 32);
1334 
            usHA_is_64b_i   <=  WrDin_r2_not_Zero_Hi;
1335 
          elsif Regs_WrEn_r2='1' and Reg_WrMuxer_Lo(CINT_ADDR_DMA_US_HAH)='1' then
1336 
            DMA_us_HA_i(C_DBUS_WIDTH-1 downto 32)  <= Regs_WrDin_r2(32-1 downto 0);
1337 
            usHA_is_64b_i   <=  WrDin_r2_not_Zero_Lo;
1338 
          else
1339 
            DMA_us_HA_i(C_DBUS_WIDTH-1 downto 32)  <= DMA_us_HA_i(C_DBUS_WIDTH-1 downto 32);
1340 
            usHA_is_64b_i   <=  usHA_is_64b_i;
1341 
          end if;
1342 
 
1343 
          if Regs_WrEn_r2='1' and Reg_WrMuxer_Hi(CINT_ADDR_DMA_US_HAL)='1' then
1344 
            DMA_us_HA_i(32-1 downto 0)  <= Regs_WrDin_r2(64-1 downto 32);
1345 
          elsif Regs_WrEn_r2='1' and Reg_WrMuxer_Lo(CINT_ADDR_DMA_US_HAL)='1' then
1346 
            DMA_us_HA_i(32-1 downto 0)  <= Regs_WrDin_r2(32-1 downto 0);
1347 
          else
1348 
            DMA_us_HA_i(32-1 downto 0)  <= DMA_us_HA_i(32-1 downto 0);
1349 
          end if;
1350 
 
1351 
        end if;
1352 
 
1353 
      end if;
1354 
   end process;
1355 
 
1356 
 
1357 
-- -------------------------------------------------------
1358 
-- Synchronous output: DMA_us_BDA_i
1359 
   Syn_Output_DMA_us_BDA:
1360 
   process ( trn_clk, trn_lnk_up_n)
1361 
   begin
1362 
      if trn_lnk_up_n = '1' then
1363 
         DMA_us_BDA_i    <= (OTHERS =>'0');
1364 
         usBDA_is_64b_i  <= '0';
1365 
      elsif trn_clk'event and trn_clk = '1' then
1366 
 
1367 
        if usDMA_Channel_Rst_i = '1' then
1368 
           DMA_us_BDA_i <= (OTHERS => '0');
1369 
           usBDA_is_64b_i <= '0';
1370 
        else
1371 
 
1372 
          if Regs_WrEn_r2='1' and Reg_WrMuxer_Hi(CINT_ADDR_DMA_US_BDAH)='1' then
1373 
            DMA_us_BDA_i(C_DBUS_WIDTH-1 downto 32)  <= Regs_WrDin_r2(C_DBUS_WIDTH-1 downto 32);
1374 
            usBDA_is_64b_i   <=  WrDin_r2_not_Zero_Hi;
1375 
          elsif Regs_WrEn_r2='1' and Reg_WrMuxer_Lo(CINT_ADDR_DMA_US_BDAH)='1' then
1376 
            DMA_us_BDA_i(C_DBUS_WIDTH-1 downto 32)  <= Regs_WrDin_r2(32-1 downto 0);
1377 
            usBDA_is_64b_i   <=  WrDin_r2_not_Zero_Lo;
1378 
          else
1379 
            DMA_us_BDA_i(C_DBUS_WIDTH-1 downto 32)  <= DMA_us_BDA_i(C_DBUS_WIDTH-1 downto 32);
1380 
            usBDA_is_64b_i   <=  usBDA_is_64b_i;
1381 
          end if;
1382 
 
1383 
          if Regs_WrEn_r2='1' and Reg_WrMuxer_Hi(CINT_ADDR_DMA_US_BDAL)='1' then
1384 
            DMA_us_BDA_i(32-1 downto 0)  <= Regs_WrDin_r2(C_DBUS_WIDTH-1 downto 32);
1385 
          elsif Regs_WrEn_r2='1' and Reg_WrMuxer_Lo(CINT_ADDR_DMA_US_BDAL)='1' then
1386 
            DMA_us_BDA_i(32-1 downto 0)  <= Regs_WrDin_r2(32-1 downto 0);
1387 
          else
1388 
            DMA_us_BDA_i(32-1 downto 0)  <= DMA_us_BDA_i(32-1 downto 0);
1389 
          end if;
1390 
 
1391 
        end if;
1392 
 
1393 
      end if;
1394 
   end process;
1395 
 
1396 
 
1397 
 
1398 
-- -------------------------------------------------------
1399 
-- Synchronous Registered: DMA_us_Length_i
1400 
   RxTrn_DMA_us_Length:
1401 
   process ( trn_clk, trn_lnk_up_n)
1402 
   begin
1403 
      if trn_lnk_up_n = '1' then
1404 
         DMA_us_Length_i     <= (OTHERS => '0');
1405 
         usLeng_Hi19b_True_i <= '0';
1406 
         usLeng_Lo7b_True_i  <= '0';
1407 
      elsif trn_clk'event and trn_clk = '1' then
1408 
 
1409 
         if usDMA_Channel_Rst_i = '1' then
1410 
            DMA_us_Length_i     <= (OTHERS => '0');
1411 
            usLeng_Hi19b_True_i <= '0';
1412 
            usLeng_Lo7b_True_i  <= '0';
1413 
 
1414 
         elsif Regs_WrEn_r2='1' and  Reg_WrMuxer_Hi(CINT_ADDR_DMA_US_LENG)='1' then
1415 
            DMA_us_Length_i(32-1 downto 0)     <= Regs_WrDin_r2(64-1 downto 32);
1416 
            usLeng_Hi19b_True_i <= Regs_WrDin_Hi19b_True_hq_r2;
1417 
            usLeng_Lo7b_True_i  <= Regs_WrDin_Lo7b_True_hq_r2;
1418 
         elsif Regs_WrEn_r2='1' and  Reg_WrMuxer_Lo(CINT_ADDR_DMA_US_LENG)='1' then
1419 
            DMA_us_Length_i(32-1 downto 0)     <= Regs_WrDin_r2(32-1 downto 0);
1420 
            usLeng_Hi19b_True_i <= Regs_WrDin_Hi19b_True_lq_r2;
1421 
            usLeng_Lo7b_True_i  <= Regs_WrDin_Lo7b_True_lq_r2;
1422 
         else
1423 
            DMA_us_Length_i     <= DMA_us_Length_i;
1424 
            usLeng_Hi19b_True_i <= usLeng_Hi19b_True_i;
1425 
            usLeng_Lo7b_True_i  <= usLeng_Lo7b_True_i;
1426 
 
1427 
         end if;
1428 
 
1429 
      end if;
1430 
   end process;
1431 
 
1432 
 
1433 
 
1434 
-- -------------------------------------------------------
1435 
-- Synchronous us_Param_Modified
1436 
   SynReg_us_Param_Modified:
1437 
   process ( trn_clk, trn_lnk_up_n)
1438 
   begin
1439 
      if trn_lnk_up_n = '1' then
1440 
         us_Param_Modified     <= '0';
1441 
 
1442 
      elsif trn_clk'event and trn_clk = '1' then
1443 
 
1444 
        if usDMA_Channel_Rst_i = '1'
1445 
           or usDMA_Start_i = '1'
1446 
           or usDMA_Start2_i = '1'
1447 
           then
1448 
             us_Param_Modified     <= '0';
1449 
        elsif Regs_WrEn_r2='1' and
1450 
                (
1451 
                    Reg_WrMuxer_Hi(CINT_ADDR_DMA_US_PAL) ='1'
1452 
                 or Reg_WrMuxer_Lo(CINT_ADDR_DMA_US_PAL) ='1'
1453 
                 or Reg_WrMuxer_Hi(CINT_ADDR_DMA_US_HAH) ='1'
1454 
                 or Reg_WrMuxer_Lo(CINT_ADDR_DMA_US_HAH) ='1'
1455 
                 or Reg_WrMuxer_Hi(CINT_ADDR_DMA_US_HAL) ='1'
1456 
                 or Reg_WrMuxer_Lo(CINT_ADDR_DMA_US_HAL) ='1'
1457 
                 or Reg_WrMuxer_Hi(CINT_ADDR_DMA_US_BDAH)='1'
1458 
                 or Reg_WrMuxer_Lo(CINT_ADDR_DMA_US_BDAH)='1'
1459 
                 or Reg_WrMuxer_Hi(CINT_ADDR_DMA_US_BDAL)='1'
1460 
                 or Reg_WrMuxer_Lo(CINT_ADDR_DMA_US_BDAL)='1'
1461 
                 or Reg_WrMuxer_Hi(CINT_ADDR_DMA_US_LENG)='1'
1462 
                 or Reg_WrMuxer_Lo(CINT_ADDR_DMA_US_LENG)='1'
1463 
                )
1464 
           then
1465 
             us_Param_Modified     <= '1';
1466 
        else
1467 
             us_Param_Modified     <= us_Param_Modified;
1468 
 
1469 
        end if;
1470 
 
1471 
      end if;
1472 
   end process;
1473 
 
1474 
 
1475 
 
1476 
-- -------------------------------------------------------
1477 
-- Synchronous output: DMA_us_Control_i
1478 
   Syn_Output_DMA_us_Control:
1479 
   process ( trn_clk, trn_lnk_up_n)
1480 
   begin
1481 
      if trn_lnk_up_n = '1' then
1482 
         DMA_us_Control_i <= (OTHERS =>'0');
1483 
      elsif trn_clk'event and trn_clk = '1' then
1484 
 
1485 
         if     Regs_Wr_dma_V_nE_Hi_r2='1'
1486 
            and Reg_WrMuxer_Hi(CINT_ADDR_DMA_US_CTRL)='1'
1487 
--            and Regs_WrDin_r2(CINT_BIT_DMA_CTRL_VALID)='1'
1488 
--            and Regs_WrDin_r2(CINT_BIT_DMA_CTRL_END)='0'
1489 
            and us_Param_Modified='1'
1490 
            and usDMA_Stop_i='0'
1491 
            then
1492 
               DMA_us_Control_i(32-1 downto 0) <= Regs_WrDin_r2(C_DBUS_WIDTH-1 downto 8+32)& X"00";
1493 
         elsif Regs_Wr_dma_V_nE_Lo_r2='1'
1494 
            and Reg_WrMuxer_Lo(CINT_ADDR_DMA_US_CTRL)='1'
1495 
--            and Regs_WrDin_r2(CINT_BIT_DMA_CTRL_VALID)='1'
1496 
--            and Regs_WrDin_r2(CINT_BIT_DMA_CTRL_END)='0'
1497 
            and us_Param_Modified='1'
1498 
            and usDMA_Stop_i='0'
1499 
            then
1500 
               DMA_us_Control_i(32-1 downto 0) <= Regs_WrDin_r2(32-1 downto 8)& X"00";
1501 
         elsif  Regs_Wr_dma_nV_Hi_r2='1'
1502 
            and Reg_WrMuxer_Hi(CINT_ADDR_DMA_US_CTRL)='1'
1503 
--            and Regs_WrDin_r2(CINT_BIT_DMA_CTRL_VALID)='0'
1504 
            then
1505 
               DMA_us_Control_i(32-1 downto 0) <= Last_Ctrl_Word_us(32-1 downto 0);
1506 
         elsif  Regs_Wr_dma_nV_Lo_r2='1'
1507 
            and Reg_WrMuxer_Lo(CINT_ADDR_DMA_US_CTRL)='1'
1508 
--            and Regs_WrDin_r2(CINT_BIT_DMA_CTRL_VALID)='0'
1509 
            then
1510 
               DMA_us_Control_i(32-1 downto 0) <= Last_Ctrl_Word_us(32-1 downto 0);
1511 
         else
1512 
            DMA_us_Control_i  <= DMA_us_Control_i;
1513 
         end if;
1514 
 
1515 
      end if;
1516 
   end process;
1517 
 
1518 
 
1519 
-- -------------------------------------------------------
1520 
-- Synchronous Register: Last_Ctrl_Word_us
1521 
   Hold_Last_Ctrl_Word_us:
1522 
   process ( trn_clk, trn_lnk_up_n)
1523 
   begin
1524 
      if trn_lnk_up_n = '1' then
1525 
         Last_Ctrl_Word_us  <= C_DEF_DMA_CTRL_WORD;
1526 
      elsif trn_clk'event and trn_clk = '1' then
1527 
 
1528 
        if usDMA_Channel_Rst_i = '1' then
1529 
            Last_Ctrl_Word_us <= C_DEF_DMA_CTRL_WORD;
1530 
        elsif Regs_Wr_dma_V_nE_Hi_r2='1'
1531 
          and Reg_WrMuxer_Hi(CINT_ADDR_DMA_US_CTRL)='1'
1532 
--          and Regs_WrDin_r2(CINT_BIT_DMA_CTRL_VALID)='1'
1533 
--          and Regs_WrDin_r2(CINT_BIT_DMA_CTRL_END)='0'
1534 
          and us_Param_Modified='1'
1535 
          and usDMA_Stop_i='0'
1536 
          then
1537 
            Last_Ctrl_Word_us(32-1 downto 0) <= Regs_WrDin_r2(C_DBUS_WIDTH-1 downto 8+32) & X"00";
1538 
        elsif Regs_Wr_dma_V_nE_Lo_r2='1'
1539 
          and Reg_WrMuxer_Lo(CINT_ADDR_DMA_US_CTRL)='1'
1540 
--          and Regs_WrDin_r2(CINT_BIT_DMA_CTRL_VALID)='1'
1541 
--          and Regs_WrDin_r2(CINT_BIT_DMA_CTRL_END)='0'
1542 
          and us_Param_Modified='1'
1543 
          and usDMA_Stop_i='0'
1544 
          then
1545 
            Last_Ctrl_Word_us(32-1 downto 0) <= Regs_WrDin_r2(32-1 downto 8) & X"00";
1546 
        elsif Regs_Wr_dma_V_nE_Hi_r2='1'
1547 
          and Reg_WrMuxer_Hi(CINT_ADDR_DMA_US_CTRL)='1'
1548 
--          and Regs_WrDin_r2(CINT_BIT_DMA_CTRL_VALID)='1'
1549 
--          and Regs_WrDin_r2(CINT_BIT_DMA_CTRL_END)='0'
1550 
          and us_Param_Modified='1'
1551 
          and usDMA_Stop_i='0'
1552 
          then
1553 
            Last_Ctrl_Word_us(32-1 downto 0) <= Regs_WrDin_r2(C_DBUS_WIDTH-1 downto 8+32) & X"00";
1554 
        elsif Regs_Wr_dma_V_nE_Lo_r2='1'
1555 
          and Reg_WrMuxer_Lo(CINT_ADDR_DMA_US_CTRL)='1'
1556 
--          and Regs_WrDin_r2(CINT_BIT_DMA_CTRL_VALID)='1'
1557 
--          and Regs_WrDin_r2(CINT_BIT_DMA_CTRL_END)='0'
1558 
          and us_Param_Modified='1'
1559 
          and usDMA_Stop_i='0'
1560 
          then
1561 
            Last_Ctrl_Word_us(32-1 downto 0) <= Regs_WrDin_r2(32-1 downto 8) & X"00";
1562 
        else
1563 
            Last_Ctrl_Word_us <= Last_Ctrl_Word_us;
1564 
        end if;
1565 
 
1566 
      end if;
1567 
   end process;
1568 
 
1569 
 
1570 
-- -------------------------------------------------------
1571 
-- Synchronous output: DMA_us_Start_Stop
1572 
   Syn_Output_DMA_us_Start_Stop:
1573 
   process ( trn_clk, trn_lnk_up_n)
1574 
   begin
1575 
      if trn_lnk_up_n = '1' then
1576 
         usDMA_Start_i  <= '0';
1577 
         usDMA_Stop_i   <= '0';
1578 
      elsif trn_clk'event and trn_clk = '1' then
1579 
 
1580 
         if     Regs_WrEnA_r2='1'
1581 
            and Reg_WrMuxer_Hi(CINT_ADDR_DMA_US_CTRL)='1'
1582 
            and Regs_WrDin_r2(CINT_BIT_DMA_CTRL_VALID+32)='1'
1583 
            then
1584 
               usDMA_Start_i <= not Regs_WrDin_r2(CINT_BIT_DMA_CTRL_END+32)
1585 
                            and not usDMA_Stop_i
1586 
                            and not Command_is_Reset_Hi
1587 
                            and us_Param_Modified
1588 
                            ;
1589 
               usDMA_Stop_i  <= Regs_WrDin_r2(CINT_BIT_DMA_CTRL_END+32)
1590 
                            and not Command_is_Reset_Hi
1591 
                            ;
1592 
         elsif Regs_WrEnA_r2='1'
1593 
            and Reg_WrMuxer_Lo(CINT_ADDR_DMA_US_CTRL)='1'
1594 
            and Regs_WrDin_r2(CINT_BIT_DMA_CTRL_VALID)='1'
1595 
            then
1596 
               usDMA_Start_i <= not Regs_WrDin_r2(CINT_BIT_DMA_CTRL_END)
1597 
                            and not usDMA_Stop_i
1598 
                            and not Command_is_Reset_Lo
1599 
                            and us_Param_Modified
1600 
                            ;
1601 
               usDMA_Stop_i  <= Regs_WrDin_r2(CINT_BIT_DMA_CTRL_END)
1602 
                            and not Command_is_Reset_Lo
1603 
                            ;
1604 
         elsif  Regs_WrEnA_r2='1'
1605 
            and Reg_WrMuxer_Hi(CINT_ADDR_DMA_US_CTRL)='1'
1606 
            and Regs_WrDin_r2(CINT_BIT_DMA_CTRL_VALID)='0'
1607 
            then
1608 
               usDMA_Start_i <= not Last_Ctrl_Word_us(CINT_BIT_DMA_CTRL_END)
1609 
                            and us_Param_Modified;
1610 
               usDMA_Stop_i  <= Last_Ctrl_Word_us(CINT_BIT_DMA_CTRL_END);
1611 
         elsif  Regs_WrEnA_r2='1'
1612 
            and Reg_WrMuxer_Lo(CINT_ADDR_DMA_US_CTRL)='1'
1613 
            and Regs_WrDin_r2(CINT_BIT_DMA_CTRL_VALID)='0'
1614 
            then
1615 
               usDMA_Start_i <= not Last_Ctrl_Word_us(CINT_BIT_DMA_CTRL_END)
1616 
                            and us_Param_Modified;
1617 
               usDMA_Stop_i  <= Last_Ctrl_Word_us(CINT_BIT_DMA_CTRL_END);
1618 
         elsif usDMA_Cmd_Ack='1'
1619 
            then
1620 
               usDMA_Start_i <= '0';
1621 
               usDMA_Stop_i  <= usDMA_Stop_i;
1622 
         else
1623 
               usDMA_Start_i <= usDMA_Start_i;
1624 
               usDMA_Stop_i  <= usDMA_Stop_i;
1625 
         end if;
1626 
 
1627 
      end if;
1628 
   end process;
1629 
 
1630 
 
1631 
-- -------------------------------------------------------
1632 
-- Synchronous output: DMA_us_Start2_Stop2
1633 
   Syn_Output_DMA_us_Start2_Stop2:
1634 
   process ( trn_clk, trn_lnk_up_n)
1635 
   begin
1636 
      if trn_lnk_up_n = '1' then
1637 
         usDMA_Start2_i <= '0';
1638 
         usDMA_Stop2_i  <= '0';
1639 
      elsif trn_clk'event and trn_clk = '1' then
1640 
 
1641 
         if usDMA_Channel_Rst_i='1' then
1642 
               usDMA_Start2_i <= '0';
1643 
               usDMA_Stop2_i  <= '0';
1644 
         elsif     Regs_WrEnB_r2='1'
1645 
            and Reg_WrMuxer_Hi(CINT_ADDR_DMA_US_CTRL)='1'
1646 
            and Regs_WrDin_r2(CINT_BIT_DMA_CTRL_VALID+32)='1'
1647 
            then
1648 
               usDMA_Start2_i <= not Regs_WrDin_r2(CINT_BIT_DMA_CTRL_END+32) and not Command_is_Reset_Hi;
1649 
               usDMA_Stop2_i  <= Regs_WrDin_r2(CINT_BIT_DMA_CTRL_END+32) and not Command_is_Reset_Lo;
1650 
         elsif  Regs_WrEnB_r2='1'
1651 
            and Reg_WrMuxer_Lo(CINT_ADDR_DMA_US_CTRL)='1'
1652 
            and Regs_WrDin_r2(CINT_BIT_DMA_CTRL_VALID)='1'
1653 
            then
1654 
               usDMA_Start2_i <= not Regs_WrDin_r2(CINT_BIT_DMA_CTRL_END) and not Command_is_Reset_Lo;
1655 
               usDMA_Stop2_i  <= Regs_WrDin_r2(CINT_BIT_DMA_CTRL_END) and not Command_is_Reset_Lo;
1656 
         elsif  Regs_WrEnB_r2='1'
1657 
            and Reg_WrMuxer_Hi(CINT_ADDR_DMA_US_CTRL)='1'
1658 
            and Regs_WrDin_r2(CINT_BIT_DMA_CTRL_VALID+32)='0'
1659 
            then
1660 
               usDMA_Start2_i <= not Last_Ctrl_Word_us(CINT_BIT_DMA_CTRL_END);
1661 
               usDMA_Stop2_i  <= Last_Ctrl_Word_us(CINT_BIT_DMA_CTRL_END);
1662 
         elsif  Regs_WrEnB_r2='1'
1663 
            and Reg_WrMuxer_Lo(CINT_ADDR_DMA_US_CTRL)='1'
1664 
            and Regs_WrDin_r2(CINT_BIT_DMA_CTRL_VALID)='0'
1665 
            then
1666 
               usDMA_Start2_i <= not Last_Ctrl_Word_us(CINT_BIT_DMA_CTRL_END);
1667 
               usDMA_Stop2_i  <= Last_Ctrl_Word_us(CINT_BIT_DMA_CTRL_END);
1668 
         elsif usDMA_Cmd_Ack='1' then
1669 
               usDMA_Start2_i <= '0';
1670 
               usDMA_Stop2_i  <= usDMA_Stop2_i;
1671 
         else
1672 
               usDMA_Start2_i <= usDMA_Start2_i;
1673 
               usDMA_Stop2_i  <= usDMA_Stop2_i;
1674 
         end if;
1675 
 
1676 
      end if;
1677 
   end process;
1678 
 
1679 
 
1680 
--  ------------------------------------------------------
1681 
--  DMA Downstream Registers
1682 
--  ------------------------------------------------------
1683 
 
1684 
-- -------------------------------------------------------
1685 
-- Synchronous Registered: DMA_ds_PA_i
1686 
   RxTrn_DMA_ds_PA:
1687 
   process ( trn_clk, trn_lnk_up_n)
1688 
   begin
1689 
      if trn_lnk_up_n = '1' then
1690 
         DMA_ds_PA_i     <= (OTHERS => '0');
1691 
      elsif trn_clk'event and trn_clk = '1' then
1692 
 
1693 
        if dsDMA_Channel_Rst_i = '1' then
1694 
            DMA_ds_PA_i <= (OTHERS => '0');
1695 
        else
1696 
 
1697 
          if Regs_WrEn_r2='1' and Reg_WrMuxer_Hi(CINT_ADDR_DMA_DS_PAH)='1' then
1698 
            DMA_ds_PA_i(C_DBUS_WIDTH-1 downto 32)  <= Regs_WrDin_r2(C_DBUS_WIDTH-1 downto 32);
1699 
          elsif Regs_WrEn_r2='1' and Reg_WrMuxer_Lo(CINT_ADDR_DMA_DS_PAH)='1' then
1700 
            DMA_ds_PA_i(C_DBUS_WIDTH-1 downto 32)  <= Regs_WrDin_r2(32-1 downto 0);
1701 
          else
1702 
            DMA_ds_PA_i(C_DBUS_WIDTH-1 downto 32)  <= DMA_ds_PA_i(C_DBUS_WIDTH-1 downto 32);
1703 
          end if;
1704 
 
1705 
          if Regs_WrEn_r2='1' and Reg_WrMuxer_Hi(CINT_ADDR_DMA_DS_PAL)='1' then
1706 
            DMA_ds_PA_i(32-1 downto 0)  <= Regs_WrDin_r2(C_DBUS_WIDTH-1 downto 32);
1707 
          elsif Regs_WrEn_r2='1' and Reg_WrMuxer_Lo(CINT_ADDR_DMA_DS_PAL)='1' then
1708 
            DMA_ds_PA_i(32-1 downto 0)  <= Regs_WrDin_r2(32-1 downto 0);
1709 
          else
1710 
            DMA_ds_PA_i(32-1 downto 0)  <= DMA_ds_PA_i(32-1 downto 0);
1711 
          end if;
1712 
 
1713 
        end if;
1714 
 
1715 
      end if;
1716 
   end process;
1717 
 
1718 
 
1719 
-- -------------------------------------------------------
1720 
-- Synchronous Registered: DMA_ds_HA_i
1721 
   RxTrn_DMA_ds_HA:
1722 
   process ( trn_clk, trn_lnk_up_n)
1723 
   begin
1724 
      if trn_lnk_up_n = '1' then
1725 
         DMA_ds_HA_i     <= (OTHERS => '1');
1726 
         dsHA_is_64b_i   <= '0';
1727 
      elsif trn_clk'event and trn_clk = '1' then
1728 
 
1729 
        if dsDMA_Channel_Rst_i = '1' then
1730 
            DMA_ds_HA_i <= (OTHERS => '1');
1731 
            dsHA_is_64b_i <= '0';
1732 
        else
1733 
 
1734 
          if Regs_WrEn_r2='1' and Reg_WrMuxer_Hi(CINT_ADDR_DMA_DS_HAH)='1' then
1735 
            DMA_ds_HA_i(C_DBUS_WIDTH-1 downto 32)  <= Regs_WrDin_r2(C_DBUS_WIDTH-1 downto 32);
1736 
            dsHA_is_64b_i   <=  WrDin_r2_not_Zero_Hi;
1737 
          elsif Regs_WrEn_r2='1' and Reg_WrMuxer_Lo(CINT_ADDR_DMA_DS_HAH)='1' then
1738 
            DMA_ds_HA_i(C_DBUS_WIDTH-1 downto 32)  <= Regs_WrDin_r2(32-1 downto 0);
1739 
            dsHA_is_64b_i   <=  WrDin_r2_not_Zero_Lo;
1740 
          else
1741 
            DMA_ds_HA_i(C_DBUS_WIDTH-1 downto 32)  <= DMA_ds_HA_i(C_DBUS_WIDTH-1 downto 32);
1742 
            dsHA_is_64b_i   <=  dsHA_is_64b_i;
1743 
          end if;
1744 
 
1745 
          if Regs_WrEn_r2='1' and Reg_WrMuxer_Hi(CINT_ADDR_DMA_DS_HAL)='1' then
1746 
            DMA_ds_HA_i(32-1 downto 0)  <= Regs_WrDin_r2(C_DBUS_WIDTH-1 downto 32);
1747 
          elsif Regs_WrEn_r2='1' and Reg_WrMuxer_Lo(CINT_ADDR_DMA_DS_HAL)='1' then
1748 
            DMA_ds_HA_i(32-1 downto 0)  <= Regs_WrDin_r2(32-1 downto 0);
1749 
          else
1750 
            DMA_ds_HA_i(32-1 downto 0)  <= DMA_ds_HA_i(32-1 downto 0);
1751 
          end if;
1752 
 
1753 
        end if;
1754 
 
1755 
      end if;
1756 
   end process;
1757 
 
1758 
 
1759 
-- -------------------------------------------------------
1760 
-- Synchronous output: DMA_ds_BDA_i
1761 
   Syn_Output_DMA_ds_BDA:
1762 
   process ( trn_clk, trn_lnk_up_n)
1763 
   begin
1764 
      if trn_lnk_up_n = '1' then
1765 
         DMA_ds_BDA_i    <= (OTHERS =>'0');
1766 
         dsBDA_is_64b_i  <= '0';
1767 
      elsif trn_clk'event and trn_clk = '1' then
1768 
 
1769 
        if dsDMA_Channel_Rst_i = '1' then
1770 
            DMA_ds_BDA_i <= (OTHERS => '0');
1771 
            dsBDA_is_64b_i <= '0';
1772 
        else
1773 
 
1774 
          if Regs_WrEn_r2='1' and Reg_WrMuxer_Hi(CINT_ADDR_DMA_DS_BDAH)='1' then
1775 
            DMA_ds_BDA_i(C_DBUS_WIDTH-1 downto 32)  <= Regs_WrDin_r2(C_DBUS_WIDTH-1 downto 32);
1776 
            dsBDA_is_64b_i   <=  WrDin_r2_not_Zero_Hi;
1777 
          elsif Regs_WrEn_r2='1' and Reg_WrMuxer_Lo(CINT_ADDR_DMA_DS_BDAH)='1' then
1778 
            DMA_ds_BDA_i(C_DBUS_WIDTH-1 downto 32)  <= Regs_WrDin_r2(32-1 downto 0);
1779 
            dsBDA_is_64b_i   <=  WrDin_r2_not_Zero_Lo;
1780 
          else
1781 
            DMA_ds_BDA_i(C_DBUS_WIDTH-1 downto 32)  <= DMA_ds_BDA_i(C_DBUS_WIDTH-1 downto 32);
1782 
            dsBDA_is_64b_i   <=  dsBDA_is_64b_i;
1783 
          end if;
1784 
 
1785 
          if Regs_WrEn_r2='1' and Reg_WrMuxer_Hi(CINT_ADDR_DMA_DS_BDAL)='1' then
1786 
            DMA_ds_BDA_i(32-1 downto 0)  <= Regs_WrDin_r2(C_DBUS_WIDTH-1 downto 32);
1787 
          elsif Regs_WrEn_r2='1' and Reg_WrMuxer_Lo(CINT_ADDR_DMA_DS_BDAL)='1' then
1788 
            DMA_ds_BDA_i(32-1 downto 0)  <= Regs_WrDin_r2(32-1 downto 0);
1789 
          else
1790 
            DMA_ds_BDA_i(32-1 downto 0)  <= DMA_ds_BDA_i(32-1 downto 0);
1791 
          end if;
1792 
 
1793 
        end if;
1794 
      end if;
1795 
   end process;
1796 
 
1797 
 
1798 
 
1799 
-- Synchronous Registered: DMA_ds_Length_i
1800 
   RxTrn_DMA_ds_Length:
1801 
   process ( trn_clk, trn_lnk_up_n)
1802 
   begin
1803 
      if trn_lnk_up_n = '1' then
1804 
         DMA_ds_Length_i     <= (OTHERS => '0');
1805 
         dsLeng_Hi19b_True_i <= '0';
1806 
         dsLeng_Lo7b_True_i  <= '0';
1807 
      elsif trn_clk'event and trn_clk = '1' then
1808 
 
1809 
         if dsDMA_Channel_Rst_i = '1' then
1810 
            DMA_ds_Length_i <= (OTHERS => '0');
1811 
            dsLeng_Hi19b_True_i <= '0';
1812 
            dsLeng_Lo7b_True_i  <= '0';
1813 
 
1814 
         elsif Regs_WrEn_r2='1' and Reg_WrMuxer_Hi(CINT_ADDR_DMA_DS_LENG)='1' then
1815 
            DMA_ds_Length_i(32-1 downto 0)     <= Regs_WrDin_r2(C_DBUS_WIDTH-1 downto 32);
1816 
            dsLeng_Hi19b_True_i <= Regs_WrDin_Hi19b_True_hq_r2;
1817 
            dsLeng_Lo7b_True_i  <= Regs_WrDin_Lo7b_True_hq_r2;
1818 
         elsif Regs_WrEn_r2='1' and Reg_WrMuxer_Lo(CINT_ADDR_DMA_DS_LENG)='1' then
1819 
            DMA_ds_Length_i(32-1 downto 0)     <= Regs_WrDin_r2(32-1 downto 0);
1820 
            dsLeng_Hi19b_True_i <= Regs_WrDin_Hi19b_True_lq_r2;
1821 
            dsLeng_Lo7b_True_i  <= Regs_WrDin_Lo7b_True_lq_r2;
1822 
         else
1823 
            DMA_ds_Length_i     <= DMA_ds_Length_i;
1824 
            dsLeng_Hi19b_True_i <= dsLeng_Hi19b_True_i;
1825 
            dsLeng_Lo7b_True_i  <= dsLeng_Lo7b_True_i;
1826 
 
1827 
         end if;
1828 
 
1829 
      end if;
1830 
   end process;
1831 
 
1832 
 
1833 
 
1834 
-- -------------------------------------------------------
1835 
-- Synchronous ds_Param_Modified
1836 
   SynReg_ds_Param_Modified:
1837 
   process ( trn_clk, trn_lnk_up_n)
1838 
   begin
1839 
      if trn_lnk_up_n = '1' then
1840 
         ds_Param_Modified     <= '0';
1841 
 
1842 
      elsif trn_clk'event and trn_clk = '1' then
1843 
 
1844 
        if dsDMA_Channel_Rst_i = '1'
1845 
           or dsDMA_Start_i = '1'
1846 
           or dsDMA_Start2_i = '1'
1847 
           then
1848 
             ds_Param_Modified     <= '0';
1849 
        elsif Regs_WrEn_r2='1' and
1850 
                (
1851 
--                    Reg_WrMuxer(CINT_ADDR_DMA_DS_PAH) ='1'
1852 
--                 or
1853 
                    Reg_WrMuxer_Hi(CINT_ADDR_DMA_DS_PAL) ='1'
1854 
                 or Reg_WrMuxer_Lo(CINT_ADDR_DMA_DS_PAL) ='1'
1855 
                 or Reg_WrMuxer_Hi(CINT_ADDR_DMA_DS_HAH) ='1'
1856 
                 or Reg_WrMuxer_Lo(CINT_ADDR_DMA_DS_HAH) ='1'
1857 
                 or Reg_WrMuxer_Hi(CINT_ADDR_DMA_DS_HAL) ='1'
1858 
                 or Reg_WrMuxer_Lo(CINT_ADDR_DMA_DS_HAL) ='1'
1859 
                 or Reg_WrMuxer_Hi(CINT_ADDR_DMA_DS_BDAH)='1'
1860 
                 or Reg_WrMuxer_Lo(CINT_ADDR_DMA_DS_BDAH)='1'
1861 
                 or Reg_WrMuxer_Hi(CINT_ADDR_DMA_DS_BDAL)='1'
1862 
                 or Reg_WrMuxer_Lo(CINT_ADDR_DMA_DS_BDAL)='1'
1863 
                 or Reg_WrMuxer_Hi(CINT_ADDR_DMA_DS_LENG)='1'
1864 
                 or Reg_WrMuxer_Lo(CINT_ADDR_DMA_DS_LENG)='1'
1865 
                )
1866 
           then
1867 
             ds_Param_Modified     <= '1';
1868 
        else
1869 
             ds_Param_Modified     <= ds_Param_Modified;
1870 
 
1871 
        end if;
1872 
 
1873 
      end if;
1874 
   end process;
1875 
 
1876 
 
1877 
 
1878 
-- -------------------------------------------------------
1879 
-- Synchronous output: DMA_ds_Control_i
1880 
   Syn_Output_DMA_ds_Control:
1881 
   process ( trn_clk, trn_lnk_up_n)
1882 
   begin
1883 
      if trn_lnk_up_n = '1' then
1884 
         DMA_ds_Control_i <= (OTHERS =>'0');
1885 
 
1886 
      elsif trn_clk'event and trn_clk = '1' then
1887 
 
1888 
         if     Regs_Wr_dma_V_nE_Hi_r2='1'
1889 
            and Reg_WrMuxer_Hi(CINT_ADDR_DMA_DS_CTRL)='1'
1890 
--            and Regs_WrDin_r2(CINT_BIT_DMA_CTRL_VALID+32)='1'
1891 
--            and Regs_WrDin_r2(CINT_BIT_DMA_CTRL_END+32)='0'
1892 
            and ds_Param_Modified='1'
1893 
            and dsDMA_Stop_i='0'
1894 
            then
1895 
               DMA_ds_Control_i(32-1 downto 0) <= Regs_WrDin_r2(C_DBUS_WIDTH-1 downto 8+32)& X"00";
1896 
         elsif  Regs_Wr_dma_V_nE_Lo_r2='1'
1897 
            and Reg_WrMuxer_Lo(CINT_ADDR_DMA_DS_CTRL)='1'
1898 
--            and Regs_WrDin_r2(CINT_BIT_DMA_CTRL_VALID)='1'
1899 
--            and Regs_WrDin_r2(CINT_BIT_DMA_CTRL_END)='0'
1900 
            and ds_Param_Modified='1'
1901 
            and dsDMA_Stop_i='0'
1902 
            then
1903 
               DMA_ds_Control_i(32-1 downto 0) <= Regs_WrDin_r2(32-1 downto 8)& X"00";
1904 
         elsif  Regs_Wr_dma_nV_Hi_r2='1'
1905 
            and (Reg_WrMuxer_Hi(CINT_ADDR_DMA_DS_CTRL)='1' or Reg_WrMuxer_Lo(CINT_ADDR_DMA_DS_CTRL)='1')
1906 
--            and Regs_WrDin_r2(CINT_BIT_DMA_CTRL_VALID)='0'
1907 
            then
1908 
               DMA_ds_Control_i <= Last_Ctrl_Word_ds;
1909 
         else
1910 
            DMA_ds_Control_i  <= DMA_ds_Control_i;
1911 
         end if;
1912 
 
1913 
      end if;
1914 
   end process;
1915 
 
1916 
 
1917 
-- -------------------------------------------------------
1918 
-- Synchronous Register: Last_Ctrl_Word_ds
1919 
   Hold_Last_Ctrl_Word_ds:
1920 
   process ( trn_clk, trn_lnk_up_n)
1921 
   begin
1922 
      if trn_lnk_up_n = '1' then
1923 
         Last_Ctrl_Word_ds  <= C_DEF_DMA_CTRL_WORD;
1924 
      elsif trn_clk'event and trn_clk = '1' then
1925 
 
1926 
        if dsDMA_Channel_Rst_i = '1' then
1927 
            Last_Ctrl_Word_ds <= C_DEF_DMA_CTRL_WORD;
1928 
        elsif Regs_Wr_dma_V_nE_Hi_r2='1'
1929 
          and Reg_WrMuxer_Hi(CINT_ADDR_DMA_DS_CTRL)='1'
1930 
--          and Regs_WrDin_r2(CINT_BIT_DMA_CTRL_VALID+32)='1'
1931 
--          and Regs_WrDin_r2(CINT_BIT_DMA_CTRL_END+32)='0'
1932 
          and ds_Param_Modified='1'
1933 
          and dsDMA_Stop_i='0'
1934 
          then
1935 
            Last_Ctrl_Word_ds(32-1 downto 0) <= Regs_WrDin_r2(C_DBUS_WIDTH-1 downto 8+32) & X"00";
1936 
        elsif Regs_Wr_dma_V_nE_Lo_r2='1'
1937 
          and Reg_WrMuxer_Lo(CINT_ADDR_DMA_DS_CTRL)='1'
1938 
--          and Regs_WrDin_r2(CINT_BIT_DMA_CTRL_VALID)='1'
1939 
--          and Regs_WrDin_r2(CINT_BIT_DMA_CTRL_END)='0'
1940 
          and ds_Param_Modified='1'
1941 
          and dsDMA_Stop_i='0'
1942 
          then
1943 
            Last_Ctrl_Word_ds(32-1 downto 0) <= Regs_WrDin_r2(32-1 downto 8) & X"00";
1944 
        else
1945 
            Last_Ctrl_Word_ds <= Last_Ctrl_Word_ds;
1946 
        end if;
1947 
 
1948 
      end if;
1949 
   end process;
1950 
 
1951 
 
1952 
-- -------------------------------------------------------
1953 
-- Synchronous output: DMA_ds_Start_Stop
1954 
   Syn_Output_DMA_ds_Start_Stop:
1955 
   process ( trn_clk, trn_lnk_up_n)
1956 
   begin
1957 
      if trn_lnk_up_n = '1' then
1958 
         dsDMA_Start_i  <= '0';
1959 
         dsDMA_Stop_i   <= '0';
1960 
 
1961 
      elsif trn_clk'event and trn_clk = '1' then
1962 
 
1963 
         if     Regs_WrEnA_r2='1'
1964 
            and Reg_WrMuxer_Hi(CINT_ADDR_DMA_DS_CTRL)='1'
1965 
            and Regs_WrDin_r2(CINT_BIT_DMA_CTRL_VALID+32)='1'
1966 
            then
1967 
               dsDMA_Start_i <= not Regs_WrDin_r2(CINT_BIT_DMA_CTRL_END+32)
1968 
                            and not dsDMA_Stop_i
1969 
                            and not Command_is_Reset_Hi
1970 
                            and ds_Param_Modified
1971 
                            ;
1972 
               dsDMA_Stop_i  <= Regs_WrDin_r2(CINT_BIT_DMA_CTRL_END+32)
1973 
                            and not Command_is_Reset_Hi
1974 
                            ;
1975 
         elsif  Regs_WrEnA_r2='1'
1976 
            and Reg_WrMuxer_Lo(CINT_ADDR_DMA_DS_CTRL)='1'
1977 
            and Regs_WrDin_r2(CINT_BIT_DMA_CTRL_VALID)='1'
1978 
            then
1979 
               dsDMA_Start_i <= not Regs_WrDin_r2(CINT_BIT_DMA_CTRL_END)
1980 
                            and not dsDMA_Stop_i
1981 
                            and not Command_is_Reset_Lo
1982 
                            and ds_Param_Modified
1983 
                            ;
1984 
               dsDMA_Stop_i  <= Regs_WrDin_r2(CINT_BIT_DMA_CTRL_END)
1985 
                            and not Command_is_Reset_Lo
1986 
                            ;
1987 
         elsif  Regs_WrEnA_r2='1'
1988 
            and (Reg_WrMuxer_Hi(CINT_ADDR_DMA_DS_CTRL)='1' or Reg_WrMuxer_Lo(CINT_ADDR_DMA_DS_CTRL)='1')
1989 
            and Regs_WrDin_r2(CINT_BIT_DMA_CTRL_VALID+32)='0'
1990 
            then
1991 
               dsDMA_Start_i <= not Last_Ctrl_Word_ds(CINT_BIT_DMA_CTRL_END)
1992 
                            and ds_Param_Modified
1993 
                            ;
1994 
               dsDMA_Stop_i  <= Last_Ctrl_Word_ds(CINT_BIT_DMA_CTRL_END);
1995 
         elsif dsDMA_Cmd_Ack='1'
1996 
            then
1997 
               dsDMA_Start_i <= '0';
1998 
               dsDMA_Stop_i  <= dsDMA_Stop_i;
1999 
         else
2000 
               dsDMA_Start_i <= dsDMA_Start_i;
2001 
               dsDMA_Stop_i  <= dsDMA_Stop_i;
2002 
         end if;
2003 
 
2004 
      end if;
2005 
   end process;
2006 
 
2007 
 
2008 
-- -------------------------------------------------------
2009 
-- Synchronous output: DMA_ds_Start2_Stop2
2010 
   Syn_Output_DMA_ds_Start2_Stop2:
2011 
   process ( trn_clk, trn_lnk_up_n)
2012 
   begin
2013 
      if trn_lnk_up_n = '1' then
2014 
         dsDMA_Start2_i <= '0';
2015 
         dsDMA_Stop2_i  <= '0';
2016 
 
2017 
      elsif trn_clk'event and trn_clk = '1' then
2018 
 
2019 
         if dsDMA_Channel_Rst_i='1' then
2020 
               dsDMA_Start2_i <= '0';
2021 
               dsDMA_Stop2_i  <= '0';
2022 
         elsif     Regs_WrEnB_r2='1'
2023 
            and Reg_WrMuxer_Hi(CINT_ADDR_DMA_DS_CTRL)='1'
2024 
            and Regs_WrDin_r2(CINT_BIT_DMA_CTRL_VALID+32)='1'
2025 
            then
2026 
               dsDMA_Start2_i <= not Regs_WrDin_r2(CINT_BIT_DMA_CTRL_END+32) and not Command_is_Reset_Hi;
2027 
               dsDMA_Stop2_i  <= Regs_WrDin_r2(CINT_BIT_DMA_CTRL_END+32) and not Command_is_Reset_Hi;
2028 
         elsif  Regs_WrEnB_r2='1'
2029 
            and Reg_WrMuxer_Lo(CINT_ADDR_DMA_DS_CTRL)='1'
2030 
            and Regs_WrDin_r2(CINT_BIT_DMA_CTRL_VALID)='1'
2031 
            then
2032 
               dsDMA_Start2_i <= not Regs_WrDin_r2(CINT_BIT_DMA_CTRL_END) and not Command_is_Reset_Lo;
2033 
               dsDMA_Stop2_i  <= Regs_WrDin_r2(CINT_BIT_DMA_CTRL_END) and not Command_is_Reset_Lo;
2034 
         elsif  Regs_WrEnB_r2='1'
2035 
            and Reg_WrMuxer_Hi(CINT_ADDR_DMA_DS_CTRL)='1'
2036 
            and Regs_WrDin_r2(CINT_BIT_DMA_CTRL_VALID+32)='0'
2037 
            then
2038 
               dsDMA_Start2_i <= not Last_Ctrl_Word_ds(CINT_BIT_DMA_CTRL_END);
2039 
               dsDMA_Stop2_i  <= Last_Ctrl_Word_ds(CINT_BIT_DMA_CTRL_END);
2040 
         elsif  Regs_WrEnB_r2='1'
2041 
            and Reg_WrMuxer_Lo(CINT_ADDR_DMA_DS_CTRL)='1'
2042 
            and Regs_WrDin_r2(CINT_BIT_DMA_CTRL_VALID)='0'
2043 
            then
2044 
               dsDMA_Start2_i <= not Last_Ctrl_Word_ds(CINT_BIT_DMA_CTRL_END);
2045 
               dsDMA_Stop2_i  <= Last_Ctrl_Word_ds(CINT_BIT_DMA_CTRL_END);
2046 
         elsif dsDMA_Cmd_Ack='1' then
2047 
               dsDMA_Start2_i <= '0';
2048 
               dsDMA_Stop2_i  <= dsDMA_Stop2_i;
2049 
         else
2050 
               dsDMA_Start2_i <= dsDMA_Start2_i;
2051 
               dsDMA_Stop2_i  <= dsDMA_Stop2_i;
2052 
         end if;
2053 
 
2054 
      end if;
2055 
   end process;
2056 
 
2057 
 
2058 
------------------------------------------------------------------------
2059 
--                          Reset signals                             --
2060 
------------------------------------------------------------------------
2061 
 
2062 
-- --------------------------------------
2063 
-- Identification: Command_is_Reset
2064 
--
2065 
   Synch_Capture_Command_is_Reset:
2066 
   process ( trn_clk, trn_lnk_up_n)
2067 
   begin
2068 
      if trn_lnk_up_n = '1' then
2069 
         Command_is_Reset_Hi    <= '0';
2070 
         Command_is_Reset_Lo    <= '0';
2071 
 
2072 
      elsif trn_clk'event and trn_clk = '1' then
2073 
         if Regs_WrDin_r1(C_FEAT_BITS_WIDTH-1+32 downto 32)=C_CHANNEL_RST_BITS then
2074 
            Command_is_Reset_Hi    <= '1';
2075 
         else
2076 
            Command_is_Reset_Hi    <= '0';
2077 
         end if;
2078 
 
2079 
         if Regs_WrDin_r1(C_FEAT_BITS_WIDTH-1 downto 0)=C_CHANNEL_RST_BITS then
2080 
            Command_is_Reset_Lo    <= '1';
2081 
         else
2082 
            Command_is_Reset_Lo    <= '0';
2083 
         end if;
2084 
      end if;
2085 
   end process;
2086 
 
2087 
 
2088 
-- --------------------------------------
2089 
-- Identification: Command_is_Host_iClr
2090 
--
2091 
   Synch_Capture_Command_is_Host_iClr:
2092 
   process ( trn_clk, trn_lnk_up_n)
2093 
   begin
2094 
      if trn_lnk_up_n = '1' then
2095 
         Command_is_Host_iClr_Hi    <= '0';
2096 
         Command_is_Host_iClr_Lo    <= '0';
2097 
 
2098 
      elsif trn_clk'event and trn_clk = '1' then
2099 
         if Regs_WrDin_r1(C_FEAT_BITS_WIDTH-1+32 downto 32)=C_HOST_ICLR_BITS then
2100 
            Command_is_Host_iClr_Hi    <= '1';
2101 
         else
2102 
            Command_is_Host_iClr_Hi    <= '0';
2103 
         end if;
2104 
 
2105 
         if Regs_WrDin_r1(C_FEAT_BITS_WIDTH-1 downto 0)=C_HOST_ICLR_BITS then
2106 
            Command_is_Host_iClr_Lo    <= '1';
2107 
         else
2108 
            Command_is_Host_iClr_Lo    <= '0';
2109 
         end if;
2110 
      end if;
2111 
   end process;
2112 
 
2113 
-------------------------------------------
2114 
-- Synchronous output: usDMA_Channel_Rst_i
2115 
--
2116 
   Syn_Output_usDMA_Channel_Rst:
2117 
   process ( trn_clk, trn_lnk_up_n)
2118 
   begin
2119 
      if trn_lnk_up_n = '1' then
2120 
         usDMA_Channel_Rst_i <= '1';
2121 
      elsif trn_clk'event and trn_clk = '1' then
2122 
 
2123 
         usDMA_Channel_Rst_i <= (Regs_Wr_dma_V_Hi_r2
2124 
                            and Reg_WrMuxer_Hi(CINT_ADDR_DMA_US_CTRL)
2125 
--                            and Regs_WrDin_r2(CINT_BIT_DMA_CTRL_VALID+32)
2126 
                            and Command_is_Reset_Hi
2127 
                                )
2128 
                            or  (Regs_Wr_dma_V_LO_r2
2129 
                            and Reg_WrMuxer_Lo(CINT_ADDR_DMA_US_CTRL)
2130 
--                            and Regs_WrDin_r2(CINT_BIT_DMA_CTRL_VALID)
2131 
                            and Command_is_Reset_Lo
2132 
                                )
2133 
                            ;
2134 
      end if;
2135 
   end process;
2136 
 
2137 
 
2138 
 
2139 
-------------------------------------------
2140 
-- Synchronous output: dsDMA_Channel_Rst_i
2141 
--
2142 
   Syn_Output_dsDMA_Channel_Rst:
2143 
   process ( trn_clk, trn_lnk_up_n)
2144 
   begin
2145 
      if trn_lnk_up_n = '1' then
2146 
         dsDMA_Channel_Rst_i <= '1';
2147 
      elsif trn_clk'event and trn_clk = '1' then
2148 
 
2149 
         dsDMA_Channel_Rst_i <= (Regs_Wr_dma_V_Hi_r2
2150 
                            and Reg_WrMuxer_Hi(CINT_ADDR_DMA_DS_CTRL)
2151 
--                            and Regs_WrDin_r2(CINT_BIT_DMA_CTRL_VALID+32)
2152 
                            and Command_is_Reset_Hi
2153 
                            )
2154 
                            or
2155 
                           (Regs_Wr_dma_V_Lo_r2
2156 
                            and Reg_WrMuxer_Lo(CINT_ADDR_DMA_DS_CTRL)
2157 
--                            and Regs_WrDin_r2(CINT_BIT_DMA_CTRL_VALID)
2158 
                            and Command_is_Reset_Lo
2159 
                            )
2160 
                            ;
2161 
      end if;
2162 
   end process;
2163 
 
2164 
 
2165 
-- -----------------------------------------------
2166 
-- Synchronous output: MRd_Channel_Rst_i
2167 
--
2168 
   Syn_Output_MRd_Channel_Rst:
2169 
   process ( trn_clk, trn_lnk_up_n)
2170 
   begin
2171 
      if trn_lnk_up_n = '1' then
2172 
         MRd_Channel_Rst_i <= '1';
2173 
      elsif trn_clk'event and trn_clk = '1' then
2174 
 
2175 
         MRd_Channel_Rst_i    <= Regs_WrEn_r2
2176 
                             and (
2177 
                                 (Reg_WrMuxer_Hi(CINT_ADDR_MRD_CTRL)
2178 
                                  and Command_is_Reset_Hi)
2179 
                             or
2180 
                                 (Reg_WrMuxer_Lo(CINT_ADDR_MRD_CTRL)
2181 
                                  and Command_is_Reset_Lo)
2182 
                             )
2183 
                             ;
2184 
      end if;
2185 
   end process;
2186 
 
2187 
 
2188 
-- -----------------------------------------------
2189 
-- Synchronous output: Tx_Reset_i
2190 
--
2191 
   Syn_Output_Tx_Reset:
2192 
   process ( trn_clk, trn_lnk_up_n)
2193 
   begin
2194 
      if trn_lnk_up_n = '1' then
2195 
         Tx_Reset_i   <= '1';
2196 
      elsif trn_clk'event and trn_clk = '1' then
2197 
 
2198 
         Tx_Reset_i   <= Regs_WrEn_r2
2199 
                     and ((Reg_WrMuxer_Hi(CINT_ADDR_TX_CTRL)
2200 
                     and Command_is_Reset_Hi)
2201 
                     or  (Reg_WrMuxer_Lo(CINT_ADDR_TX_CTRL)
2202 
                     and Command_is_Reset_Lo))
2203 
                     ;
2204 
      end if;
2205 
   end process;
2206 
 
2207 
 
2208 
-- -----------------------------------------------
2209 
-- Synchronous output: eb_FIFO_Rst_i
2210 
--
2211 
   Syn_Output_eb_FIFO_Rst:
2212 
   process ( trn_clk, trn_lnk_up_n)
2213 
   begin
2214 
      if trn_lnk_up_n = '1' then
2215 
         eb_FIFO_Rst_i    <= '1';
2216 
         eb_FIFO_Rst_b3   <= '1';
2217 
         eb_FIFO_Rst_b2   <= '1';
2218 
         eb_FIFO_Rst_b1   <= '1';
2219 
      elsif trn_clk'event and trn_clk = '1' then
2220 
 
2221 
         eb_FIFO_Rst_i   <= eb_FIFO_Rst_b1 or eb_FIFO_Rst_b2 or eb_FIFO_Rst_b3;
2222 
         eb_FIFO_Rst_b3  <= eb_FIFO_Rst_b2;
2223 
         eb_FIFO_Rst_b2  <= eb_FIFO_Rst_b1;
2224 
         eb_FIFO_Rst_b1  <= Regs_WrEn_r2
2225 
                         and ((Reg_WrMuxer_Hi(CINT_ADDR_EB_STACON)
2226 
                         and Command_is_Reset_Hi)
2227 
                         or  (Reg_WrMuxer_Lo(CINT_ADDR_EB_STACON)
2228 
                         and Command_is_Reset_Lo))
2229 
                         ;
2230 
      end if;
2231 
   end process;
2232 
 
2233 
 
2234 
-- -----------------------------------------------
2235 
-- Synchronous output: protocol_rst
2236 
--
2237 
--            !!!  reset by trn_reset_n  !!!
2238 
--
2239 
   Syn_Output_protocol_rst:
2240 
   process ( trn_clk, trn_reset_n)
2241 
   begin
2242 
      if trn_reset_n = '0' then
2243 
         protocol_rst_i   <= '1';
2244 
         protocol_rst_b1  <= '1';
2245 
         protocol_rst_b2  <= '1';
2246 
      elsif trn_clk'event and trn_clk = '1' then
2247 
 
2248 
         protocol_rst_i  <= protocol_rst_b1 or protocol_rst_b2;
2249 
         protocol_rst_b1 <= protocol_rst_b2;
2250 
         protocol_rst_b2 <= Regs_WrEn_r2
2251 
                         and ((Reg_WrMuxer_Hi(CINT_ADDR_PROTOCOL_STACON)
2252 
                         and Command_is_Reset_Hi)
2253 
                         or  (Reg_WrMuxer_Lo(CINT_ADDR_PROTOCOL_STACON)
2254 
                         and Command_is_Reset_Lo))
2255 
                         ;
2256 
      end if;
2257 
   end process;
2258 
 
2259 
 
2260 
-- -----------------------------------------------
2261 
-- Synchronous Calculation: DMA_us_Transf_Bytes
2262 
--
2263 
   Syn_Calc_DMA_us_Transf_Bytes:
2264 
   process ( trn_clk, trn_lnk_up_n)
2265 
   begin
2266 
      if trn_lnk_up_n = '1' then
2267 
         DMA_us_Transf_Bytes_i   <= (OTHERS=>'0');
2268 
      elsif trn_clk'event and trn_clk = '1' then
2269 
 
2270 
         if usDMA_Channel_Rst_i='1' then
2271 
            DMA_us_Transf_Bytes_i   <= (OTHERS=>'0');
2272 
         elsif us_DMA_Bytes_Add='1' then
2273 
            DMA_us_Transf_Bytes_i(32-1 downto 0)
2274 
                                    <= DMA_us_Transf_Bytes_i(32-1 downto 0)
2275 
                                    +  us_DMA_Bytes;
2276 
         else
2277 
            DMA_us_Transf_Bytes_i   <= DMA_us_Transf_Bytes_i;
2278 
         end if;
2279 
      end if;
2280 
   end process;
2281 
 
2282 
 
2283 
-- -----------------------------------------------
2284 
-- Synchronous Calculation: DMA_ds_Transf_Bytes
2285 
--
2286 
   Syn_Calc_DMA_ds_Transf_Bytes:
2287 
   process ( trn_clk, trn_lnk_up_n)
2288 
   begin
2289 
      if trn_lnk_up_n = '1' then
2290 
         DMA_ds_Transf_Bytes_i   <= (OTHERS=>'0');
2291 
      elsif trn_clk'event and trn_clk = '1' then
2292 
 
2293 
         if dsDMA_Channel_Rst_i='1' then
2294 
            DMA_ds_Transf_Bytes_i   <= (OTHERS=>'0');
2295 
         elsif ds_DMA_Bytes_Add='1' then
2296 
            DMA_ds_Transf_Bytes_i(32-1 downto 0)
2297 
                                    <= DMA_ds_Transf_Bytes_i(32-1 downto 0)
2298 
                                    +  ds_DMA_Bytes;
2299 
         else
2300 
            DMA_ds_Transf_Bytes_i   <= DMA_ds_Transf_Bytes_i;
2301 
         end if;
2302 
      end if;
2303 
   end process;
2304 
 
2305 
---- -------------------------------------------------------
2306 
---- Synchronous Registers: icap_Write_i
2307 
--   RxTrn_icap_Write:
2308 
--   process ( trn_clk, trn_lnk_up_n)
2309 
--   begin
2310 
--      if trn_lnk_up_n = '1' then
2311 
--         icap_CLK      <= '0';
2312 
--         icap_I        <= (OTHERS => '0');
2313 
--         icap_Write    <= '1';
2314 
--         icap_CE       <= '1';
2315 
--         FSM_icap      <= icapST_Reset;
2316 
--
2317 
--      elsif trn_clk'event and trn_clk = '1' then
2318 
--
2319 
--        case FSM_icap is
2320 
--
2321 
--          when icapST_Reset =>
2322 
--            icap_CLK      <= '0';
2323 
--            icap_I        <= (OTHERS => '0');
2324 
--            icap_Write    <= '1';
2325 
--            icap_CE       <= '1';
2326 
--            FSM_icap      <= icapST_Idle;
2327 
--
2328 
--          when icapST_Idle =>
2329 
--
2330 
--            if Regs_WrEn_r2='1' and  Reg_WrMuxer(CINT_ADDR_ICAP)='1' then
2331 
--               icap_CLK   <= '1';
2332 
--               icap_I     <= Regs_WrDin_r2;
2333 
--               icap_Write <= '0';
2334 
--               icap_CE    <= '0';
2335 
--               FSM_icap   <= icapST_Access;
2336 
--            elsif Reg_RdMuxer(CINT_ADDR_ICAP)='1' then
2337 
--               icap_CLK   <= '1';
2338 
--               icap_I     <= icap_I;
2339 
--               icap_Write <= '1';
2340 
--               icap_CE    <= '0';
2341 
--               FSM_icap   <= icapST_Access;
2342 
--            else
2343 
--               icap_CLK   <= icap_CLK;
2344 
--               icap_I     <= icap_I;
2345 
--               icap_Write <= icap_Write;
2346 
--               icap_CE    <= icap_CE;
2347 
--               FSM_icap   <= icapST_Idle;
2348 
--            end if;
2349 
--
2350 
--
2351 
--          when icapST_Access =>
2352 
--               icap_CLK   <= '1';
2353 
--               icap_I     <= icap_I;
2354 
--               icap_Write <= icap_Write;
2355 
--               icap_CE    <= icap_CE;
2356 
--               FSM_icap   <= icapST_Abort;
2357 
--
2358 
--          when icapST_Abort =>
2359 
--               icap_CLK   <= '0';
2360 
--               icap_I     <= icap_I;
2361 
--               icap_Write <= icap_Write;
2362 
--               icap_CE    <= icap_CE;
2363 
--               FSM_icap   <= icapST_Idle;
2364 
--
2365 
--          when Others =>
2366 
--            icap_CLK      <= '0';
2367 
--            icap_I        <= (OTHERS => '0');
2368 
--            icap_Write    <= '1';
2369 
--            icap_CE       <= '1';
2370 
--            FSM_icap      <= icapST_Idle;
2371 
--
2372 
--        end case;
2373 
--
2374 
--      end if;
2375 
--   end process;
2376 
--
2377 
 
2378 
 
2379 
----------------------------------------------------------
2380 
---------------  Tx reading registers  -------------------
2381 
----------------------------------------------------------
2382 
 
2383 
----------------------------------------------------------
2384 
-- Synch Register:  Read Selection
2385 
--
2386 
   Tx_DMA_Reg_RdMuxer:
2387 
   process ( trn_clk, trn_lnk_up_n)
2388 
   begin
2389 
      if trn_lnk_up_n = '1' then
2390 
           Reg_RdMuxer_Hi     <= (Others =>'0');
2391 
           Reg_RdMuxer_Lo     <= (Others =>'0');
2392 
 
2393 
      elsif trn_clk'event and trn_clk = '1' then
2394 
 
2395 
         FOR k IN 0 TO C_NUM_OF_ADDRESSES-1 LOOP
2396 
            if Regs_RdAddr_i(C_DECODE_BIT_TOP downto C_DECODE_BIT_BOT)= C_REGS_BASE_ADDR(C_DECODE_BIT_TOP downto C_DECODE_BIT_BOT)
2397 
               and Regs_RdAddr_i(C_DECODE_BIT_BOT-1 downto 2)=CONV_STD_LOGIC_VECTOR(k, C_DECODE_BIT_BOT-2)
2398 
               and Regs_RdAddr_i(2-1 downto 0)="00"
2399 
               then
2400 
               Reg_RdMuxer_Hi(k) <= '1';
2401 
            else
2402 
               Reg_RdMuxer_Hi(k) <= '0';
2403 
            end if;
2404 
         END LOOP;
2405 
 
2406 
         if Regs_RdAddr_i(C_DECODE_BIT_TOP downto C_DECODE_BIT_BOT)= C_ALL_ONES(C_DECODE_BIT_TOP downto C_DECODE_BIT_BOT)
2407 
            and Regs_RdAddr_i(C_DECODE_BIT_BOT-1 downto 2)=C_ALL_ONES(C_DECODE_BIT_BOT-1 downto 2)
2408 
            and Regs_RdAddr_i(2-1 downto 0)="00"
2409 
            then
2410 
            Reg_RdMuxer_Lo(0) <= '1';
2411 
         else
2412 
            Reg_RdMuxer_Lo(0) <= '0';
2413 
         end if;
2414 
         FOR k IN 1 TO C_NUM_OF_ADDRESSES-1 LOOP
2415 
            if Regs_RdAddr_i(C_DECODE_BIT_TOP downto C_DECODE_BIT_BOT)= C_REGS_BASE_ADDR(C_DECODE_BIT_TOP downto C_DECODE_BIT_BOT)
2416 
               and Regs_RdAddr_i(C_DECODE_BIT_BOT-1 downto 2)=CONV_STD_LOGIC_VECTOR(k-1, C_DECODE_BIT_BOT-2)
2417 
               and Regs_RdAddr_i(2-1 downto 0)="00"
2418 
               then
2419 
               Reg_RdMuxer_Lo(k) <= '1';
2420 
            else
2421 
               Reg_RdMuxer_Lo(k) <= '0';
2422 
            end if;
2423 
         END LOOP;
2424 
 
2425 
      end if;
2426 
   end process;
2427 
 
2428 
 
2429 
----------------------------------------------------------
2430 
-- Synch Register:  CTL_TTake
2431 
--
2432 
   Syn_CTL_ttake:
2433 
   process ( trn_clk, trn_lnk_up_n)
2434 
   begin
2435 
      if trn_lnk_up_n = '1' then
2436 
         ctl_ttake_i      <= '0';
2437 
         ctl_t_read_Hi_r1 <= '0';
2438 
         ctl_t_read_Lo_r1 <= '0';
2439 
         CTL_read_counter <= (OTHERS=>'0');
2440 
 
2441 
      elsif trn_clk'event and trn_clk = '1' then
2442 
         ctl_t_read_Hi_r1 <= Reg_RdMuxer_Hi(CINT_ADDR_CTL_CLASS);
2443 
         ctl_t_read_Lo_r1 <= Reg_RdMuxer_Lo(CINT_ADDR_CTL_CLASS);
2444 
         ctl_ttake_i  <= (Reg_RdMuxer_Hi(CINT_ADDR_CTL_CLASS) and not ctl_t_read_Hi_r1)
2445 
                      or (Reg_RdMuxer_Lo(CINT_ADDR_CTL_CLASS) and not ctl_t_read_Lo_r1)
2446 
                      ;
2447 
         if ctl_reset_i='1' then
2448 
            CTL_read_counter <= (OTHERS=>'0');
2449 
         else
2450 
            CTL_read_counter <= CTL_read_counter + ctl_ttake_i;
2451 
         end if;
2452 
 
2453 
      end if;
2454 
   end process;
2455 
 
2456 
----------------------------------------------------------
2457 
-- Synch Register:  class_CTL_Status
2458 
--
2459 
   Syn_class_CTL_Status:
2460 
   process ( trn_clk, trn_lnk_up_n)
2461 
   begin
2462 
      if trn_lnk_up_n = '1' then
2463 
         class_CTL_Status_i      <= (OTHERS=>'0');
2464 
 
2465 
      elsif trn_clk'event and trn_clk = '1' then
2466 
         class_CTL_Status_i(C_DBUS_WIDTH/2-1 downto 0)      <= ctl_status;
2467 
 
2468 
      end if;
2469 
   end process;
2470 
 
2471 
 
2472 
-- -------------------------------------------------------
2473 
--
2474 
   Sys_Int_Status_i     <= (
2475 
                            CINT_BIT_DLM_IN_ISR     => DLM_irq     ,
2476 
                            CINT_BIT_CTL_IN_ISR     => CTL_irq     ,
2477 
                            CINT_BIT_DAQ_IN_ISR     => DAQ_irq     ,
2478 
 
2479 
                            CINT_BIT_DSTOUT_IN_ISR  => DMA_ds_Tout ,
2480 
                            CINT_BIT_USTOUT_IN_ISR  => DMA_us_Tout ,
2481 
 
2482 
                            CINT_BIT_INTGEN_IN_ISR  => IG_Asserting,
2483 
                            CINT_BIT_DS_DONE_IN_ISR => DMA_ds_Done ,
2484 
                            CINT_BIT_US_DONE_IN_ISR => DMA_us_Done ,
2485 
                            OTHERS                  => '0'
2486 
                           );
2487 
 
2488 
   --------------------------------------------------------------------------
2489 
   -- Upstream Registers
2490 
   --------------------------------------------------------------------------
2491 
 
2492 
   --  Peripheral Address Start point
2493 
   DMA_us_PA_o_Hi(C_DBUS_WIDTH-1 downto C_DBUS_WIDTH/2)
2494 
      <= DMA_us_PA_i(C_DBUS_WIDTH-1 downto C_DBUS_WIDTH/2) when Reg_RdMuxer_Hi(CINT_ADDR_DMA_US_PAH)='1'
2495 
         else (Others=>'0');
2496 
 
2497 
   DMA_us_PA_o_Hi(C_DBUS_WIDTH/2-1 downto 0)
2498 
      <= DMA_us_PA_i(C_DBUS_WIDTH/2-1 downto 0) when Reg_RdMuxer_Hi(CINT_ADDR_DMA_US_PAL)='1'
2499 
         else (Others=>'0');
2500 
 
2501 
 
2502 
   --  Host Address Start point
2503 
   DMA_us_HA_o_Hi(C_DBUS_WIDTH-1 downto C_DBUS_WIDTH/2)
2504 
      <= DMA_us_HA_i(C_DBUS_WIDTH-1 downto C_DBUS_WIDTH/2) when Reg_RdMuxer_Hi(CINT_ADDR_DMA_US_HAH)='1'
2505 
         else (Others=>'0');
2506 
 
2507 
   DMA_us_HA_o_Hi(C_DBUS_WIDTH/2-1 downto 0)
2508 
      <= DMA_us_HA_i(C_DBUS_WIDTH/2-1 downto 0) when Reg_RdMuxer_Hi(CINT_ADDR_DMA_US_HAL)='1'
2509 
         else (Others=>'0');
2510 
 
2511 
 
2512 
   --  Next Descriptor Address
2513 
   DMA_us_BDA_o_Hi(C_DBUS_WIDTH-1 downto C_DBUS_WIDTH/2)
2514 
      <= DMA_us_BDA_i(C_DBUS_WIDTH-1 downto C_DBUS_WIDTH/2) when Reg_RdMuxer_Hi(CINT_ADDR_DMA_US_BDAH)='1'
2515 
         else (Others=>'0');
2516 
 
2517 
   DMA_us_BDA_o_Hi(C_DBUS_WIDTH/2-1 downto 0)
2518 
      <= DMA_us_BDA_i(C_DBUS_WIDTH/2-1 downto 0) when Reg_RdMuxer_Hi(CINT_ADDR_DMA_US_BDAL)='1'
2519 
         else (Others=>'0');
2520 
 
2521 
   --  Length
2522 
   DMA_us_Length_o_Hi(32-1 downto 0)
2523 
      <= DMA_us_Length_i(32-1 downto 0) when Reg_RdMuxer_Hi(CINT_ADDR_DMA_US_LENG)='1'
2524 
         else (Others=>'0');
2525 
 
2526 
   --  Control word
2527 
   DMA_us_Control_o_Hi(32-1 downto 0)
2528 
      <= DMA_us_Control_i(32-1 downto 0) when Reg_RdMuxer_Hi(CINT_ADDR_DMA_US_CTRL)='1'
2529 
         else (Others=>'0');
2530 
 
2531 
   --  Status (Read only)
2532 
   DMA_us_Status_o_Hi(32-1 downto 0)
2533 
      <= DMA_us_Status_i(32-1 downto 0) when Reg_RdMuxer_Hi(CINT_ADDR_DMA_US_STA)='1'
2534 
         else (Others=>'0');
2535 
 
2536 
   --  Tranferred bytes (Read only)
2537 
   DMA_us_Transf_Bytes_o_Hi(32-1 downto 0)
2538 
      <= DMA_us_Transf_Bytes_i(32-1 downto 0) when Reg_RdMuxer_Hi(CINT_ADDR_US_TRANSF_BC)='1'
2539 
         else (Others=>'0');
2540 
 
2541 
 
2542 
   --  Peripheral Address Start point
2543 
   DMA_us_PA_o_Lo(C_DBUS_WIDTH-1 downto C_DBUS_WIDTH/2)
2544 
      <= DMA_us_PA_i(C_DBUS_WIDTH-1 downto C_DBUS_WIDTH/2) when Reg_RdMuxer_Lo(CINT_ADDR_DMA_US_PAH)='1'
2545 
         else (Others=>'0');
2546 
 
2547 
   DMA_us_PA_o_Lo(C_DBUS_WIDTH/2-1 downto 0)
2548 
      <= DMA_us_PA_i(C_DBUS_WIDTH/2-1 downto 0) when Reg_RdMuxer_Lo(CINT_ADDR_DMA_US_PAL)='1'
2549 
         else (Others=>'0');
2550 
 
2551 
 
2552 
   --  Host Address Start point
2553 
   DMA_us_HA_o_Lo(C_DBUS_WIDTH-1 downto C_DBUS_WIDTH/2)
2554 
      <= DMA_us_HA_i(C_DBUS_WIDTH-1 downto C_DBUS_WIDTH/2) when Reg_RdMuxer_Lo(CINT_ADDR_DMA_US_HAH)='1'
2555 
         else (Others=>'0');
2556 
 
2557 
   DMA_us_HA_o_Lo(C_DBUS_WIDTH/2-1 downto 0)
2558 
      <= DMA_us_HA_i(C_DBUS_WIDTH/2-1 downto 0) when Reg_RdMuxer_Lo(CINT_ADDR_DMA_US_HAL)='1'
2559 
         else (Others=>'0');
2560 
 
2561 
 
2562 
   --  Next Descriptor Address
2563 
   DMA_us_BDA_o_Lo(C_DBUS_WIDTH-1 downto C_DBUS_WIDTH/2)
2564 
      <= DMA_us_BDA_i(C_DBUS_WIDTH-1 downto C_DBUS_WIDTH/2) when Reg_RdMuxer_Lo(CINT_ADDR_DMA_US_BDAH)='1'
2565 
         else (Others=>'0');
2566 
 
2567 
   DMA_us_BDA_o_Lo(C_DBUS_WIDTH/2-1 downto 0)
2568 
      <= DMA_us_BDA_i(C_DBUS_WIDTH/2-1 downto 0) when Reg_RdMuxer_Lo(CINT_ADDR_DMA_US_BDAL)='1'
2569 
         else (Others=>'0');
2570 
 
2571 
   --  Length
2572 
   DMA_us_Length_o_Lo(32-1 downto 0)
2573 
      <= DMA_us_Length_i(32-1 downto 0) when Reg_RdMuxer_Lo(CINT_ADDR_DMA_US_LENG)='1'
2574 
         else (Others=>'0');
2575 
 
2576 
   --  Control word
2577 
   DMA_us_Control_o_Lo(32-1 downto 0)
2578 
      <= DMA_us_Control_i(32-1 downto 0) when Reg_RdMuxer_Lo(CINT_ADDR_DMA_US_CTRL)='1'
2579 
         else (Others=>'0');
2580 
 
2581 
   --  Status (Read only)
2582 
   DMA_us_Status_o_Lo(32-1 downto 0)
2583 
      <= DMA_us_Status_i(32-1 downto 0) when Reg_RdMuxer_Lo(CINT_ADDR_DMA_US_STA)='1'
2584 
         else (Others=>'0');
2585 
 
2586 
   --  Tranferred bytes (Read only)
2587 
   DMA_us_Transf_Bytes_o_Lo(32-1 downto 0)
2588 
      <= DMA_us_Transf_Bytes_i(32-1 downto 0) when Reg_RdMuxer_Lo(CINT_ADDR_US_TRANSF_BC)='1'
2589 
         else (Others=>'0');
2590 
 
2591 
   --------------------------------------------------------------------------
2592 
   -- Downstream Registers
2593 
   --------------------------------------------------------------------------
2594 
 
2595 
   --  Peripheral Address Start point
2596 
   DMA_ds_PA_o_Hi(C_DBUS_WIDTH-1 downto C_DBUS_WIDTH/2)
2597 
      <= DMA_ds_PA_i(C_DBUS_WIDTH-1 downto C_DBUS_WIDTH/2) when Reg_RdMuxer_Hi(CINT_ADDR_DMA_DS_PAH)='1'
2598 
         else (Others=>'0');
2599 
 
2600 
   DMA_ds_PA_o_Hi(C_DBUS_WIDTH/2-1 downto 0)
2601 
      <= DMA_ds_PA_i(C_DBUS_WIDTH/2-1 downto 0) when Reg_RdMuxer_Hi(CINT_ADDR_DMA_DS_PAL)='1'
2602 
         else (Others=>'0');
2603 
 
2604 
   --  Host Address Start point
2605 
   DMA_ds_HA_o_Hi(C_DBUS_WIDTH-1 downto C_DBUS_WIDTH/2)
2606 
      <= DMA_ds_HA_i(C_DBUS_WIDTH-1 downto C_DBUS_WIDTH/2) when Reg_RdMuxer_Hi(CINT_ADDR_DMA_DS_HAH)='1'
2607 
         else (Others=>'0');
2608 
 
2609 
   DMA_ds_HA_o_Hi(C_DBUS_WIDTH/2-1 downto 0)
2610 
      <= DMA_ds_HA_i(C_DBUS_WIDTH/2-1 downto 0) when Reg_RdMuxer_Hi(CINT_ADDR_DMA_DS_HAL)='1'
2611 
         else (Others=>'0');
2612 
 
2613 
   --  Next Descriptor Address
2614 
   DMA_ds_BDA_o_Hi(C_DBUS_WIDTH-1 downto C_DBUS_WIDTH/2)
2615 
      <= DMA_ds_BDA_i(C_DBUS_WIDTH-1 downto C_DBUS_WIDTH/2) when Reg_RdMuxer_Hi(CINT_ADDR_DMA_DS_BDAH)='1'
2616 
         else (Others=>'0');
2617 
 
2618 
   DMA_ds_BDA_o_Hi(C_DBUS_WIDTH/2-1 downto 0)
2619 
      <= DMA_ds_BDA_i(C_DBUS_WIDTH/2-1 downto 0) when Reg_RdMuxer_Hi(CINT_ADDR_DMA_DS_BDAL)='1'
2620 
         else (Others=>'0');
2621 
 
2622 
   --  Length
2623 
   DMA_ds_Length_o_Hi(32-1 downto 0)
2624 
      <= DMA_ds_Length_i(32-1 downto 0) when Reg_RdMuxer_Hi(CINT_ADDR_DMA_DS_LENG)='1'
2625 
         else (Others=>'0');
2626 
 
2627 
   --  Control word
2628 
   DMA_ds_Control_o_Hi(32-1 downto 0)
2629 
      <= DMA_ds_Control_i(32-1 downto 0) when Reg_RdMuxer_Hi(CINT_ADDR_DMA_DS_CTRL)='1'
2630 
         else (Others=>'0');
2631 
 
2632 
   --  Status (Read only)
2633 
   DMA_ds_Status_o_Hi(32-1 downto 0)
2634 
      <= DMA_ds_Status_i(32-1 downto 0) when Reg_RdMuxer_Hi(CINT_ADDR_DMA_DS_STA)='1'
2635 
         else (Others=>'0');
2636 
 
2637 
   --  Tranferred bytes (Read only)
2638 
   DMA_ds_Transf_Bytes_o_Hi(32-1 downto 0)
2639 
      <= DMA_ds_Transf_Bytes_i(32-1 downto 0) when Reg_RdMuxer_Hi(CINT_ADDR_DS_TRANSF_BC)='1'
2640 
         else (Others=>'0');
2641 
 
2642 
   --  Peripheral Address Start point
2643 
   DMA_ds_PA_o_Lo(C_DBUS_WIDTH-1 downto C_DBUS_WIDTH/2)
2644 
      <= DMA_ds_PA_i(C_DBUS_WIDTH-1 downto C_DBUS_WIDTH/2) when Reg_RdMuxer_Lo(CINT_ADDR_DMA_DS_PAH)='1'
2645 
         else (Others=>'0');
2646 
 
2647 
   DMA_ds_PA_o_Lo(C_DBUS_WIDTH/2-1 downto 0)
2648 
      <= DMA_ds_PA_i(C_DBUS_WIDTH/2-1 downto 0) when Reg_RdMuxer_Lo(CINT_ADDR_DMA_DS_PAL)='1'
2649 
         else (Others=>'0');
2650 
 
2651 
   --  Host Address Start point
2652 
   DMA_ds_HA_o_Lo(C_DBUS_WIDTH-1 downto C_DBUS_WIDTH/2)
2653 
      <= DMA_ds_HA_i(C_DBUS_WIDTH-1 downto C_DBUS_WIDTH/2) when Reg_RdMuxer_Lo(CINT_ADDR_DMA_DS_HAH)='1'
2654 
         else (Others=>'0');
2655 
 
2656 
   DMA_ds_HA_o_Lo(C_DBUS_WIDTH/2-1 downto 0)
2657 
      <= DMA_ds_HA_i(C_DBUS_WIDTH/2-1 downto 0) when Reg_RdMuxer_Lo(CINT_ADDR_DMA_DS_HAL)='1'
2658 
         else (Others=>'0');
2659 
 
2660 
   --  Next Descriptor Address
2661 
   DMA_ds_BDA_o_Lo(C_DBUS_WIDTH-1 downto C_DBUS_WIDTH/2)
2662 
      <= DMA_ds_BDA_i(C_DBUS_WIDTH-1 downto C_DBUS_WIDTH/2) when Reg_RdMuxer_Lo(CINT_ADDR_DMA_DS_BDAH)='1'
2663 
         else (Others=>'0');
2664 
 
2665 
   DMA_ds_BDA_o_Lo(C_DBUS_WIDTH/2-1 downto 0)
2666 
      <= DMA_ds_BDA_i(C_DBUS_WIDTH/2-1 downto 0) when Reg_RdMuxer_Lo(CINT_ADDR_DMA_DS_BDAL)='1'
2667 
         else (Others=>'0');
2668 
 
2669 
   --  Length
2670 
   DMA_ds_Length_o_Lo(32-1 downto 0)
2671 
      <= DMA_ds_Length_i(32-1 downto 0) when Reg_RdMuxer_Lo(CINT_ADDR_DMA_DS_LENG)='1'
2672 
         else (Others=>'0');
2673 
 
2674 
   --  Control word
2675 
   DMA_ds_Control_o_Lo(32-1 downto 0)
2676 
      <= DMA_ds_Control_i(32-1 downto 0) when Reg_RdMuxer_Lo(CINT_ADDR_DMA_DS_CTRL)='1'
2677 
         else (Others=>'0');
2678 
 
2679 
   --  Status (Read only)
2680 
   DMA_ds_Status_o_Lo(32-1 downto 0)
2681 
      <= DMA_ds_Status_i(32-1 downto 0) when Reg_RdMuxer_Lo(CINT_ADDR_DMA_DS_STA)='1'
2682 
         else (Others=>'0');
2683 
 
2684 
   --  Tranferred bytes (Read only)
2685 
   DMA_ds_Transf_Bytes_o_Lo(32-1 downto 0)
2686 
      <= DMA_ds_Transf_Bytes_i(32-1 downto 0) when Reg_RdMuxer_Lo(CINT_ADDR_DS_TRANSF_BC)='1'
2687 
         else (Others=>'0');
2688 
 
2689 
 
2690 
   --------------------------------------------------------------------------
2691 
   -- CTL
2692 
   --------------------------------------------------------------------------
2693 
   ctl_td_o_Hi(32-1 downto 0)
2694 
      <= ctl_td_r(32-1 downto 0) when Reg_RdMuxer_Hi(CINT_ADDR_CTL_CLASS)='1'
2695 
         else (Others=>'0');
2696 
 
2697 
   ctl_td_o_Lo(32-1 downto 0)
2698 
      <= ctl_td_r(32-1 downto 0) when Reg_RdMuxer_Lo(CINT_ADDR_CTL_CLASS)='1'
2699 
         else (Others=>'0');
2700 
 
2701 
   --------------------------------------------------------------------------
2702 
   -- DLM
2703 
   --------------------------------------------------------------------------
2704 
   dlm_rd_o_Hi(32-1 downto 0)
2705 
      <= dlm_rd_r(32-1 downto 0) when Reg_RdMuxer_Hi(CINT_ADDR_DLM_CLASS)='1'
2706 
         else (Others=>'0');
2707 
 
2708 
   dlm_rd_o_Lo(32-1 downto 0)
2709 
      <= dlm_rd_r(32-1 downto 0) when Reg_RdMuxer_Lo(CINT_ADDR_DLM_CLASS)='1'
2710 
         else (Others=>'0');
2711 
 
2712 
 
2713 
   --------------------------------------------------------------------------
2714 
   -- System Interrupt Status
2715 
   --------------------------------------------------------------------------
2716 
   Sys_Int_Status_o_Hi(32-1 downto 0)
2717 
      <= (Sys_Int_Status_i(32-1 downto 0) and Sys_Int_Enable_i(32-1 downto 0)) when Reg_RdMuxer_Hi(CINT_ADDR_IRQ_STAT)='1'
2718 
         else (Others=>'0');
2719 
 
2720 
   Sys_Int_Enable_o_Hi(32-1 downto 0)
2721 
      <= Sys_Int_Enable_i(32-1 downto 0) when Reg_RdMuxer_Hi(CINT_ADDR_IRQ_EN)='1'
2722 
         else (Others=>'0');
2723 
 
2724 
   Sys_Int_Status_o_Lo(32-1 downto 0)
2725 
      <= (Sys_Int_Status_i(32-1 downto 0) and Sys_Int_Enable_i(32-1 downto 0)) when Reg_RdMuxer_Lo(CINT_ADDR_IRQ_STAT)='1'
2726 
         else (Others=>'0');
2727 
 
2728 
   Sys_Int_Enable_o_Lo(32-1 downto 0)
2729 
      <= Sys_Int_Enable_i(32-1 downto 0) when Reg_RdMuxer_Lo(CINT_ADDR_IRQ_EN)='1'
2730 
         else (Others=>'0');
2731 
 
2732 
 
2733 
   -- ----------------------------------------------------------------------------------
2734 
   -- ----------------------------------------------------------------------------------
2735 
   Gen_IG_Read:  if IMP_INT_GENERATOR generate
2736 
 
2737 
   --------------------------------------------------------------------------
2738 
   -- Interrupt Generator Latency
2739 
   --------------------------------------------------------------------------
2740 
   IG_Latency_o_Hi(32-1 downto 0)
2741 
      <= IG_Latency_i(32-1 downto 0) when Reg_RdMuxer_Hi(CINT_ADDR_IG_LATENCY)='1'
2742 
         else (Others=>'0');
2743 
 
2744 
   IG_Latency_o_Lo(32-1 downto 0)
2745 
      <= IG_Latency_i(32-1 downto 0) when Reg_RdMuxer_Lo(CINT_ADDR_IG_LATENCY)='1'
2746 
         else (Others=>'0');
2747 
   --------------------------------------------------------------------------
2748 
   -- Interrupt Generator Statistics
2749 
   --------------------------------------------------------------------------
2750 
   IG_Num_Assert_o_Hi(32-1 downto 0)
2751 
      <= IG_Num_Assert_i(32-1 downto 0) when Reg_RdMuxer_Hi(CINT_ADDR_IG_NUM_ASSERT)='1'
2752 
         else (Others=>'0');
2753 
 
2754 
   IG_Num_Deassert_o_Hi(32-1 downto 0)
2755 
      <= IG_Num_Deassert_i(32-1 downto 0) when Reg_RdMuxer_Hi(CINT_ADDR_IG_NUM_DEASSERT)='1'
2756 
         else (Others=>'0');
2757 
 
2758 
   IG_Num_Assert_o_Lo(32-1 downto 0)
2759 
      <= IG_Num_Assert_i(32-1 downto 0) when Reg_RdMuxer_Lo(CINT_ADDR_IG_NUM_ASSERT)='1'
2760 
         else (Others=>'0');
2761 
 
2762 
   IG_Num_Deassert_o_Lo(32-1 downto 0)
2763 
      <= IG_Num_Deassert_i(32-1 downto 0) when Reg_RdMuxer_Lo(CINT_ADDR_IG_NUM_DEASSERT)='1'
2764 
         else (Others=>'0');
2765 
 
2766 
   end generate;
2767 
 
2768 
 
2769 
   NotGen_IG_Read:  if not IMP_INT_GENERATOR generate
2770 
 
2771 
   IG_Latency_o_Hi(32-1 downto 0)      <= (Others=>'0');
2772 
   IG_Latency_o_Lo(32-1 downto 0)      <= (Others=>'0');
2773 
   IG_Num_Assert_o_Hi(32-1 downto 0)   <= (Others=>'0');
2774 
   IG_Num_Deassert_o_Hi(32-1 downto 0) <= (Others=>'0');
2775 
   IG_Num_Assert_o_Lo(32-1 downto 0)   <= (Others=>'0');
2776 
   IG_Num_Deassert_o_Lo(32-1 downto 0) <= (Others=>'0');
2777 
 
2778 
   end generate;
2779 
 
2780 
 
2781 
   --------------------------------------------------------------------------
2782 
   --  System Error
2783 
   --------------------------------------------------------------------------
2784 
   Synch_Sys_Error_i:
2785 
   process ( trn_clk, trn_lnk_up_n)
2786 
   begin
2787 
     if trn_lnk_up_n = '1' then
2788 
        Sys_Error_i                            <= (OTHERS => '0');
2789 
        eb_FIFO_OverWritten                    <= '0';
2790 
     elsif trn_clk'event and trn_clk = '1' then
2791 
        Sys_Error_i(CINT_BIT_TX_TOUT_IN_SER)   <= Tx_TimeOut;
2792 
        Sys_Error_i(CINT_BIT_EB_TOUT_IN_SER)   <= Tx_eb_TimeOut;
2793 
        Sys_Error_i(CINT_BIT_EB_OVERWRITTEN)   <= eb_FIFO_OverWritten;
2794 
        --  !!!!!!!!!!!!!! capture eb_FIFO overflow, temp cleared by MRd_Channel_Rst_i
2795 
        eb_FIFO_OverWritten      <= (not MRd_Channel_Rst_i) and (eb_FIFO_ow or eb_FIFO_OverWritten);
2796 
     end if;
2797 
   end process;
2798 
 
2799 
 
2800 
   --------------------------------------------------------------------------
2801 
   --  General Status and Control
2802 
   --------------------------------------------------------------------------
2803 
   Synch_General_Status_i:
2804 
   process ( trn_clk, trn_lnk_up_n)
2805 
   begin
2806 
     if trn_lnk_up_n = '1' then
2807 
       General_Status_i  <= (OTHERS => '0');
2808 
     elsif trn_clk'event and trn_clk = '1' then
2809 
       General_Status_i(32-1 downto 32-16)
2810 
                       <= cfg_dcommand;
2811 
       General_Status_i(CINT_BIT_LWIDTH_IN_GSR_TOP downto CINT_BIT_LWIDTH_IN_GSR_BOT)
2812 
                       <= pcie_link_width;
2813 
       General_Status_i(CINT_BIT_ICAP_BUSY_IN_GSR)
2814 
                       <= icap_Busy;
2815 
       General_Status_i(CINT_BIT_DG_AVAIL_IN_GSR)
2816 
                       <= DG_is_Available;
2817 
       General_Status_i(CINT_BIT_LINK_ACT_IN_GSR+1 downto CINT_BIT_LINK_ACT_IN_GSR)
2818 
                       <= protocol_link_act;
2819 
 
2820 
--       General_Status_i(8) <= CTL_read_counter(6-1);   ---- DEBUG !!!
2821 
     end if;
2822 
   end process;
2823 
 
2824 
 
2825 
 
2826 
   Sys_Error_o_Hi(32-1 downto 0)
2827 
      <= Sys_Error_i(32-1 downto 0) when Reg_RdMuxer_Hi(CINT_ADDR_ERROR)='1'
2828 
         else (Others=>'0');
2829 
 
2830 
   General_Status_o_Hi(32-1 downto 0)
2831 
      <= General_Status_i(32-1 downto 0) when Reg_RdMuxer_Hi(CINT_ADDR_STATUS)='1'
2832 
         else (Others=>'0');
2833 
 
2834 
   General_Control_o_Hi(32-1 downto 0)
2835 
      <= General_Control_i(32-1 downto 0) when Reg_RdMuxer_Hi(CINT_ADDR_CONTROL)='1'
2836 
         else (Others=>'0');
2837 
 
2838 
   Sys_Error_o_Lo(32-1 downto 0)
2839 
      <= Sys_Error_i(32-1 downto 0) when Reg_RdMuxer_Lo(CINT_ADDR_ERROR)='1'
2840 
         else (Others=>'0');
2841 
 
2842 
   General_Status_o_Lo(32-1 downto 0)
2843 
      <= General_Status_i(32-1 downto 0) when Reg_RdMuxer_Lo(CINT_ADDR_STATUS)='1'
2844 
         else (Others=>'0');
2845 
 
2846 
   General_Control_o_Lo(32-1 downto 0)
2847 
      <= General_Control_i(32-1 downto 0) when Reg_RdMuxer_Lo(CINT_ADDR_CONTROL)='1'
2848 
         else (Others=>'0');
2849 
 
2850 
 
2851 
   --------------------------------------------------------------------------
2852 
   -- ICAP
2853 
   --------------------------------------------------------------------------
2854 
   icap_O_o_Hi(32-1 downto 0)
2855 
      <= icap_O(32-1 downto 0) when Reg_RdMuxer_Hi(CINT_ADDR_ICAP)='1'
2856 
         else (Others=>'0');
2857 
 
2858 
   icap_O_o_Lo(32-1 downto 0)
2859 
      <= icap_O(32-1 downto 0) when Reg_RdMuxer_Lo(CINT_ADDR_ICAP)='1'
2860 
         else (Others=>'0');
2861 
 
2862 
   --------------------------------------------------------------------------
2863 
   -- FIFO Statuses (read only)
2864 
   --------------------------------------------------------------------------
2865 
   eb_FIFO_Status_o_Hi(32-1 downto 0)
2866 
      <= eb_FIFO_Status_r1(32-1 downto 0) when Reg_RdMuxer_Hi(CINT_ADDR_EB_STACON)='1'
2867 
         else (Others=>'0');
2868 
 
2869 
   eb_FIFO_Status_o_Lo(32-1 downto 0)
2870 
      <= eb_FIFO_Status_r1(32-1 downto 0) when Reg_RdMuxer_Lo(CINT_ADDR_EB_STACON)='1'
2871 
         else (Others=>'0');
2872 
 
2873 
   --------------------------------------------------------------------------
2874 
   -- Optical Link Status
2875 
   --------------------------------------------------------------------------
2876 
   Opto_Link_Status_o_Hi(32-1 downto 0)
2877 
      <= Opto_Link_Status_i(32-1 downto 0) when Reg_RdMuxer_Hi(CINT_ADDR_PROTOCOL_STACON)='1'
2878 
         else (Others=>'0');
2879 
 
2880 
   Opto_link_Status_o_Lo(32-1 downto 0)
2881 
      <= Opto_Link_Status_i(32-1 downto 0) when Reg_RdMuxer_Lo(CINT_ADDR_PROTOCOL_STACON)='1'
2882 
         else (Others=>'0');
2883 
 
2884 
   --------------------------------------------------------------------------
2885 
   -- Class CTL status
2886 
   --------------------------------------------------------------------------
2887 
   class_CTL_Status_o_Hi(32-1 downto 0)
2888 
      <= class_CTL_Status_i(32-1 downto 0) when Reg_RdMuxer_Hi(CINT_ADDR_TC_STATUS)='1'
2889 
         else (Others=>'0');
2890 
 
2891 
   class_CTL_Status_o_Lo(32-1 downto 0)
2892 
      <= class_CTL_Status_i(32-1 downto 0) when Reg_RdMuxer_Lo(CINT_ADDR_TC_STATUS)='1'
2893 
         else (Others=>'0');
2894 
 
2895 
   --------------------------------------------------------------------------
2896 
   -- Data generator Status
2897 
   --------------------------------------------------------------------------
2898 
   DG_Status_o_Hi(32-1 downto 0)
2899 
      <= DG_Status_i(32-1 downto 0) when Reg_RdMuxer_Hi(CINT_ADDR_DG_CTRL)='1'
2900 
         else (Others=>'0');
2901 
 
2902 
   DG_Status_o_Lo(32-1 downto 0)
2903 
      <= DG_Status_i(32-1 downto 0) when Reg_RdMuxer_Lo(CINT_ADDR_DG_CTRL)='1'
2904 
         else (Others=>'0');
2905 
 
2906 
   --------------------------------------------------------------------------
2907 
   -- Hardware version
2908 
   --------------------------------------------------------------------------
2909 
   HW_Version_o_Hi(32-1 downto 0)
2910 
      <= C_DESIGN_ID(32-1 downto 0) when Reg_RdMuxer_Hi(CINT_ADDR_VERSION)='1'
2911 
         else (Others=>'0');
2912 
 
2913 
   HW_Version_o_Lo(32-1 downto 0)
2914 
      <= C_DESIGN_ID(32-1 downto 0) when Reg_RdMuxer_Lo(CINT_ADDR_VERSION)='1'
2915 
         else (Others=>'0');
2916 
 
2917 
-----------------------------------------------------
2918 
-- Sequential : Regs_RdQout_i
2919 
--
2920 
   Synch_Regs_RdQout:
2921 
   process ( trn_clk, trn_lnk_up_n)
2922 
   begin
2923 
      if trn_lnk_up_n = '1' then
2924 
         Regs_RdQout_i <= (OTHERS =>'0');
2925 
 
2926 
      elsif trn_clk'event and trn_clk = '1' then
2927 
 
2928 
         Regs_RdQout_i(64-1 downto 32)        <=
2929 
                                  HW_Version_o_Hi     (32-1 downto 0)
2930 
 
2931 
                              or  Sys_Error_o_Hi      (32-1 downto 0)
2932 
                              or  General_Status_o_Hi (32-1 downto 0)
2933 
                              or  General_Control_o_Hi(32-1 downto 0)
2934 
 
2935 
                              or  Sys_Int_Status_o_Hi (32-1 downto 0)
2936 
                              or  Sys_Int_Enable_o_Hi (32-1 downto 0)
2937 
 
2938 
--                              or  DMA_us_PA_o_Hi      (C_DBUS_WIDTH-1 downto 32)
2939 
                              or  DMA_us_PA_o_Hi      (32-1   downto          0)
2940 
                              or  DMA_us_HA_o_Hi      (C_DBUS_WIDTH-1 downto 32)
2941 
                              or  DMA_us_HA_o_Hi      (32-1   downto          0)
2942 
                              or  DMA_us_BDA_o_Hi     (C_DBUS_WIDTH-1 downto 32)
2943 
                              or  DMA_us_BDA_o_Hi     (32-1   downto          0)
2944 
                              or  DMA_us_Length_o_Hi  (32-1 downto 0)
2945 
                              or  DMA_us_Control_o_Hi (32-1 downto 0)
2946 
                              or  DMA_us_Status_o_Hi  (32-1 downto 0)
2947 
                              or  DMA_us_Transf_Bytes_o_Hi  (32-1 downto 0)
2948 
 
2949 
--                              or  DMA_ds_PA_o_Hi      (C_DBUS_WIDTH-1 downto 32)
2950 
                              or  DMA_ds_PA_o_Hi      (32-1   downto          0)
2951 
                              or  DMA_ds_HA_o_Hi      (C_DBUS_WIDTH-1 downto 32)
2952 
                              or  DMA_ds_HA_o_Hi      (32-1   downto          0)
2953 
                              or  DMA_ds_BDA_o_Hi     (C_DBUS_WIDTH-1 downto 32)
2954 
                              or  DMA_ds_BDA_o_Hi     (32-1   downto          0)
2955 
                              or  DMA_ds_Length_o_Hi  (32-1 downto 0)
2956 
                              or  DMA_ds_Control_o_Hi (32-1 downto 0)
2957 
                              or  DMA_ds_Status_o_Hi  (32-1 downto 0)
2958 
                              or  DMA_ds_Transf_Bytes_o_Hi  (32-1 downto 0)
2959 
 
2960 
                              or  IG_Latency_o_Hi     (32-1 downto 0)
2961 
                              or  IG_Num_Assert_o_Hi  (32-1 downto 0)
2962 
                              or  IG_Num_Deassert_o_Hi(32-1 downto 0)
2963 
 
2964 
                              or  DG_Status_o_Hi      (32-1 downto 0)
2965 
                              or  class_CTL_Status_o_Hi  (32-1 downto 0)
2966 
 
2967 
--                              or  icap_O_o_Hi         (32-1 downto 0)
2968 
                              or  Opto_Link_Status_o_Hi (32-1 downto 0)
2969 
                              or  eb_FIFO_Status_o_Hi (32-1 downto 0)
2970 
                                                                                or  dlm_rd_o_Hi
2971 
                                                                                or  ctl_td_o_Hi
2972 
                              ;
2973 
 
2974 
 
2975 
         Regs_RdQout_i(32-1 downto 0)        <=
2976 
                                  HW_Version_o_Lo     (32-1 downto 0)
2977 
 
2978 
                              or  Sys_Error_o_Lo      (32-1 downto 0)
2979 
                              or  General_Status_o_Lo (32-1 downto 0)
2980 
                              or  General_Control_o_Lo(32-1 downto 0)
2981 
 
2982 
                              or  Sys_Int_Status_o_Lo (32-1 downto 0)
2983 
                              or  Sys_Int_Enable_o_Lo (32-1 downto 0)
2984 
 
2985 
--                              or  DMA_us_PA_o_Lo      (C_DBUS_WIDTH-1 downto 32)
2986 
                              or  DMA_us_PA_o_Lo      (32-1   downto          0)
2987 
                              or  DMA_us_HA_o_Lo      (C_DBUS_WIDTH-1 downto 32)
2988 
                              or  DMA_us_HA_o_Lo      (32-1   downto          0)
2989 
                              or  DMA_us_BDA_o_Lo     (C_DBUS_WIDTH-1 downto 32)
2990 
                              or  DMA_us_BDA_o_Lo     (32-1   downto          0)
2991 
                              or  DMA_us_Length_o_Lo  (32-1 downto 0)
2992 
                              or  DMA_us_Control_o_Lo (32-1 downto 0)
2993 
                              or  DMA_us_Status_o_Lo  (32-1 downto 0)
2994 
                              or  DMA_us_Transf_Bytes_o_Lo  (32-1 downto 0)
2995 
 
2996 
--                              or  DMA_ds_PA_o_Lo      (C_DBUS_WIDTH-1 downto 32)
2997 
                              or  DMA_ds_PA_o_Lo      (32-1   downto          0)
2998 
                              or  DMA_ds_HA_o_Lo      (C_DBUS_WIDTH-1 downto 32)
2999 
                              or  DMA_ds_HA_o_Lo      (32-1   downto          0)
3000 
                              or  DMA_ds_BDA_o_Lo     (C_DBUS_WIDTH-1 downto 32)
3001 
                              or  DMA_ds_BDA_o_Lo     (32-1   downto          0)
3002 
                              or  DMA_ds_Length_o_Lo  (32-1 downto 0)
3003 
                              or  DMA_ds_Control_o_Lo (32-1 downto 0)
3004 
                              or  DMA_ds_Status_o_Lo  (32-1 downto 0)
3005 
                              or  DMA_ds_Transf_Bytes_o_Lo  (32-1 downto 0)
3006 
 
3007 
                              or  IG_Latency_o_Lo     (32-1 downto 0)
3008 
                              or  IG_Num_Assert_o_Lo  (32-1 downto 0)
3009 
                              or  IG_Num_Deassert_o_Lo(32-1 downto 0)
3010 
 
3011 
                              or  DG_Status_o_Lo      (32-1 downto 0)
3012 
                              or  class_CTL_Status_o_Lo  (32-1 downto 0)
3013 
 
3014 
--                              or  icap_O_o_Lo(32-1 downto 0)
3015 
                              or  Opto_Link_Status_o_Lo (32-1 downto 0)
3016 
                              or  eb_FIFO_Status_o_Lo (32-1 downto 0)
3017 
                                                                                or  dlm_rd_o_Lo
3018 
                                                                                or  ctl_td_o_Lo
3019 
                              ;
3020 
 
3021 
      end if;
3022 
   end process;
3023 
 
3024 
 
3025 
-- -----------------------------------------------------------------------------
3026 
-- -- Implementation codes
3027 
-- -----------------------------------------------------------------------------
3028 
--  Gen_ICAP_width_8:
3029 
--  if C_ICAP_WIDTH=8 generate
3030 
--
3031 
--     ICAP_VIRTEX4_pcie :
3032 
--     ICAP_VIRTEX4
3033 
--       generic map (
3034 
--                    ICAP_WIDTH => "X8"    -- "X8" or "X32"
3035 
--                   )
3036 
--          port map (
3037 
--                    BUSY  => icap_BUSY ,   -- Busy output
3038 
--                    O     => icap_O    ,   -- 8-bit data output
3039 
--                    CE    => icap_CE   ,   -- Clock enable input
3040 
--                    CLK   => icap_CLK  ,   -- Clock input
3041 
--                    I     => icap_I    ,   -- 8-bit data input
3042 
--                    WRITE => icap_WRITE    -- Write input
3043 
--                   );
3044 
--
3045 
--  end generate;
3046 
--
3047 
--  Gen_ICAP_width_32:
3048 
--  if C_ICAP_WIDTH=32 generate
3049 
--
3050 
--     ICAP_VIRTEX4_pcie :
3051 
--     ICAP_VIRTEX4
3052 
--       generic map (
3053 
--                    ICAP_WIDTH => "X32"    -- "X8" or "X32"
3054 
--                   )
3055 
--          port map (
3056 
--                    BUSY  => icap_BUSY ,   -- Busy output
3057 
--                    O     => icap_O    ,   -- 32-bit data output
3058 
--                    CE    => icap_CE   ,   -- Clock enable input
3059 
--                    CLK   => icap_CLK  ,   -- Clock input
3060 
--                    I     => icap_I    ,   -- 32-bit data input
3061 
--                    WRITE => icap_WRITE    -- Write input
3062 
--                   );
3063 
--
3064 
--  end generate;
3065 
--
3066 
 
3067 
end Behavioral;

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