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[/] [pcie_sg_dma/] [trunk/] [rtl/] [Registers.vhd] - Blame information for rev 8

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Line No. Rev Author Line
1 2 weng_ziti 
----------------------------------------------------------------------------------
2 
-- Company:  ziti, Uni. HD
3 
-- Engineer:  wgao
4 
--
5 
-- Design Name:
6 
-- Module Name:    Regs_Group - Behavioral
7 
-- Project Name:
8 
-- Target Devices:
9 
-- Tool versions:
10 
-- Description:
11 
--
12 
-- Dependencies:
13 
--
14 
-- Revision:
15 
--
16 
-- Revision 1.00 - first release.  06.02.2007
17 
--
18 
-- Additional Comments:
19 
--
20 
----------------------------------------------------------------------------------
21 
 
22 
library IEEE;
23 
use IEEE.STD_LOGIC_1164.ALL;
24 
use IEEE.STD_LOGIC_ARITH.ALL;
25 
use IEEE.STD_LOGIC_UNSIGNED.ALL;
26 
 
27 
 
28 
library work;
29 
use work.abb64Package.all;
30 
 
31 
---- Uncomment the following library declaration if instantiating
32 
---- any Xilinx primitives in this code.
33 
library UNISIM;
34 
use UNISIM.VComponents.all;
35 
 
36 
entity Regs_Group is
37 
    port (
38 
 
39 3 weng_ziti 
--      -- DCB protocol interface
40 
--      protocol_link_act        : IN  std_logic_vector(2-1 downto 0);
41 
--      protocol_rst             : OUT std_logic;
42 
--
43 
--      -- Fabric side: CTL Rx
44 
--      ctl_rv                   : OUT std_logic;
45 
--      ctl_rd                   : OUT std_logic_vector(C_DBUS_WIDTH/2-1 downto 0);
46 
--
47 
--      -- Fabric side: CTL Tx
48 
--      ctl_ttake                : OUT std_logic;
49 
--      ctl_tv                   : IN  std_logic;
50 
--      ctl_td                   : IN  std_logic_vector(C_DBUS_WIDTH/2-1 downto 0);
51 
--      ctl_tstop                : OUT std_logic;
52 
--
53 
--      ctl_reset                : OUT std_logic;
54 
--      ctl_status               : IN  std_logic_vector(C_DBUS_WIDTH/2-1 downto 0);
55 
--
56 
--      -- Fabric side: DLM Rx
57 
--      dlm_tv                   : OUT std_logic;
58 
--      dlm_td                   : OUT std_logic_vector(C_DBUS_WIDTH/2-1 downto 0);
59 
--
60 
--      -- Fabric side: DLM Tx
61 
--      dlm_rv                   : IN  std_logic;
62 
--      dlm_rd                   : IN  std_logic_vector(C_DBUS_WIDTH/2-1 downto 0);
63 2 weng_ziti 
 
64 
      -- Event Buffer status + reset
65 
      eb_FIFO_Status           : IN  std_logic_vector(C_DBUS_WIDTH-1 downto 0);
66 
      eb_FIFO_Rst              : OUT std_logic;
67 
      eb_FIFO_ow               : IN  std_logic;
68 
 
69 
      self_feed_daq            : OUT std_logic;
70 
 
71 
      -- Write interface
72 
      Regs_WrEnA               : IN  std_logic;
73 
      Regs_WrMaskA             : IN  std_logic_vector(2-1 downto 0);
74 
      Regs_WrAddrA             : IN  std_logic_vector(C_EP_AWIDTH-1 downto 0);
75 
      Regs_WrDinA              : IN  std_logic_vector(C_DBUS_WIDTH-1 downto 0);
76 
 
77 
      Regs_WrEnB               : IN  std_logic;
78 
      Regs_WrMaskB             : IN  std_logic_vector(2-1 downto 0);
79 
      Regs_WrAddrB             : IN  std_logic_vector(C_EP_AWIDTH-1 downto 0);
80 
      Regs_WrDinB              : IN  std_logic_vector(C_DBUS_WIDTH-1 downto 0);
81 
 
82 
      -- Register Read interface
83 
      Regs_RdAddr              : IN  std_logic_vector(C_EP_AWIDTH-1 downto 0);
84 
      Regs_RdQout              : OUT std_logic_vector(C_DBUS_WIDTH-1 downto 0);
85 
 
86 
      -- Downstream DMA transferred bytes count up
87 
      ds_DMA_Bytes_Add         : IN  std_logic;
88 
      ds_DMA_Bytes             : IN  std_logic_vector(C_TLP_FLD_WIDTH_OF_LENG+2 downto 0);
89 
 
90 
     -- Registers to/from Downstream Engine
91 
      DMA_ds_PA                : OUT std_logic_vector(C_DBUS_WIDTH-1 downto 0);
92 
      DMA_ds_HA                : OUT std_logic_vector(C_DBUS_WIDTH-1 downto 0);
93 
      DMA_ds_BDA               : OUT std_logic_vector(C_DBUS_WIDTH-1 downto 0);
94 
      DMA_ds_Length            : OUT std_logic_vector(C_DBUS_WIDTH-1 downto 0);
95 
      DMA_ds_Control           : OUT std_logic_vector(C_DBUS_WIDTH-1 downto 0);
96 
      dsDMA_BDA_eq_Null        : OUT std_logic;      -- obsolete
97 
      DMA_ds_Status            : IN  std_logic_vector(C_DBUS_WIDTH-1 downto 0);
98 
      DMA_ds_Done              : IN  std_logic;
99 
      DMA_ds_Tout              : IN  std_logic;
100 
 
101 
      -- Calculation in advance, for better timing
102 
      dsHA_is_64b              : OUT std_logic;
103 
      dsBDA_is_64b             : OUT std_logic;
104 
 
105 
      -- Calculation in advance, for better timing
106 
      dsLeng_Hi19b_True        : OUT std_logic;
107 
      dsLeng_Lo7b_True         : OUT std_logic;
108 
 
109 
      -- Downstream Control Signals
110 
      dsDMA_Start              : OUT std_logic;
111 
      dsDMA_Stop               : OUT std_logic;
112 
      dsDMA_Start2             : OUT std_logic;
113 
      dsDMA_Stop2              : OUT std_logic;
114 
      dsDMA_Channel_Rst        : OUT std_logic;
115 
      dsDMA_Cmd_Ack            : IN  std_logic;
116 
 
117 
 
118 
      -- Upstream DMA transferred bytes count up
119 
      us_DMA_Bytes_Add         : IN  std_logic;
120 
      us_DMA_Bytes             : IN  std_logic_vector(C_TLP_FLD_WIDTH_OF_LENG+2 downto 0);
121 
 
122 
      -- Registers to/from Upstream Engine
123 
      DMA_us_PA                : OUT std_logic_vector(C_DBUS_WIDTH-1 downto 0);
124 
      DMA_us_HA                : OUT std_logic_vector(C_DBUS_WIDTH-1 downto 0);
125 
      DMA_us_BDA               : OUT std_logic_vector(C_DBUS_WIDTH-1 downto 0);
126 
      DMA_us_Length            : OUT std_logic_vector(C_DBUS_WIDTH-1 downto 0);
127 
      DMA_us_Control           : OUT std_logic_vector(C_DBUS_WIDTH-1 downto 0);
128 
      usDMA_BDA_eq_Null        : OUT std_logic;      -- obsolete
129 
      us_MWr_Param_Vec         : OUT std_logic_vector(6-1 downto 0);
130 
      DMA_us_Status            : IN  std_logic_vector(C_DBUS_WIDTH-1 downto 0);
131 
      DMA_us_Done              : IN  std_logic;
132 
      DMA_us_Tout              : IN  std_logic;
133 
 
134 
      -- Calculation in advance, for better timing
135 
      usHA_is_64b              : OUT std_logic;
136 
      usBDA_is_64b             : OUT std_logic;
137 
 
138 
      -- Calculation in advance, for better timing
139 
      usLeng_Hi19b_True        : OUT std_logic;
140 
      usLeng_Lo7b_True         : OUT std_logic;
141 
 
142 
      -- Upstream Control Signals
143 
      usDMA_Start              : OUT std_logic;
144 
      usDMA_Stop               : OUT std_logic;
145 
      usDMA_Start2             : OUT std_logic;
146 
      usDMA_Stop2              : OUT std_logic;
147 
      usDMA_Channel_Rst        : OUT std_logic;
148 
      usDMA_Cmd_Ack            : IN  std_logic;
149 
 
150 
      -- MRd Channel Reset
151 
      MRd_Channel_Rst          : OUT std_logic;
152 
 
153 
      -- Tx module reset
154 
      Tx_Reset                 : OUT std_logic;
155 
 
156 
                -- to Interrupts Module
157 
      Sys_IRQ                  : OUT std_logic_vector(C_DBUS_WIDTH-1 downto 0);
158 3 weng_ziti 
--      DAQ_irq                  : IN  std_logic;
159 
--      CTL_irq                  : IN  std_logic;
160 
--      DLM_irq                  : IN  std_logic;
161 2 weng_ziti 
 
162 
      -- System error and info
163 
      Tx_TimeOut               : IN  std_logic;
164 
      Tx_eb_TimeOut            : IN  std_logic;
165 
      Msg_Routing              : OUT std_logic_vector(C_GCR_MSG_ROUT_BIT_TOP-C_GCR_MSG_ROUT_BIT_BOT downto 0);
166 
      pcie_link_width          : IN  std_logic_vector(CINT_BIT_LWIDTH_IN_GSR_TOP-CINT_BIT_LWIDTH_IN_GSR_BOT downto 0);
167 
      cfg_dcommand             : IN  std_logic_vector(16-1 downto 0);
168 
 
169 
      -- Interrupt Generation Signals
170 
      IG_Reset                 : OUT std_logic;
171 
      IG_Host_Clear            : OUT std_logic;
172 
      IG_Latency               : OUT std_logic_vector(C_DBUS_WIDTH-1 downto 0);
173 
      IG_Num_Assert            : IN  std_logic_vector(C_DBUS_WIDTH-1 downto 0);
174 
      IG_Num_Deassert          : IN  std_logic_vector(C_DBUS_WIDTH-1 downto 0);
175 
      IG_Asserting             : IN  std_logic;
176 
 
177 3 weng_ziti 
--      -- Data generator control
178 
--      DG_is_Running            : IN  std_logic;
179 
--      DG_Reset                 : OUT std_logic;
180 
--      DG_Mask                  : OUT std_logic;
181 2 weng_ziti 
 
182 
      -- Clock and reset
183 
      trn_clk                  : IN  std_logic;
184 
      trn_lnk_up_n             : IN  std_logic;
185 
      trn_reset_n              : IN  std_logic
186 
 
187 
    );
188 
end Regs_Group;
189 
 
190 
 
191 
architecture Behavioral of Regs_Group is
192 
 
193 
  ----------------------------------------------------------------------------
194 
  ----------------------------------------------------------------------------
195 
  signal  Regs_WrDin_i         : std_logic_vector(C_DBUS_WIDTH-1   downto 0);
196 
  signal  Regs_WrAddr_i        : std_logic_vector(C_EP_AWIDTH-1   downto 0);
197 
  signal  Regs_WrMask_i        : std_logic_vector(2-1   downto 0);
198 
 
199 
  ------  Delay signals
200 
  signal  Regs_WrEn_r1         : std_logic;
201 
  signal  Regs_WrAddr_r1       : std_logic_vector(C_EP_AWIDTH-1   downto 0);
202 
  signal  Regs_WrMask_r1       : std_logic_vector(2-1   downto 0);
203 
  signal  Regs_WrDin_r1        : std_logic_vector(C_DBUS_WIDTH-1   downto 0);
204 
  signal  Regs_WrEn_r2         : std_logic;
205 
  signal  Regs_WrDin_r2        : std_logic_vector(C_DBUS_WIDTH-1   downto 0);
206 
  signal  Regs_Wr_dma_V_hi_r2     : std_logic;
207 
  signal  Regs_Wr_dma_nV_hi_r2    : std_logic;
208 
  signal  Regs_Wr_dma_V_nE_hi_r2  : std_logic;
209 
  signal  Regs_Wr_dma_V_lo_r2     : std_logic;
210 
  signal  Regs_Wr_dma_nV_lo_r2    : std_logic;
211 
  signal  Regs_Wr_dma_V_nE_lo_r2  : std_logic;
212 
  signal  WrDin_r1_not_Zero_Hi    : std_logic_vector(4-1 downto 0);
213 
  signal  WrDin_r2_not_Zero_Hi    : std_logic;
214 
  signal  WrDin_r1_not_Zero_Lo    : std_logic_vector(4-1 downto 0);
215 
  signal  WrDin_r2_not_Zero_Lo    : std_logic;
216 
 
217 
  --      Calculation in advance, just for better timing
218 
  signal  Regs_WrDin_Hi19b_True_hq_r2 : std_logic;
219 
  signal  Regs_WrDin_Lo7b_True_hq_r2  : std_logic;
220 
  signal  Regs_WrDin_Hi19b_True_lq_r2 : std_logic;
221 
  signal  Regs_WrDin_Lo7b_True_lq_r2  : std_logic;
222 
 
223 
  signal  Regs_WrEnA_r1           : std_logic;
224 
  signal  Regs_WrEnB_r1           : std_logic;
225 
  signal  Regs_WrEnA_r2           : std_logic;
226 
  signal  Regs_WrEnB_r2           : std_logic;
227 
 
228 
  --      Register write mux signals
229 
  signal  Reg_WrMuxer_Hi          : std_logic_vector(C_NUM_OF_ADDRESSES-1 downto 0);
230 
  signal  Reg_WrMuxer_Lo          : std_logic_vector(C_NUM_OF_ADDRESSES-1 downto 0);
231 
 
232 
 
233 
  -- Signals for Tx reading
234 
  signal  Regs_RdAddr_i           : std_logic_vector(C_EP_AWIDTH-1   downto 0);
235 
  signal  Regs_RdQout_i           : std_logic_vector(C_DBUS_WIDTH-1   downto 0);
236 
 
237 
  --      Register read mux signals
238 
  signal  Reg_RdMuxer_Hi          : std_logic_vector(C_NUM_OF_ADDRESSES-1 downto 0);
239 
  signal  Reg_RdMuxer_Lo          : std_logic_vector(C_NUM_OF_ADDRESSES-1 downto 0);
240 
 
241 3 weng_ziti 
--  -- Optical Link status
242 
--  signal  Opto_Link_Status_i      : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
243 
--  signal  Opto_Link_Status_o_Hi   : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
244 
--  signal  Opto_Link_Status_o_Lo   : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
245 2 weng_ziti 
  -- Event Buffer
246 
  signal  eb_FIFO_Status_r1       : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
247 
  signal  eb_FIFO_Status_o_Hi     : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
248 
  signal  eb_FIFO_Status_o_Lo     : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
249 
  signal  eb_FIFO_Rst_i           : std_logic;
250 
  signal  eb_FIFO_Rst_b1          : std_logic;
251 
  signal  eb_FIFO_Rst_b2          : std_logic;
252 
  signal  eb_FIFO_Rst_b3          : std_logic;
253 
  signal  eb_FIFO_OverWritten     : std_logic;
254 
 
255 
  -- Downstream DMA registers
256 
  signal  DMA_ds_PA_o_Hi          : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
257 
  signal  DMA_ds_HA_o_Hi          : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
258 
  signal  DMA_ds_BDA_o_Hi         : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
259 
  signal  DMA_ds_Length_o_Hi      : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
260 
  signal  DMA_ds_Control_o_Hi     : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
261 
  signal  DMA_ds_Status_o_Hi      : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
262 
  signal  DMA_ds_Transf_Bytes_o_Hi      : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
263 
  signal  DMA_ds_PA_o_Lo          : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
264 
  signal  DMA_ds_HA_o_Lo          : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
265 
  signal  DMA_ds_BDA_o_Lo         : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
266 
  signal  DMA_ds_Length_o_Lo      : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
267 
  signal  DMA_ds_Control_o_Lo     : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
268 
  signal  DMA_ds_Status_o_Lo      : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
269 
  signal  DMA_ds_Transf_Bytes_o_Lo      : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
270 
 
271 
  -- Upstream DMA registers
272 
  signal  DMA_us_PA_o_Hi          : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
273 
  signal  DMA_us_HA_o_Hi          : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
274 
  signal  DMA_us_BDA_o_Hi         : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
275 
  signal  DMA_us_Length_o_Hi      : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
276 
  signal  DMA_us_Control_o_Hi     : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
277 
  signal  DMA_us_Status_o_Hi      : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
278 
  signal  DMA_us_Transf_Bytes_o_Hi      : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
279 
  signal  DMA_us_PA_o_Lo          : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
280 
  signal  DMA_us_HA_o_Lo          : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
281 
  signal  DMA_us_BDA_o_Lo         : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
282 
  signal  DMA_us_Length_o_Lo      : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
283 
  signal  DMA_us_Control_o_Lo     : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
284 
  signal  DMA_us_Status_o_Lo      : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
285 
  signal  DMA_us_Transf_Bytes_o_Lo      : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
286 
 
287 
 
288 
  -- System Interrupt Status/Control
289 
  signal  Sys_IRQ_i               : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
290 
  signal  Sys_Int_Status_i        : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
291 
  signal  Sys_Int_Status_o_Hi     : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
292 
  signal  Sys_Int_Status_o_Lo     : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
293 
 
294 
  signal  Sys_Int_Enable_i        : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
295 
  signal  Sys_Int_Enable_o_Hi     : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
296 
  signal  Sys_Int_Enable_o_Lo     : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
297 
 
298 
 
299 3 weng_ziti 
--  -- Data generator control
300 
--  signal  DG_Reset_i              : std_logic;
301 
--  signal  DG_Mask_i               : std_logic;
302 
--  signal  DG_is_Available         : std_logic;
303 
--  signal  DG_Rst_Counter          : std_logic_vector(8-1 downto 0);
304 
--  signal  DG_Status_i             : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
305 
--  signal  DG_Status_o_Hi          : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
306 
--  signal  DG_Status_o_Lo          : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
307 2 weng_ziti 
 
308 
  -- General Control and Status
309 
  signal  Sys_Error_i             : std_logic_vector(C_DBUS_WIDTH-1   downto 0);
310 
  signal  Sys_Error_o_Hi          : std_logic_vector(C_DBUS_WIDTH-1   downto 0);
311 
  signal  Sys_Error_o_Lo          : std_logic_vector(C_DBUS_WIDTH-1   downto 0);
312 
 
313 
  signal  General_Control_i       : std_logic_vector(C_DBUS_WIDTH-1   downto 0);
314 
  signal  General_Control_o_Hi    : std_logic_vector(C_DBUS_WIDTH-1   downto 0);
315 
  signal  General_Control_o_Lo    : std_logic_vector(C_DBUS_WIDTH-1   downto 0);
316 
 
317 
  signal  General_Status_i        : std_logic_vector(C_DBUS_WIDTH-1   downto 0);
318 
  signal  General_Status_o_Hi     : std_logic_vector(C_DBUS_WIDTH-1   downto 0);
319 
  signal  General_Status_o_Lo     : std_logic_vector(C_DBUS_WIDTH-1   downto 0);
320 
 
321 
  -- Hardward version
322 
  signal  HW_Version_o_Hi         : std_logic_vector(C_DBUS_WIDTH-1   downto 0);
323 
  signal  HW_Version_o_Lo         : std_logic_vector(C_DBUS_WIDTH-1   downto 0);
324 
 
325 
  -- Signal as the source of interrupts
326 
  signal  IG_Host_Clear_i         : std_logic;
327 
  signal  IG_Reset_i              : std_logic;
328 
 
329 
  -- Interrupt Generator Control
330 
  signal  IG_Control_i            : std_logic_vector(C_DBUS_WIDTH-1   downto 0);
331 
 
332 
  -- Interrupt Generator Latency
333 
  signal  IG_Latency_i            : std_logic_vector(C_DBUS_WIDTH-1   downto 0);
334 
  signal  IG_Latency_o_Hi         : std_logic_vector(C_DBUS_WIDTH-1   downto 0);
335 
  signal  IG_Latency_o_Lo         : std_logic_vector(C_DBUS_WIDTH-1   downto 0);
336 
 
337 
  -- Interrupt Generator Statistic: Assert number
338 
  signal  IG_Num_Assert_i         : std_logic_vector(C_DBUS_WIDTH-1   downto 0);
339 
  signal  IG_Num_Assert_o_Hi      : std_logic_vector(C_DBUS_WIDTH-1   downto 0);
340 
  signal  IG_Num_Assert_o_Lo      : std_logic_vector(C_DBUS_WIDTH-1   downto 0);
341 
 
342 
  -- Interrupt Generator Statistic: Deassert number
343 
  signal  IG_Num_Deassert_i       : std_logic_vector(C_DBUS_WIDTH-1   downto 0);
344 
  signal  IG_Num_Deassert_o_Hi    : std_logic_vector(C_DBUS_WIDTH-1   downto 0);
345 
  signal  IG_Num_Deassert_o_Lo    : std_logic_vector(C_DBUS_WIDTH-1   downto 0);
346 
 
347 
  -- IntClr character is written
348 
  signal  Command_is_Host_iClr_Hi : std_logic;
349 
  signal  Command_is_Host_iClr_Lo : std_logic;
350 
 
351 
  -- Downstream Registers
352 
  signal  DMA_ds_PA_i          : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
353 
  signal  DMA_ds_HA_i          : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
354 
  signal  DMA_ds_BDA_i         : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
355 
  signal  DMA_ds_Length_i      : std_logic_vector(C_DBUS_WIDTH-1   downto 0);
356 
  signal  DMA_ds_Control_i     : std_logic_vector(C_DBUS_WIDTH-1   downto 0);
357 
  signal  DMA_ds_Status_i      : std_logic_vector(C_DBUS_WIDTH-1   downto 0);
358 
  signal  DMA_ds_Transf_Bytes_i      : std_logic_vector(C_DBUS_WIDTH-1   downto 0);
359 
 
360 
  signal  Last_Ctrl_Word_ds    : std_logic_vector(C_DBUS_WIDTH-1   downto 0);
361 
 
362 
  -- Calculation in advance, for better timing
363 
  signal  dsHA_is_64b_i        : std_logic;
364 
  signal  dsBDA_is_64b_i       : std_logic;
365 
 
366 
  -- Calculation in advance, for better timing
367 
  signal  dsLeng_Hi19b_True_i  : std_logic;
368 
  signal  dsLeng_Lo7b_True_i   : std_logic;
369 
 
370 
  -- Downstream Control Signals
371 
  signal  dsDMA_Start_i        : std_logic;
372 
  signal  dsDMA_Stop_i         : std_logic;
373 
  signal  dsDMA_Start2_i       : std_logic;
374 
  signal  dsDMA_Start2_r1      : std_logic;
375 
  signal  dsDMA_Stop2_i        : std_logic;
376 
  signal  dsDMA_Channel_Rst_i  : std_logic;
377 
  signal  ds_Param_Modified    : std_logic;
378 
 
379 
 
380 
  -- Upstream Registers
381 
  signal  DMA_us_PA_i          : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
382 
  signal  DMA_us_HA_i          : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
383 
  signal  DMA_us_BDA_i         : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
384 
  signal  DMA_us_Length_i      : std_logic_vector(C_DBUS_WIDTH-1   downto 0);
385 
  signal  DMA_us_Control_i     : std_logic_vector(C_DBUS_WIDTH-1   downto 0);
386 
  signal  DMA_us_Status_i      : std_logic_vector(C_DBUS_WIDTH-1   downto 0);
387 
  signal  DMA_us_Transf_Bytes_i      : std_logic_vector(C_DBUS_WIDTH-1   downto 0);
388 
 
389 
  signal  Last_Ctrl_Word_us    : std_logic_vector(C_DBUS_WIDTH-1   downto 0);
390 
 
391 
  -- Calculation in advance, for better timing
392 
  signal  usHA_is_64b_i        : std_logic;
393 
  signal  usBDA_is_64b_i       : std_logic;
394 
 
395 
  -- Calculation in advance, for better timing
396 
  signal  usLeng_Hi19b_True_i  : std_logic;
397 
  signal  usLeng_Lo7b_True_i   : std_logic;
398 
 
399 
 
400 
  -- Upstream Control Signals
401 
  signal  usDMA_Start_i        : std_logic;
402 
  signal  usDMA_Stop_i         : std_logic;
403 
  signal  usDMA_Start2_i       : std_logic;
404 
  signal  usDMA_Start2_r1      : std_logic;
405 
  signal  usDMA_Stop2_i        : std_logic;
406 
  signal  usDMA_Channel_Rst_i  : std_logic;
407 
  signal  us_Param_Modified    : std_logic;
408 
 
409 
  -- Reset character is written
410 
  signal  Command_is_Reset_Hi  : std_logic;
411 
  signal  Command_is_Reset_Lo  : std_logic;
412 
 
413 
  -- MRd channel reset
414 
  signal  MRd_Channel_Rst_i    : std_logic;
415 
 
416 
  -- Tx module reset
417 
  signal  Tx_Reset_i           : std_logic;
418 
 
419 
 
420 
  -- ICAP
421 
  signal  icap_CLK             : std_logic;
422 
  signal  icap_I               : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
423 
  signal  icap_CE              : std_logic;
424 
  signal  icap_Write           : std_logic;
425 
  signal  icap_O               : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
426 
  signal  icap_O_o_Hi          : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
427 
  signal  icap_O_o_Lo          : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
428 
  signal  icap_BUSY            : std_logic;
429 
 
430 
  -- DCB protocol interface
431 
  signal  protocol_rst_i       : std_logic;
432 
  signal  protocol_rst_b1      : std_logic;
433 
  signal  protocol_rst_b2      : std_logic;
434 
 
435 
  -- Protocol : CTL
436 
  signal  ctl_rv_i             : std_logic;
437 
  signal  ctl_rd_i             : std_logic_vector(C_DBUS_WIDTH/2-1 downto 0);
438 
 
439 
  signal  class_CTL_Status_i   : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
440 
  signal  class_CTL_Status_o_Hi: std_logic_vector(C_DBUS_WIDTH-1 downto 0);
441 
  signal  class_CTL_Status_o_Lo: std_logic_vector(C_DBUS_WIDTH-1 downto 0);
442 
 
443 
  signal  ctl_td_o_Hi          : std_logic_vector(C_DBUS_WIDTH/2-1 downto 0);
444 
  signal  ctl_td_o_Lo          : std_logic_vector(C_DBUS_WIDTH/2-1 downto 0);
445 
  signal  ctl_td_r             : std_logic_vector(C_DBUS_WIDTH/2-1 downto 0);
446 
 
447 
  signal  ctl_reset_i          : std_logic;
448 
  signal  ctl_ttake_i          : std_logic;
449 
  signal  ctl_tstop_i          : std_logic;
450 
  signal  ctl_t_read_Hi_r1     : std_logic;
451 
  signal  ctl_t_read_Lo_r1     : std_logic;
452 
  signal  CTL_read_counter     : std_logic_vector(6-1 downto 0);
453 
 
454 
  -- Protocol : DLM
455 
  signal  dlm_tv_i             : std_logic;
456 
  signal  dlm_td_i             : std_logic_vector(C_DBUS_WIDTH/2-1 downto 0);
457 
 
458 
  signal  dlm_rd_o_Hi          : std_logic_vector(C_DBUS_WIDTH/2-1 downto 0);
459 
  signal  dlm_rd_o_Lo          : std_logic_vector(C_DBUS_WIDTH/2-1 downto 0);
460 
  signal  dlm_rd_r             : std_logic_vector(C_DBUS_WIDTH/2-1 downto 0);
461 
 
462 
begin
463 
 
464 
 
465 3 weng_ziti 
--   DG_is_Available   <= '0';
466 2 weng_ziti 
 
467 3 weng_ziti 
--   -- protocol interface reset
468 
--   protocol_rst         <= protocol_rst_i;
469 
--
470 
--   ctl_rv               <= ctl_rv_i;
471 
--   ctl_rd               <= ctl_rd_i;
472 
--
473 
--   ctl_ttake            <= ctl_ttake_i;
474 
--   ctl_tstop            <= ctl_tstop_i;
475 
--   ctl_reset            <= ctl_reset_i;
476 
--
477 
--   ctl_tstop_i          <= '0';   -- ???
478 
--
479 
--   dlm_tv               <= dlm_tv_i;
480 
--   dlm_td               <= dlm_td_i;
481 2 weng_ziti 
 
482 3 weng_ziti 
--   -- Data generator control
483 
--   DG_Reset             <= DG_Reset_i;
484 
--   DG_Mask              <= DG_Mask_i;
485 2 weng_ziti 
 
486 
   -- Event buffer reset
487 
   eb_FIFO_Rst          <= eb_FIFO_Rst_i;
488 
 
489 
   -- MRd channel reset
490 
   MRd_Channel_Rst      <= MRd_Channel_Rst_i;
491 
 
492 
   -- Tx module reset
493 
   Tx_Reset             <= Tx_Reset_i;
494 
 
495 
   -- Upstream DMA engine reset
496 
   usDMA_Channel_Rst    <= usDMA_Channel_Rst_i;
497 
 
498 
   -- Downstream DMA engine reset
499 
   dsDMA_Channel_Rst    <= dsDMA_Channel_Rst_i;
500 
 
501 
 
502 
   -- Upstream DMA registers
503 
   DMA_us_PA            <= DMA_us_PA_i;
504 
   DMA_us_HA            <= DMA_us_HA_i;
505 
   DMA_us_BDA           <= DMA_us_BDA_i;
506 
   DMA_us_Length        <= DMA_us_Length_i;
507 
   DMA_us_Control       <= DMA_us_Control_i;
508 
   usDMA_BDA_eq_Null    <= '0';
509 
   DMA_us_Status_i      <= DMA_us_Status;
510 
 
511 
   usHA_is_64b          <= usHA_is_64b_i;
512 
   usBDA_is_64b         <= usBDA_is_64b_i;
513 
 
514 
   usLeng_Hi19b_True    <= usLeng_Hi19b_True_i;
515 
   usLeng_Lo7b_True     <= usLeng_Lo7b_True_i;
516 
 
517 
   usDMA_Start          <= usDMA_Start_i;
518 
   usDMA_Stop           <= usDMA_Stop_i;
519 
   usDMA_Start2         <= usDMA_Start2_r1;
520 
--   usDMA_Start2         <= usDMA_Start2_i;
521 
   usDMA_Stop2          <= usDMA_Stop2_i;
522 
 
523 
   -- Downstream DMA registers
524 
   DMA_ds_PA            <= DMA_ds_PA_i;
525 
   DMA_ds_HA            <= DMA_ds_HA_i;
526 
   DMA_ds_BDA           <= DMA_ds_BDA_i;
527 
   DMA_ds_Length        <= DMA_ds_Length_i;
528 
   DMA_ds_Control       <= DMA_ds_Control_i;
529 
   dsDMA_BDA_eq_Null    <= '0';
530 
   DMA_ds_Status_i      <= DMA_ds_Status;
531 
 
532 
   dsHA_is_64b          <= dsHA_is_64b_i;
533 
   dsBDA_is_64b         <= dsBDA_is_64b_i;
534 
 
535 
   dsLeng_Hi19b_True    <= dsLeng_Hi19b_True_i;
536 
   dsLeng_Lo7b_True     <= dsLeng_Lo7b_True_i;
537 
 
538 
   dsDMA_Start          <= dsDMA_Start_i;
539 
   dsDMA_Stop           <= dsDMA_Stop_i;
540 
   dsDMA_Start2         <= dsDMA_Start2_r1;
541 
--   dsDMA_Start2         <= dsDMA_Start2_i;
542 
   dsDMA_Stop2          <= dsDMA_Stop2_i;
543 
 
544 
 
545 
   -- Register to Interrupt handler module
546 
   Sys_IRQ              <= Sys_IRQ_i;
547 
 
548 
   -- Message routing method
549 
   Msg_Routing          <= General_Control_i(C_GCR_MSG_ROUT_BIT_TOP downto C_GCR_MSG_ROUT_BIT_BOT);
550 
 
551 
   -- us_MWr_TLP_Param
552 
   us_MWr_Param_Vec     <= General_Control_i(13 downto 8);
553 
 
554 
   self_feed_daq        <= General_Control_i(16);
555 
 
556 
 
557 
   -- -------------   Interrupt generator generation    ----------------------
558 
   Gen_IG:  if IMP_INT_GENERATOR generate
559 
 
560 
   IG_Reset             <= IG_Reset_i;
561 
   IG_Host_Clear        <= IG_Host_Clear_i;  -- and Sys_Int_Enable_i(CINT_BIT_INTGEN_IN_ISR);
562 
   IG_Latency           <= IG_Latency_i;
563 
   IG_Num_Assert_i      <= IG_Num_Assert;
564 
   IG_Num_Deassert_i    <= IG_Num_Deassert;
565 
 
566 
 
567 
-- -----------------------------------------------
568 
-- Synchronous Registered: IG_Control_i
569 
   SysReg_IntGen_Control:
570 
   process ( trn_clk, trn_lnk_up_n)
571 
   begin
572 
      if trn_lnk_up_n = '1' then
573 
         IG_Control_i          <= (OTHERS => '0');
574 
         IG_Reset_i            <= '1';
575 
         IG_Host_Clear_i       <= '0';
576 
 
577 
      elsif trn_clk'event and trn_clk = '1' then
578 
 
579 
        if Regs_WrEn_r2='1'
580 
                    and Reg_WrMuxer_Hi(CINT_ADDR_IG_CONTROL)='1'
581 
                         then
582 
            IG_Control_i(32-1 downto 0)       <=  Regs_WrDin_r2(64-1 downto 32);
583 
            IG_Reset_i         <=  Command_is_Reset_Hi;
584 
            IG_Host_Clear_i    <=  Command_is_Host_iClr_Hi;
585 
        elsif Regs_WrEn_r2='1'
586 
                    and Reg_WrMuxer_Lo(CINT_ADDR_IG_CONTROL)='1'
587 
                         then
588 
            IG_Control_i(32-1 downto 0)       <=  Regs_WrDin_r2(32-1 downto 0);
589 
            IG_Reset_i         <=  Command_is_Reset_Lo;
590 
            IG_Host_Clear_i    <=  Command_is_Host_iClr_Lo;
591 
        else
592 
            IG_Control_i       <=  IG_Control_i;
593 
            IG_Reset_i         <=  '0';
594 
            IG_Host_Clear_i    <=  '0';
595 
        end if;
596 
 
597 
      end if;
598 
   end process;
599 
 
600 
 
601 
-- -----------------------------------------------
602 
-- Synchronous Registered: IG_Latency_i
603 
   SysReg_IntGen_Latency:
604 
   process ( trn_clk, trn_lnk_up_n)
605 
   begin
606 
      if trn_lnk_up_n = '1' then
607 
         IG_Latency_i       <= (OTHERS => '0');
608 
 
609 
      elsif trn_clk'event and trn_clk = '1' then
610 
 
611 
        if IG_Reset_i='1' then
612 
            IG_Latency_i    <=  (OTHERS => '0');
613 
        elsif Regs_WrEn_r2='1'
614 
                    and Reg_WrMuxer_Hi(CINT_ADDR_IG_LATENCY)='1'
615 
                         then
616 
            IG_Latency_i(32-1 downto 0)    <=  Regs_WrDin_r2(64-1 downto 32);
617 
        elsif Regs_WrEn_r2='1'
618 
                    and Reg_WrMuxer_Lo(CINT_ADDR_IG_LATENCY)='1'
619 
                         then
620 
            IG_Latency_i(32-1 downto 0)    <=  Regs_WrDin_r2(32-1 downto 0);
621 
        else
622 
            IG_Latency_i    <=  IG_Latency_i;
623 
        end if;
624 
 
625 
      end if;
626 
   end process;
627 
 
628 
   end generate;
629 
 
630 
   NotGen_IG:  if not IMP_INT_GENERATOR generate
631 
 
632 
   IG_Reset             <= '0';
633 
   IG_Host_Clear        <= '0';
634 
   IG_Latency           <= (OTHERS=>'0');
635 
   IG_Num_Assert_i      <= (OTHERS=>'0');
636 
   IG_Num_Deassert_i    <= (OTHERS=>'0');
637 
 
638 
   IG_Control_i         <= (OTHERS=>'0');
639 
   IG_Reset_i           <= '0';
640 
   IG_Host_Clear_i      <= '0';
641 
   IG_Latency_i         <= (OTHERS=>'0');
642 
 
643 
   end generate;
644 
 
645 
 
646 
 
647 
-- ----------------------------------------------
648 
-- Synchronous Delay : Sys_IRQ_i
649 
--
650 
   Synch_Delay_Sys_IRQ:
651 
   process ( trn_clk, trn_lnk_up_n )
652 
   begin
653 
      if trn_lnk_up_n = '1' then
654 
         Sys_IRQ_i   <=  (OTHERS=>'0');
655 
 
656 
      elsif trn_clk'event and trn_clk = '1' then
657 
         Sys_IRQ_i(C_NUM_OF_INTERRUPTS-1 downto 0)
658 
                     <= Sys_Int_Enable_i(C_NUM_OF_INTERRUPTS-1 downto 0)
659 
                    and Sys_Int_Status_i(C_NUM_OF_INTERRUPTS-1 downto 0);
660 
 
661 
      end if;
662 
   end process;
663 
 
664 
 
665 
-- ----------------------------------------------
666 
-- Registers writing
667 
--
668 
   Regs_WrAddr_i        <= Regs_WrAddrA and Regs_WrAddrB;
669 
   Regs_WrMask_i        <= Regs_WrMaskA or  Regs_WrMaskB;
670 
   Regs_WrDin_i         <= Regs_WrDinA  or  Regs_WrDinB;
671 
 
672 
-- ----------------------------------------------
673 
-- Registers reading
674 
--
675 
   Regs_RdAddr_i        <= Regs_RdAddr;
676 
   Regs_RdQout          <= Regs_RdQout_i;
677 
 
678 
-- ----------------------------------------------
679 
-- Synchronous Delay : Regs_WrEn
680 
--
681 
   Synch_Delay_Regs_WrEn:
682 
   process ( trn_clk )
683 
   begin
684 
      if trn_clk'event and trn_clk = '1' then
685 
         Regs_WrEn_r1   <= Regs_WrEnA or Regs_WrEnB;
686 
         Regs_WrEn_r2   <= Regs_WrEn_r1;
687 
 
688 
         Regs_WrEnA_r1  <= Regs_WrEnA;
689 
         Regs_WrEnA_r2  <= Regs_WrEnA_r1;
690 
 
691 
         Regs_WrEnB_r1  <= Regs_WrEnB;
692 
         Regs_WrEnB_r2  <= Regs_WrEnB_r1;
693 
 
694 
      end if;
695 
   end process;
696 
 
697 3 weng_ziti 
---- ----------------------------------------------
698 
---- Synchronous Delay : Opto_Link_Status
699 
----
700 
--   Synch_Delay_Opto_Link_Status:
701 
--   process ( trn_clk )
702 
--   begin
703 
--      if trn_clk'event and trn_clk = '1' then
704 
--         Opto_Link_Status_i(C_DBUS_WIDTH-1 downto 2)   <= (OTHERS=>'0');
705 
--         Opto_Link_Status_i(2-1 downto 0)   <= protocol_link_act;
706 
--      end if;
707 
--   end process;
708 2 weng_ziti 
 
709 
-- ----------------------------------------------
710 
-- Synchronous Delay : eb_FIFO_Status
711 
--
712 
   Synch_Delay_eb_FIFO_Status:
713 
   process ( trn_clk )
714 
   begin
715 
      if trn_clk'event and trn_clk = '1' then
716 
         eb_FIFO_Status_r1   <= eb_FIFO_Status;
717 
      end if;
718 
   end process;
719 
 
720 
-- ----------------------------------------------
721 
-- Synchronous Delay : Regs_WrAddr
722 
--
723 
   Synch_Delay_Regs_WrAddr:
724 
   process ( trn_clk )
725 
   begin
726 
      if trn_clk'event and trn_clk = '1' then
727 
         Regs_WrAddr_r1   <= Regs_WrAddr_i;
728 
         Regs_WrMask_r1   <= Regs_WrMask_i;
729 
      end if;
730 
   end process;
731 
 
732 
-- ----------------------------------------------------
733 
-- Synchronous Delay : dsDMA_Start2
734 
--                     usDMA_Start2
735 
--   (Special recipe for 64-bit successive descriptors)
736 
--
737 
   Synch_Delay_DMA_Start2:
738 
   process ( trn_clk )
739 
   begin
740 
      if trn_clk'event and trn_clk = '1' then
741 
         dsDMA_Start2_r1   <= dsDMA_Start2_i and not dsDMA_Cmd_Ack;
742 
         usDMA_Start2_r1   <= usDMA_Start2_i and not usDMA_Cmd_Ack;
743 
      end if;
744 
   end process;
745 
 
746 
 
747 
-- ----------------------------------------------
748 
-- Synchronous Delay : Regs_WrDin_i
749 
--
750 
   Synch_Delay_Regs_WrDin:
751 
   process ( trn_clk )
752 
   begin
753 
      if trn_clk'event and trn_clk = '1' then
754 
         Regs_WrDin_r1   <= Regs_WrDin_i;
755 
         Regs_WrDin_r2   <= Regs_WrDin_r1;
756 
 
757 
         if Regs_WrDin_i(31+32 downto 24+32) = C_ALL_ZEROS(31+32 downto 24+32) then
758 
            WrDin_r1_not_Zero_Hi(3) <= '0';
759 
         else
760 
            WrDin_r1_not_Zero_Hi(3) <= '1';
761 
         end if;
762 
         if Regs_WrDin_i(23+32 downto 16+32) = C_ALL_ZEROS(23+32 downto 16+32) then
763 
            WrDin_r1_not_Zero_Hi(2) <= '0';
764 
         else
765 
            WrDin_r1_not_Zero_Hi(2) <= '1';
766 
         end if;
767 
         if Regs_WrDin_i(15+32 downto 8+32) = C_ALL_ZEROS(15+32 downto 8+32) then
768 
            WrDin_r1_not_Zero_Hi(1) <= '0';
769 
         else
770 
            WrDin_r1_not_Zero_Hi(1) <= '1';
771 
         end if;
772 
         if Regs_WrDin_i(7+32 downto 0+32) = C_ALL_ZEROS(7+32 downto 0+32) then
773 
            WrDin_r1_not_Zero_Hi(0) <= '0';
774 
         else
775 
            WrDin_r1_not_Zero_Hi(0) <= '1';
776 
         end if;
777 
 
778 
         if WrDin_r1_not_Zero_Hi = C_ALL_ZEROS(3 downto 0) then
779 
            WrDin_r2_not_Zero_Hi <= '0';
780 
         else
781 
            WrDin_r2_not_Zero_Hi <= '1';
782 
         end if;
783 
 
784 
 
785 
         if Regs_WrDin_i(31 downto 24) = C_ALL_ZEROS(31 downto 24) then
786 
            WrDin_r1_not_Zero_Lo(3) <= '0';
787 
         else
788 
            WrDin_r1_not_Zero_Lo(3) <= '1';
789 
         end if;
790 
         if Regs_WrDin_i(23 downto 16) = C_ALL_ZEROS(23 downto 16) then
791 
            WrDin_r1_not_Zero_Lo(2) <= '0';
792 
         else
793 
            WrDin_r1_not_Zero_Lo(2) <= '1';
794 
         end if;
795 
         if Regs_WrDin_i(15 downto 8) = C_ALL_ZEROS(15 downto 8) then
796 
            WrDin_r1_not_Zero_Lo(1) <= '0';
797 
         else
798 
            WrDin_r1_not_Zero_Lo(1) <= '1';
799 
         end if;
800 
         if Regs_WrDin_i(7 downto 0) = C_ALL_ZEROS(7 downto 0) then
801 
            WrDin_r1_not_Zero_Lo(0) <= '0';
802 
         else
803 
            WrDin_r1_not_Zero_Lo(0) <= '1';
804 
         end if;
805 
 
806 
         if WrDin_r1_not_Zero_Lo = C_ALL_ZEROS(3 downto 0) then
807 
            WrDin_r2_not_Zero_Lo <= '0';
808 
         else
809 
            WrDin_r2_not_Zero_Lo <= '1';
810 
         end if;
811 
      end if;
812 
   end process;
813 
 
814 
 
815 
-- -----------------------------------------------------------
816 
-- Synchronous Delay : DMA Commands Write Valid and not End
817 
--
818 
   Synch_Delay_dmaCmd_Wr_Valid_and_End:
819 
   process ( trn_clk )
820 
   begin
821 
      if trn_clk'event and trn_clk = '1' then
822 
         Regs_Wr_dma_V_hi_r2      <= Regs_WrEn_r1
823 
                               and Regs_WrDin_r1(CINT_BIT_DMA_CTRL_VALID+32)
824 
                               ;
825 
         Regs_Wr_dma_nV_hi_r2     <= Regs_WrEn_r1
826 
                               and not Regs_WrDin_r1(CINT_BIT_DMA_CTRL_VALID+32)
827 
                               ;
828 
         Regs_Wr_dma_V_nE_hi_r2   <= Regs_WrEn_r1
829 
                               and Regs_WrDin_r1(CINT_BIT_DMA_CTRL_VALID+32)
830 
                               and not Regs_WrDin_r1(CINT_BIT_DMA_CTRL_END+32)
831 
                               ;
832 
 
833 
 
834 
         Regs_Wr_dma_V_lo_r2      <= Regs_WrEn_r1
835 
                               and Regs_WrDin_r1(CINT_BIT_DMA_CTRL_VALID)
836 
                               ;
837 
         Regs_Wr_dma_nV_lo_r2     <= Regs_WrEn_r1
838 
                               and not Regs_WrDin_r1(CINT_BIT_DMA_CTRL_VALID)
839 
                               ;
840 
         Regs_Wr_dma_V_nE_lo_r2   <= Regs_WrEn_r1
841 
                               and Regs_WrDin_r1(CINT_BIT_DMA_CTRL_VALID)
842 
                               and not Regs_WrDin_r1(CINT_BIT_DMA_CTRL_END)
843 
                               ;
844 
      end if;
845 
   end process;
846 
 
847 
 
848 
 
849 
-- ------------------------------------------------
850 
-- Synchronous Delay : Regs_WrDin_Hi19b_True_r2 x2
851 
--                     Regs_WrDin_Lo7b_True_r2 x2
852 
--
853 
   Synch_Delay_Regs_WrDin_Hi19b_and_Lo7b_True:
854 
   process ( trn_clk )
855 
   begin
856 
      if trn_clk'event and trn_clk = '1' then
857 
 
858 
         if Regs_WrDin_r1(C_DBUS_WIDTH-1 downto C_MAXSIZE_FLD_BIT_TOP+1+32)
859 
            = C_ALL_ZEROS(C_DBUS_WIDTH-1 downto C_MAXSIZE_FLD_BIT_TOP+1+32)
860 
            then
861 
            Regs_WrDin_Hi19b_True_hq_r2  <= '0';
862 
         else
863 
            Regs_WrDin_Hi19b_True_hq_r2  <= '1';
864 
         end if;
865 
 
866 
         if Regs_WrDin_r1(C_MAXSIZE_FLD_BIT_BOT-1+32 downto 2+32)
867 
            = C_ALL_ZEROS(C_MAXSIZE_FLD_BIT_BOT-1+32 downto 2+32)
868 
            then                               -- ! Lowest 2 bits ignored !
869 
            Regs_WrDin_Lo7b_True_hq_r2  <= '0';
870 
         else
871 
            Regs_WrDin_Lo7b_True_hq_r2  <= '1';
872 
         end if;
873 
 
874 
         if Regs_WrDin_r1(C_DBUS_WIDTH-1-32 downto C_MAXSIZE_FLD_BIT_TOP+1)
875 
            = C_ALL_ZEROS(C_DBUS_WIDTH-1-32 downto C_MAXSIZE_FLD_BIT_TOP+1)
876 
            then
877 
            Regs_WrDin_Hi19b_True_lq_r2  <= '0';
878 
         else
879 
            Regs_WrDin_Hi19b_True_lq_r2  <= '1';
880 
         end if;
881 
 
882 
         if Regs_WrDin_r1(C_MAXSIZE_FLD_BIT_BOT-1 downto 2)
883 
            = C_ALL_ZEROS(C_MAXSIZE_FLD_BIT_BOT-1 downto 2)
884 
            then                               -- ! Lowest 2 bits ignored !
885 
            Regs_WrDin_Lo7b_True_lq_r2  <= '0';
886 
         else
887 
            Regs_WrDin_Lo7b_True_lq_r2  <= '1';
888 
         end if;
889 
 
890 
      end if;
891 
   end process;
892 
 
893 
 
894 
 
895 
-- ---------------------------------------
896 
--
897 
   Write_DMA_Registers_Mux:
898 
   process ( trn_clk, trn_lnk_up_n)
899 
   begin
900 
      if trn_lnk_up_n = '1' then
901 
         Reg_WrMuxer_Hi <= (Others => '0');
902 
         Reg_WrMuxer_Lo <= (Others => '0');
903 
 
904 
      elsif trn_clk'event and trn_clk = '1' then
905 
 
906 
         if -- Regs_WrAddr_r1(C_DECODE_BIT_TOP downto C_DECODE_BIT_BOT)=C_REGS_BASE_ADDR(C_DECODE_BIT_TOP downto C_DECODE_BIT_BOT)
907 
            -- and
908 
            Regs_WrAddr_r1(C_DECODE_BIT_BOT-1 downto 2)=CONV_STD_LOGIC_VECTOR(0, C_DECODE_BIT_BOT-2)
909 
            -- and Regs_WrAddr_r1(2-1 downto 0)="00"
910 
            then
911 
            Reg_WrMuxer_Hi(0)   <= not Regs_WrMask_r1(1);
912 
         else
913 
            Reg_WrMuxer_Hi(0)   <= '0';
914 
         end if;
915 
 
916 
         FOR k IN 1 TO C_NUM_OF_ADDRESSES-1 LOOP
917 
 
918 
            if -- Regs_WrAddr_r1(C_DECODE_BIT_TOP downto C_DECODE_BIT_BOT)=C_REGS_BASE_ADDR(C_DECODE_BIT_TOP downto C_DECODE_BIT_BOT)
919 
               -- and
920 
               Regs_WrAddr_r1(C_DECODE_BIT_BOT-1 downto 2)=CONV_STD_LOGIC_VECTOR(k, C_DECODE_BIT_BOT-2)
921 
               -- and Regs_WrAddr_r1(2-1 downto 0)="00"
922 
               then
923 
               Reg_WrMuxer_Hi(k)   <= not Regs_WrMask_r1(1);
924 
            else
925 
               Reg_WrMuxer_Hi(k)   <= '0';
926 
            end if;
927 
 
928 
            if -- Regs_WrAddr_r1(C_DECODE_BIT_TOP downto C_DECODE_BIT_BOT)=C_REGS_BASE_ADDR(C_DECODE_BIT_TOP downto C_DECODE_BIT_BOT)
929 
               -- and
930 
               Regs_WrAddr_r1(C_DECODE_BIT_BOT-1 downto 2)=CONV_STD_LOGIC_VECTOR(k-1, C_DECODE_BIT_BOT-2)
931 
               -- and Regs_WrAddr_r1(2-1 downto 0)="00"
932 
               then
933 
               Reg_WrMuxer_Lo(k)   <= not Regs_WrMask_r1(0);
934 
            else
935 
               Reg_WrMuxer_Lo(k)   <= '0';
936 
            end if;
937 
 
938 
         END LOOP;
939 
 
940 
      end if;
941 
   end process;
942 
 
943 
 
944 
 
945 
--  -----------------------------------------------
946 
--  System Interrupt Status Control
947 
--  -----------------------------------------------
948 
 
949 
-- -------------------------------------------------------
950 
-- Synchronous Registered: Sys_Int_Enable_i
951 
   SysReg_Sys_Int_Enable:
952 
   process ( trn_clk, trn_lnk_up_n)
953 
   begin
954 
      if trn_lnk_up_n = '1' then
955 
         Sys_Int_Enable_i     <= (OTHERS => '0');
956 
      elsif trn_clk'event and trn_clk = '1' then
957 
 
958 
        if Regs_WrEn_r2='1'
959 
                    and Reg_WrMuxer_Hi(CINT_ADDR_IRQ_EN)='1'
960 
                         then
961 
            Sys_Int_Enable_i(32-1 downto 0) <=  Regs_WrDin_r2(64-1 downto 32);
962 
        elsif Regs_WrEn_r2='1'
963 
                    and Reg_WrMuxer_Lo(CINT_ADDR_IRQ_EN)='1'
964 
                         then
965 
            Sys_Int_Enable_i(32-1 downto 0) <=  Regs_WrDin_r2(32-1 downto 0);
966 
        else
967 
            Sys_Int_Enable_i <=  Sys_Int_Enable_i;
968 
        end if;
969 
 
970 
      end if;
971 
   end process;
972 
 
973 
 
974 
--  -----------------------------------------------
975 
--    System General Control Register
976 
--  -----------------------------------------------
977 
-- -----------------------------------------------
978 
-- Synchronous Registered: General_Control
979 
   SysReg_General_Control:
980 
   process ( trn_clk, trn_lnk_up_n)
981 
   begin
982 
      if trn_lnk_up_n = '1' then
983 
         General_Control_i     <= (OTHERS => '0');
984 
         General_Control_i(C_GCR_MSG_ROUT_BIT_TOP downto C_GCR_MSG_ROUT_BIT_BOT)
985 
                               <= C_TYPE_OF_MSG(C_TLP_TYPE_BIT_BOT+C_GCR_MSG_ROUT_BIT_TOP-C_GCR_MSG_ROUT_BIT_BOT
986 
                                  downto C_TLP_TYPE_BIT_BOT);
987 
 
988 
      elsif trn_clk'event and trn_clk = '1' then
989 
 
990 
        if Regs_WrEn_r2='1'
991 
           and Reg_WrMuxer_Hi(CINT_ADDR_CONTROL)='1'
992 
           then
993 
            General_Control_i(32-1 downto 0)  <=  Regs_WrDin_r2(64-1 downto 32);
994 
        elsif Regs_WrEn_r2='1'
995 
           and Reg_WrMuxer_Lo(CINT_ADDR_CONTROL)='1'
996 
           then
997 
            General_Control_i(32-1 downto 0)  <=  Regs_WrDin_r2(32-1 downto 0);
998 
        else
999 
            General_Control_i  <=  General_Control_i;
1000 
        end if;
1001 
 
1002 
      end if;
1003 
   end process;
1004 
 
1005 3 weng_ziti 
---- -----------------------------------------------
1006 
---- Synchronous Registered: DG_Reset_i
1007 
--   SysReg_DGen_Reset:
1008 
--   process ( trn_clk, trn_lnk_up_n)
1009 
--   begin
1010 
--      if trn_lnk_up_n = '1' then
1011 
--         DG_Reset_i            <= '1';
1012 
--         DG_Rst_Counter        <= (OTHERS=>'0');
1013 
--
1014 
--      elsif trn_clk'event and trn_clk = '1' then
1015 
--
1016 
--        if DG_Rst_Counter=X"FF" then
1017 
--           DG_Rst_Counter  <= DG_Rst_Counter;
1018 
--        else
1019 
--           DG_Rst_Counter  <= DG_Rst_Counter + '1';
1020 
--        end if;
1021 
--
1022 
--        if DG_Rst_Counter(7)='0' then
1023 
--            DG_Reset_i         <=  '1';
1024 
--        elsif Regs_WrEn_r2='1'
1025 
--                  and Reg_WrMuxer_Hi(CINT_ADDR_DG_CTRL)='1'
1026 
--                       then
1027 
--            DG_Reset_i         <=  Command_is_Reset_Hi;
1028 
--        elsif Regs_WrEn_r2='1'
1029 
--                  and Reg_WrMuxer_Lo(CINT_ADDR_DG_CTRL)='1'
1030 
--                       then
1031 
--            DG_Reset_i         <=  Command_is_Reset_Lo;
1032 
--        else
1033 
--            DG_Reset_i         <=  '0';
1034 
--        end if;
1035 
--
1036 
--      end if;
1037 
--   end process;
1038 
--
1039 
---- -----------------------------------------------
1040 
---- Synchronous Registered: DG_Mask_i
1041 
--   SysReg_DGen_Mask:
1042 
--   process ( trn_clk, trn_lnk_up_n)
1043 
--   begin
1044 
--      if trn_lnk_up_n = '1' then
1045 
--         DG_Mask_i     <= '0';
1046 
--      elsif trn_clk'event and trn_clk = '1' then
1047 
--
1048 
--        if Regs_WrEn_r2='1'
1049 
--           and Reg_WrMuxer_Hi(CINT_ADDR_DG_CTRL)='1'
1050 
--           then
1051 
--           DG_Mask_i  <=  Regs_WrDin_r2(32+CINT_BIT_DG_MASK);
1052 
--        elsif Regs_WrEn_r2='1'
1053 
--           and Reg_WrMuxer_Lo(CINT_ADDR_DG_CTRL)='1'
1054 
--           then
1055 
--           DG_Mask_i  <=  Regs_WrDin_r2(CINT_BIT_DG_MASK);
1056 
--        else
1057 
--           DG_Mask_i  <=  DG_Mask_i;
1058 
--        end if;
1059 
--
1060 
--      end if;
1061 
--   end process;
1062 
--
1063 
----------------------------------------------------------------------------
1064 
----  Data generator status
1065 
----
1066 
--   Synch_DG_Status_i:
1067 
--   process ( trn_clk, DG_Reset_i )
1068 
--   begin
1069 
--     if DG_Reset_i = '1' then
1070 
--        DG_Status_i    <= (OTHERS=>'0');
1071 
--     elsif trn_clk'event and trn_clk = '1' then
1072 
--        DG_Status_i(CINT_BIT_DG_MASK)    <= DG_Mask_i;
1073 
--        DG_Status_i(CINT_BIT_DG_BUSY)    <= DG_is_Running;
1074 
--     end if;
1075 
--   end process;
1076 2 weng_ziti 
 
1077 
-- -----------------------------------------------
1078 
-- Synchronous Registered: IG_Control_i
1079 
   SysReg_IntGen_Control:
1080 
   process ( trn_clk, trn_lnk_up_n)
1081 
   begin
1082 
      if trn_lnk_up_n = '1' then
1083 
         IG_Control_i          <= (OTHERS => '0');
1084 
         IG_Reset_i            <= '1';
1085 
         IG_Host_Clear_i       <= '0';
1086 
 
1087 
      elsif trn_clk'event and trn_clk = '1' then
1088 
 
1089 
        if Regs_WrEn_r2='1'
1090 
                    and Reg_WrMuxer_Hi(CINT_ADDR_IG_CONTROL)='1'
1091 
                         then
1092 
            IG_Control_i(32-1 downto 0)       <=  Regs_WrDin_r2(64-1 downto 32);
1093 
            IG_Reset_i         <=  Command_is_Reset_Hi;
1094 
            IG_Host_Clear_i    <=  Command_is_Host_iClr_Hi;
1095 
        elsif Regs_WrEn_r2='1'
1096 
                    and Reg_WrMuxer_Lo(CINT_ADDR_IG_CONTROL)='1'
1097 
                         then
1098 
            IG_Control_i(32-1 downto 0)       <=  Regs_WrDin_r2(32-1 downto 0);
1099 
            IG_Reset_i         <=  Command_is_Reset_Lo;
1100 
            IG_Host_Clear_i    <=  Command_is_Host_iClr_Lo;
1101 
        else
1102 
            IG_Control_i       <=  IG_Control_i;
1103 
            IG_Reset_i         <=  '0';
1104 
            IG_Host_Clear_i    <=  '0';
1105 
        end if;
1106 
 
1107 
      end if;
1108 
   end process;
1109 
 
1110 
 
1111 
-- -----------------------------------------------
1112 
-- Synchronous Registered: IG_Latency_i
1113 
   SysReg_IntGen_Latency:
1114 
   process ( trn_clk, trn_lnk_up_n)
1115 
   begin
1116 
      if trn_lnk_up_n = '1' then
1117 
         IG_Latency_i       <= (OTHERS => '0');
1118 
 
1119 
      elsif trn_clk'event and trn_clk = '1' then
1120 
 
1121 
        if IG_Reset_i='1' then
1122 
            IG_Latency_i    <=  (OTHERS => '0');
1123 
        elsif Regs_WrEn_r2='1'
1124 
                    and Reg_WrMuxer_Hi(CINT_ADDR_IG_LATENCY)='1'
1125 
                         then
1126 
            IG_Latency_i(32-1 downto 0)    <=  Regs_WrDin_r2(64-1 downto 32);
1127 
        elsif Regs_WrEn_r2='1'
1128 
                    and Reg_WrMuxer_Lo(CINT_ADDR_IG_LATENCY)='1'
1129 
                         then
1130 
            IG_Latency_i(32-1 downto 0)    <=  Regs_WrDin_r2(32-1 downto 0);
1131 
        else
1132 
            IG_Latency_i    <=  IG_Latency_i;
1133 
        end if;
1134 
 
1135 
      end if;
1136 
   end process;
1137 
 
1138 
 
1139 
 
1140 
 
1141 3 weng_ziti 
----  ------------------------------------------------------
1142 
----      Protocol CTL interface
1143 
----  ------------------------------------------------------
1144 
--
1145 
---- -------------------------------------------------------
1146 
---- Synchronous Registered: ctl_rd
1147 
--   Syn_CTL_rd:
1148 
--   process ( trn_clk, trn_lnk_up_n)
1149 
--   begin
1150 
--      if trn_lnk_up_n = '1' then
1151 
--         ctl_rd_i     <= (OTHERS => '0');
1152 
--         ctl_rv_i     <= '0';
1153 
--      elsif trn_clk'event and trn_clk = '1' then
1154 
--
1155 
--         if Regs_WrEn_r2='1' and Reg_WrMuxer_Hi(CINT_ADDR_CTL_CLASS)='1' then
1156 
--            ctl_rd_i     <= Regs_WrDin_r2(C_DBUS_WIDTH-1 downto 32);
1157 
--            ctl_rv_i     <= '1';
1158 
--         elsif Regs_WrEn_r2='1' and Reg_WrMuxer_Lo(CINT_ADDR_CTL_CLASS)='1' then
1159 
--            ctl_rd_i     <= Regs_WrDin_r2(32-1 downto 0);
1160 
--            ctl_rv_i     <= '1';
1161 
--         else
1162 
--            ctl_rd_i     <= ctl_rd_i;
1163 
--            ctl_rv_i     <= '0';
1164 
--         end if;
1165 
--
1166 
--      end if;
1167 
--   end process;
1168 
--
1169 
--
1170 
---- -----------------------------------------------
1171 
---- Synchronous Registered: ctl_reset
1172 
--   SysReg_ctl_reset:
1173 
--   process ( trn_clk, trn_lnk_up_n)
1174 
--   begin
1175 
--      if trn_lnk_up_n = '1' then
1176 
--         ctl_reset_i            <= '1';
1177 
--
1178 
--      elsif trn_clk'event and trn_clk = '1' then
1179 
--
1180 
--        if Regs_WrEn_r2='1'
1181 
--                  and Reg_WrMuxer_Hi(CINT_ADDR_TC_STATUS)='1'
1182 
--                       then
1183 
--            ctl_reset_i         <=  Command_is_Reset_Hi;
1184 
--        elsif Regs_WrEn_r2='1'
1185 
--                  and Reg_WrMuxer_Lo(CINT_ADDR_TC_STATUS)='1'
1186 
--                       then
1187 
--            ctl_reset_i         <=  Command_is_Reset_Lo;
1188 
--        else
1189 
--            ctl_reset_i         <=  '0';
1190 
--        end if;
1191 
--
1192 
--      end if;
1193 
--   end process;
1194 
--
1195 
--
1196 
--
1197 
---- -------------------------------------------------------
1198 
---- Synchronous Registered: ctl_td
1199 
----    ++++++++++++ INT triggering  ++++++++++++++++++
1200 
--   Syn_CTL_td:
1201 
--   process ( trn_clk, trn_lnk_up_n)
1202 
--   begin
1203 
--      if trn_lnk_up_n = '1' then
1204 
--         ctl_td_r     <= (OTHERS => '0');
1205 
--      elsif trn_clk'event and trn_clk = '1' then
1206 
--
1207 
--         if ctl_tv='1' then
1208 
--            ctl_td_r     <= ctl_td;
1209 
--         else
1210 
--            ctl_td_r     <= ctl_td_r;
1211 
--         end if;
1212 
--
1213 
--      end if;
1214 
--   end process;
1215 
--
1216 
--
1217 
--
1218 
----  ------------------------------------------------------
1219 
----      Protocol DLM interface
1220 
----  ------------------------------------------------------
1221 
--
1222 
---- -------------------------------------------------------
1223 
---- Synchronous Registered: dlm_td
1224 
--   Syn_DLM_td:
1225 
--   process ( trn_clk, trn_lnk_up_n)
1226 
--   begin
1227 
--      if trn_lnk_up_n = '1' then
1228 
--         dlm_td_i     <= (OTHERS => '0');
1229 
--         dlm_tv_i     <= '0';
1230 
--      elsif trn_clk'event and trn_clk = '1' then
1231 
--
1232 
--         if Regs_WrEn_r2='1' and Reg_WrMuxer_Hi(CINT_ADDR_DLM_CLASS)='1' then
1233 
--            dlm_td_i     <= Regs_WrDin_r2(C_DBUS_WIDTH-1 downto 32);
1234 
--            dlm_tv_i     <= '1';
1235 
--         elsif Regs_WrEn_r2='1' and Reg_WrMuxer_Lo(CINT_ADDR_DLM_CLASS)='1' then
1236 
--            dlm_td_i     <= Regs_WrDin_r2(32-1 downto 0);
1237 
--            dlm_tv_i     <= '1';
1238 
--         else
1239 
--            dlm_td_i     <= dlm_td_i;
1240 
--            dlm_tv_i     <= '0';
1241 
--         end if;
1242 
--
1243 
--      end if;
1244 
--   end process;
1245 
--
1246 
--
1247 
---- -------------------------------------------------------
1248 
---- Synchronous Registered: dlm_rd
1249 
----    ++++++++++++ INT triggering  ++++++++++++++++++
1250 
--   Syn_DLM_rd:
1251 
--   process ( trn_clk, trn_lnk_up_n)
1252 
--   begin
1253 
--      if trn_lnk_up_n = '1' then
1254 
--         dlm_rd_r     <= (OTHERS => '0');
1255 
--      elsif trn_clk'event and trn_clk = '1' then
1256 
--
1257 
--         if dlm_rv='1' then
1258 
--            dlm_rd_r     <= dlm_rd;
1259 
--         else
1260 
--            dlm_rd_r     <= dlm_rd_r;
1261 
--         end if;
1262 
--
1263 
--      end if;
1264 
--   end process;
1265 2 weng_ziti 
 
1266 
 
1267 
--  ------------------------------------------------------
1268 
--  DMA Upstream Registers
1269 
--  ------------------------------------------------------
1270 
 
1271 
-- -------------------------------------------------------
1272 
-- Synchronous Registered: DMA_us_PA_i
1273 
   RxTrn_DMA_us_PA:
1274 
   process ( trn_clk, trn_lnk_up_n)
1275 
   begin
1276 
      if trn_lnk_up_n = '1' then
1277 
         DMA_us_PA_i  <= (OTHERS => '0');
1278 
      elsif trn_clk'event and trn_clk = '1' then
1279 
 
1280 
        if usDMA_Channel_Rst_i = '1' then
1281 
            DMA_us_PA_i <= (OTHERS => '0');
1282 
        else
1283 
 
1284 
          if Regs_WrEn_r2='1' and Reg_WrMuxer_Hi(CINT_ADDR_DMA_US_PAH)='1' then
1285 
            DMA_us_PA_i(C_DBUS_WIDTH-1 downto 32)  <= Regs_WrDin_r2(64-1 downto 32);
1286 
          elsif Regs_WrEn_r2='1' and Reg_WrMuxer_Lo(CINT_ADDR_DMA_US_PAH)='1' then
1287 
            DMA_us_PA_i(C_DBUS_WIDTH-1 downto 32)  <= Regs_WrDin_r2(32-1 downto 0);
1288 
          else
1289 
            DMA_us_PA_i(C_DBUS_WIDTH-1 downto 32)  <= DMA_us_PA_i(C_DBUS_WIDTH-1 downto 32);
1290 
          end if;
1291 
 
1292 
          if Regs_WrEn_r2='1' and Reg_WrMuxer_Hi(CINT_ADDR_DMA_US_PAL)='1' then
1293 
            DMA_us_PA_i(32-1 downto 0)  <= Regs_WrDin_r2(64-1 downto 32);
1294 
          elsif Regs_WrEn_r2='1' and Reg_WrMuxer_Lo(CINT_ADDR_DMA_US_PAL)='1' then
1295 
            DMA_us_PA_i(32-1 downto 0)  <= Regs_WrDin_r2(32-1 downto 0);
1296 
          else
1297 
            DMA_us_PA_i(32-1 downto 0)  <= DMA_us_PA_i(32-1 downto 0);
1298 
          end if;
1299 
 
1300 
        end if;
1301 
 
1302 
      end if;
1303 
   end process;
1304 
 
1305 
 
1306 
-- -------------------------------------------------------
1307 
-- Synchronous Registered: DMA_us_HA_i
1308 
   RxTrn_DMA_us_HA:
1309 
   process ( trn_clk, trn_lnk_up_n)
1310 
   begin
1311 
      if trn_lnk_up_n = '1' then
1312 
         DMA_us_HA_i     <= (OTHERS => '1');
1313 
         usHA_is_64b_i   <= '0';
1314 
 
1315 
      elsif trn_clk'event and trn_clk = '1' then
1316 
 
1317 
        if usDMA_Channel_Rst_i = '1' then
1318 
            DMA_us_HA_i <= (OTHERS => '1');
1319 
            usHA_is_64b_i <= '0';
1320 
        else
1321 
 
1322 
          if Regs_WrEn_r2='1' and Reg_WrMuxer_Hi(CINT_ADDR_DMA_US_HAH)='1' then
1323 
            DMA_us_HA_i(C_DBUS_WIDTH-1 downto 32)  <= Regs_WrDin_r2(64-1 downto 32);
1324 
            usHA_is_64b_i   <=  WrDin_r2_not_Zero_Hi;
1325 
          elsif Regs_WrEn_r2='1' and Reg_WrMuxer_Lo(CINT_ADDR_DMA_US_HAH)='1' then
1326 
            DMA_us_HA_i(C_DBUS_WIDTH-1 downto 32)  <= Regs_WrDin_r2(32-1 downto 0);
1327 
            usHA_is_64b_i   <=  WrDin_r2_not_Zero_Lo;
1328 
          else
1329 
            DMA_us_HA_i(C_DBUS_WIDTH-1 downto 32)  <= DMA_us_HA_i(C_DBUS_WIDTH-1 downto 32);
1330 
            usHA_is_64b_i   <=  usHA_is_64b_i;
1331 
          end if;
1332 
 
1333 
          if Regs_WrEn_r2='1' and Reg_WrMuxer_Hi(CINT_ADDR_DMA_US_HAL)='1' then
1334 
            DMA_us_HA_i(32-1 downto 0)  <= Regs_WrDin_r2(64-1 downto 32);
1335 
          elsif Regs_WrEn_r2='1' and Reg_WrMuxer_Lo(CINT_ADDR_DMA_US_HAL)='1' then
1336 
            DMA_us_HA_i(32-1 downto 0)  <= Regs_WrDin_r2(32-1 downto 0);
1337 
          else
1338 
            DMA_us_HA_i(32-1 downto 0)  <= DMA_us_HA_i(32-1 downto 0);
1339 
          end if;
1340 
 
1341 
        end if;
1342 
 
1343 
      end if;
1344 
   end process;
1345 
 
1346 
 
1347 
-- -------------------------------------------------------
1348 
-- Synchronous output: DMA_us_BDA_i
1349 
   Syn_Output_DMA_us_BDA:
1350 
   process ( trn_clk, trn_lnk_up_n)
1351 
   begin
1352 
      if trn_lnk_up_n = '1' then
1353 
         DMA_us_BDA_i    <= (OTHERS =>'0');
1354 
         usBDA_is_64b_i  <= '0';
1355 
      elsif trn_clk'event and trn_clk = '1' then
1356 
 
1357 
        if usDMA_Channel_Rst_i = '1' then
1358 
           DMA_us_BDA_i <= (OTHERS => '0');
1359 
           usBDA_is_64b_i <= '0';
1360 
        else
1361 
 
1362 
          if Regs_WrEn_r2='1' and Reg_WrMuxer_Hi(CINT_ADDR_DMA_US_BDAH)='1' then
1363 
            DMA_us_BDA_i(C_DBUS_WIDTH-1 downto 32)  <= Regs_WrDin_r2(C_DBUS_WIDTH-1 downto 32);
1364 
            usBDA_is_64b_i   <=  WrDin_r2_not_Zero_Hi;
1365 
          elsif Regs_WrEn_r2='1' and Reg_WrMuxer_Lo(CINT_ADDR_DMA_US_BDAH)='1' then
1366 
            DMA_us_BDA_i(C_DBUS_WIDTH-1 downto 32)  <= Regs_WrDin_r2(32-1 downto 0);
1367 
            usBDA_is_64b_i   <=  WrDin_r2_not_Zero_Lo;
1368 
          else
1369 
            DMA_us_BDA_i(C_DBUS_WIDTH-1 downto 32)  <= DMA_us_BDA_i(C_DBUS_WIDTH-1 downto 32);
1370 
            usBDA_is_64b_i   <=  usBDA_is_64b_i;
1371 
          end if;
1372 
 
1373 
          if Regs_WrEn_r2='1' and Reg_WrMuxer_Hi(CINT_ADDR_DMA_US_BDAL)='1' then
1374 
            DMA_us_BDA_i(32-1 downto 0)  <= Regs_WrDin_r2(C_DBUS_WIDTH-1 downto 32);
1375 
          elsif Regs_WrEn_r2='1' and Reg_WrMuxer_Lo(CINT_ADDR_DMA_US_BDAL)='1' then
1376 
            DMA_us_BDA_i(32-1 downto 0)  <= Regs_WrDin_r2(32-1 downto 0);
1377 
          else
1378 
            DMA_us_BDA_i(32-1 downto 0)  <= DMA_us_BDA_i(32-1 downto 0);
1379 
          end if;
1380 
 
1381 
        end if;
1382 
 
1383 
      end if;
1384 
   end process;
1385 
 
1386 
 
1387 
 
1388 
-- -------------------------------------------------------
1389 
-- Synchronous Registered: DMA_us_Length_i
1390 
   RxTrn_DMA_us_Length:
1391 
   process ( trn_clk, trn_lnk_up_n)
1392 
   begin
1393 
      if trn_lnk_up_n = '1' then
1394 
         DMA_us_Length_i     <= (OTHERS => '0');
1395 
         usLeng_Hi19b_True_i <= '0';
1396 
         usLeng_Lo7b_True_i  <= '0';
1397 
      elsif trn_clk'event and trn_clk = '1' then
1398 
 
1399 
         if usDMA_Channel_Rst_i = '1' then
1400 
            DMA_us_Length_i     <= (OTHERS => '0');
1401 
            usLeng_Hi19b_True_i <= '0';
1402 
            usLeng_Lo7b_True_i  <= '0';
1403 
 
1404 
         elsif Regs_WrEn_r2='1' and  Reg_WrMuxer_Hi(CINT_ADDR_DMA_US_LENG)='1' then
1405 
            DMA_us_Length_i(32-1 downto 0)     <= Regs_WrDin_r2(64-1 downto 32);
1406 
            usLeng_Hi19b_True_i <= Regs_WrDin_Hi19b_True_hq_r2;
1407 
            usLeng_Lo7b_True_i  <= Regs_WrDin_Lo7b_True_hq_r2;
1408 
         elsif Regs_WrEn_r2='1' and  Reg_WrMuxer_Lo(CINT_ADDR_DMA_US_LENG)='1' then
1409 
            DMA_us_Length_i(32-1 downto 0)     <= Regs_WrDin_r2(32-1 downto 0);
1410 
            usLeng_Hi19b_True_i <= Regs_WrDin_Hi19b_True_lq_r2;
1411 
            usLeng_Lo7b_True_i  <= Regs_WrDin_Lo7b_True_lq_r2;
1412 
         else
1413 
            DMA_us_Length_i     <= DMA_us_Length_i;
1414 
            usLeng_Hi19b_True_i <= usLeng_Hi19b_True_i;
1415 
            usLeng_Lo7b_True_i  <= usLeng_Lo7b_True_i;
1416 
 
1417 
         end if;
1418 
 
1419 
      end if;
1420 
   end process;
1421 
 
1422 
 
1423 
 
1424 
-- -------------------------------------------------------
1425 
-- Synchronous us_Param_Modified
1426 
   SynReg_us_Param_Modified:
1427 
   process ( trn_clk, trn_lnk_up_n)
1428 
   begin
1429 
      if trn_lnk_up_n = '1' then
1430 
         us_Param_Modified     <= '0';
1431 
 
1432 
      elsif trn_clk'event and trn_clk = '1' then
1433 
 
1434 
        if usDMA_Channel_Rst_i = '1'
1435 
           or usDMA_Start_i = '1'
1436 
           or usDMA_Start2_i = '1'
1437 
           then
1438 
             us_Param_Modified     <= '0';
1439 
        elsif Regs_WrEn_r2='1' and
1440 
                (
1441 
                    Reg_WrMuxer_Hi(CINT_ADDR_DMA_US_PAL) ='1'
1442 
                 or Reg_WrMuxer_Lo(CINT_ADDR_DMA_US_PAL) ='1'
1443 
                 or Reg_WrMuxer_Hi(CINT_ADDR_DMA_US_HAH) ='1'
1444 
                 or Reg_WrMuxer_Lo(CINT_ADDR_DMA_US_HAH) ='1'
1445 
                 or Reg_WrMuxer_Hi(CINT_ADDR_DMA_US_HAL) ='1'
1446 
                 or Reg_WrMuxer_Lo(CINT_ADDR_DMA_US_HAL) ='1'
1447 
                 or Reg_WrMuxer_Hi(CINT_ADDR_DMA_US_BDAH)='1'
1448 
                 or Reg_WrMuxer_Lo(CINT_ADDR_DMA_US_BDAH)='1'
1449 
                 or Reg_WrMuxer_Hi(CINT_ADDR_DMA_US_BDAL)='1'
1450 
                 or Reg_WrMuxer_Lo(CINT_ADDR_DMA_US_BDAL)='1'
1451 
                 or Reg_WrMuxer_Hi(CINT_ADDR_DMA_US_LENG)='1'
1452 
                 or Reg_WrMuxer_Lo(CINT_ADDR_DMA_US_LENG)='1'
1453 
                )
1454 
           then
1455 
             us_Param_Modified     <= '1';
1456 
        else
1457 
             us_Param_Modified     <= us_Param_Modified;
1458 
 
1459 
        end if;
1460 
 
1461 
      end if;
1462 
   end process;
1463 
 
1464 
 
1465 
 
1466 
-- -------------------------------------------------------
1467 
-- Synchronous output: DMA_us_Control_i
1468 
   Syn_Output_DMA_us_Control:
1469 
   process ( trn_clk, trn_lnk_up_n)
1470 
   begin
1471 
      if trn_lnk_up_n = '1' then
1472 
         DMA_us_Control_i <= (OTHERS =>'0');
1473 
      elsif trn_clk'event and trn_clk = '1' then
1474 
 
1475 
         if     Regs_Wr_dma_V_nE_Hi_r2='1'
1476 
            and Reg_WrMuxer_Hi(CINT_ADDR_DMA_US_CTRL)='1'
1477 
--            and Regs_WrDin_r2(CINT_BIT_DMA_CTRL_VALID)='1'
1478 
--            and Regs_WrDin_r2(CINT_BIT_DMA_CTRL_END)='0'
1479 
            and us_Param_Modified='1'
1480 
            and usDMA_Stop_i='0'
1481 
            then
1482 
               DMA_us_Control_i(32-1 downto 0) <= Regs_WrDin_r2(C_DBUS_WIDTH-1 downto 8+32)& X"00";
1483 
         elsif Regs_Wr_dma_V_nE_Lo_r2='1'
1484 
            and Reg_WrMuxer_Lo(CINT_ADDR_DMA_US_CTRL)='1'
1485 
--            and Regs_WrDin_r2(CINT_BIT_DMA_CTRL_VALID)='1'
1486 
--            and Regs_WrDin_r2(CINT_BIT_DMA_CTRL_END)='0'
1487 
            and us_Param_Modified='1'
1488 
            and usDMA_Stop_i='0'
1489 
            then
1490 
               DMA_us_Control_i(32-1 downto 0) <= Regs_WrDin_r2(32-1 downto 8)& X"00";
1491 
         elsif  Regs_Wr_dma_nV_Hi_r2='1'
1492 
            and Reg_WrMuxer_Hi(CINT_ADDR_DMA_US_CTRL)='1'
1493 
--            and Regs_WrDin_r2(CINT_BIT_DMA_CTRL_VALID)='0'
1494 
            then
1495 
               DMA_us_Control_i(32-1 downto 0) <= Last_Ctrl_Word_us(32-1 downto 0);
1496 
         elsif  Regs_Wr_dma_nV_Lo_r2='1'
1497 
            and Reg_WrMuxer_Lo(CINT_ADDR_DMA_US_CTRL)='1'
1498 
--            and Regs_WrDin_r2(CINT_BIT_DMA_CTRL_VALID)='0'
1499 
            then
1500 
               DMA_us_Control_i(32-1 downto 0) <= Last_Ctrl_Word_us(32-1 downto 0);
1501 
         else
1502 
            DMA_us_Control_i  <= DMA_us_Control_i;
1503 
         end if;
1504 
 
1505 
      end if;
1506 
   end process;
1507 
 
1508 
 
1509 
-- -------------------------------------------------------
1510 
-- Synchronous Register: Last_Ctrl_Word_us
1511 
   Hold_Last_Ctrl_Word_us:
1512 
   process ( trn_clk, trn_lnk_up_n)
1513 
   begin
1514 
      if trn_lnk_up_n = '1' then
1515 
         Last_Ctrl_Word_us  <= C_DEF_DMA_CTRL_WORD;
1516 
      elsif trn_clk'event and trn_clk = '1' then
1517 
 
1518 
        if usDMA_Channel_Rst_i = '1' then
1519 
            Last_Ctrl_Word_us <= C_DEF_DMA_CTRL_WORD;
1520 
        elsif Regs_Wr_dma_V_nE_Hi_r2='1'
1521 
          and Reg_WrMuxer_Hi(CINT_ADDR_DMA_US_CTRL)='1'
1522 
--          and Regs_WrDin_r2(CINT_BIT_DMA_CTRL_VALID)='1'
1523 
--          and Regs_WrDin_r2(CINT_BIT_DMA_CTRL_END)='0'
1524 
          and us_Param_Modified='1'
1525 
          and usDMA_Stop_i='0'
1526 
          then
1527 
            Last_Ctrl_Word_us(32-1 downto 0) <= Regs_WrDin_r2(C_DBUS_WIDTH-1 downto 8+32) & X"00";
1528 
        elsif Regs_Wr_dma_V_nE_Lo_r2='1'
1529 
          and Reg_WrMuxer_Lo(CINT_ADDR_DMA_US_CTRL)='1'
1530 
--          and Regs_WrDin_r2(CINT_BIT_DMA_CTRL_VALID)='1'
1531 
--          and Regs_WrDin_r2(CINT_BIT_DMA_CTRL_END)='0'
1532 
          and us_Param_Modified='1'
1533 
          and usDMA_Stop_i='0'
1534 
          then
1535 
            Last_Ctrl_Word_us(32-1 downto 0) <= Regs_WrDin_r2(32-1 downto 8) & X"00";
1536 
        elsif Regs_Wr_dma_V_nE_Hi_r2='1'
1537 
          and Reg_WrMuxer_Hi(CINT_ADDR_DMA_US_CTRL)='1'
1538 
--          and Regs_WrDin_r2(CINT_BIT_DMA_CTRL_VALID)='1'
1539 
--          and Regs_WrDin_r2(CINT_BIT_DMA_CTRL_END)='0'
1540 
          and us_Param_Modified='1'
1541 
          and usDMA_Stop_i='0'
1542 
          then
1543 
            Last_Ctrl_Word_us(32-1 downto 0) <= Regs_WrDin_r2(C_DBUS_WIDTH-1 downto 8+32) & X"00";
1544 
        elsif Regs_Wr_dma_V_nE_Lo_r2='1'
1545 
          and Reg_WrMuxer_Lo(CINT_ADDR_DMA_US_CTRL)='1'
1546 
--          and Regs_WrDin_r2(CINT_BIT_DMA_CTRL_VALID)='1'
1547 
--          and Regs_WrDin_r2(CINT_BIT_DMA_CTRL_END)='0'
1548 
          and us_Param_Modified='1'
1549 
          and usDMA_Stop_i='0'
1550 
          then
1551 
            Last_Ctrl_Word_us(32-1 downto 0) <= Regs_WrDin_r2(32-1 downto 8) & X"00";
1552 
        else
1553 
            Last_Ctrl_Word_us <= Last_Ctrl_Word_us;
1554 
        end if;
1555 
 
1556 
      end if;
1557 
   end process;
1558 
 
1559 
 
1560 
-- -------------------------------------------------------
1561 
-- Synchronous output: DMA_us_Start_Stop
1562 
   Syn_Output_DMA_us_Start_Stop:
1563 
   process ( trn_clk, trn_lnk_up_n)
1564 
   begin
1565 
      if trn_lnk_up_n = '1' then
1566 
         usDMA_Start_i  <= '0';
1567 
         usDMA_Stop_i   <= '0';
1568 
      elsif trn_clk'event and trn_clk = '1' then
1569 
 
1570 
         if     Regs_WrEnA_r2='1'
1571 
            and Reg_WrMuxer_Hi(CINT_ADDR_DMA_US_CTRL)='1'
1572 
            and Regs_WrDin_r2(CINT_BIT_DMA_CTRL_VALID+32)='1'
1573 
            then
1574 
               usDMA_Start_i <= not Regs_WrDin_r2(CINT_BIT_DMA_CTRL_END+32)
1575 
                            and not usDMA_Stop_i
1576 
                            and not Command_is_Reset_Hi
1577 
                            and us_Param_Modified
1578 
                            ;
1579 
               usDMA_Stop_i  <= Regs_WrDin_r2(CINT_BIT_DMA_CTRL_END+32)
1580 
                            and not Command_is_Reset_Hi
1581 
                            ;
1582 
         elsif Regs_WrEnA_r2='1'
1583 
            and Reg_WrMuxer_Lo(CINT_ADDR_DMA_US_CTRL)='1'
1584 
            and Regs_WrDin_r2(CINT_BIT_DMA_CTRL_VALID)='1'
1585 
            then
1586 
               usDMA_Start_i <= not Regs_WrDin_r2(CINT_BIT_DMA_CTRL_END)
1587 
                            and not usDMA_Stop_i
1588 
                            and not Command_is_Reset_Lo
1589 
                            and us_Param_Modified
1590 
                            ;
1591 
               usDMA_Stop_i  <= Regs_WrDin_r2(CINT_BIT_DMA_CTRL_END)
1592 
                            and not Command_is_Reset_Lo
1593 
                            ;
1594 
         elsif  Regs_WrEnA_r2='1'
1595 
            and Reg_WrMuxer_Hi(CINT_ADDR_DMA_US_CTRL)='1'
1596 
            and Regs_WrDin_r2(CINT_BIT_DMA_CTRL_VALID)='0'
1597 
            then
1598 
               usDMA_Start_i <= not Last_Ctrl_Word_us(CINT_BIT_DMA_CTRL_END)
1599 
                            and us_Param_Modified;
1600 
               usDMA_Stop_i  <= Last_Ctrl_Word_us(CINT_BIT_DMA_CTRL_END);
1601 
         elsif  Regs_WrEnA_r2='1'
1602 
            and Reg_WrMuxer_Lo(CINT_ADDR_DMA_US_CTRL)='1'
1603 
            and Regs_WrDin_r2(CINT_BIT_DMA_CTRL_VALID)='0'
1604 
            then
1605 
               usDMA_Start_i <= not Last_Ctrl_Word_us(CINT_BIT_DMA_CTRL_END)
1606 
                            and us_Param_Modified;
1607 
               usDMA_Stop_i  <= Last_Ctrl_Word_us(CINT_BIT_DMA_CTRL_END);
1608 
         elsif usDMA_Cmd_Ack='1'
1609 
            then
1610 
               usDMA_Start_i <= '0';
1611 
               usDMA_Stop_i  <= usDMA_Stop_i;
1612 
         else
1613 
               usDMA_Start_i <= usDMA_Start_i;
1614 
               usDMA_Stop_i  <= usDMA_Stop_i;
1615 
         end if;
1616 
 
1617 
      end if;
1618 
   end process;
1619 
 
1620 
 
1621 
-- -------------------------------------------------------
1622 
-- Synchronous output: DMA_us_Start2_Stop2
1623 
   Syn_Output_DMA_us_Start2_Stop2:
1624 
   process ( trn_clk, trn_lnk_up_n)
1625 
   begin
1626 
      if trn_lnk_up_n = '1' then
1627 
         usDMA_Start2_i <= '0';
1628 
         usDMA_Stop2_i  <= '0';
1629 
      elsif trn_clk'event and trn_clk = '1' then
1630 
 
1631 
         if usDMA_Channel_Rst_i='1' then
1632 
               usDMA_Start2_i <= '0';
1633 
               usDMA_Stop2_i  <= '0';
1634 
         elsif     Regs_WrEnB_r2='1'
1635 
            and Reg_WrMuxer_Hi(CINT_ADDR_DMA_US_CTRL)='1'
1636 
            and Regs_WrDin_r2(CINT_BIT_DMA_CTRL_VALID+32)='1'
1637 
            then
1638 
               usDMA_Start2_i <= not Regs_WrDin_r2(CINT_BIT_DMA_CTRL_END+32) and not Command_is_Reset_Hi;
1639 
               usDMA_Stop2_i  <= Regs_WrDin_r2(CINT_BIT_DMA_CTRL_END+32) and not Command_is_Reset_Lo;
1640 
         elsif  Regs_WrEnB_r2='1'
1641 
            and Reg_WrMuxer_Lo(CINT_ADDR_DMA_US_CTRL)='1'
1642 
            and Regs_WrDin_r2(CINT_BIT_DMA_CTRL_VALID)='1'
1643 
            then
1644 
               usDMA_Start2_i <= not Regs_WrDin_r2(CINT_BIT_DMA_CTRL_END) and not Command_is_Reset_Lo;
1645 
               usDMA_Stop2_i  <= Regs_WrDin_r2(CINT_BIT_DMA_CTRL_END) and not Command_is_Reset_Lo;
1646 
         elsif  Regs_WrEnB_r2='1'
1647 
            and Reg_WrMuxer_Hi(CINT_ADDR_DMA_US_CTRL)='1'
1648 
            and Regs_WrDin_r2(CINT_BIT_DMA_CTRL_VALID+32)='0'
1649 
            then
1650 
               usDMA_Start2_i <= not Last_Ctrl_Word_us(CINT_BIT_DMA_CTRL_END);
1651 
               usDMA_Stop2_i  <= Last_Ctrl_Word_us(CINT_BIT_DMA_CTRL_END);
1652 
         elsif  Regs_WrEnB_r2='1'
1653 
            and Reg_WrMuxer_Lo(CINT_ADDR_DMA_US_CTRL)='1'
1654 
            and Regs_WrDin_r2(CINT_BIT_DMA_CTRL_VALID)='0'
1655 
            then
1656 
               usDMA_Start2_i <= not Last_Ctrl_Word_us(CINT_BIT_DMA_CTRL_END);
1657 
               usDMA_Stop2_i  <= Last_Ctrl_Word_us(CINT_BIT_DMA_CTRL_END);
1658 
         elsif usDMA_Cmd_Ack='1' then
1659 
               usDMA_Start2_i <= '0';
1660 
               usDMA_Stop2_i  <= usDMA_Stop2_i;
1661 
         else
1662 
               usDMA_Start2_i <= usDMA_Start2_i;
1663 
               usDMA_Stop2_i  <= usDMA_Stop2_i;
1664 
         end if;
1665 
 
1666 
      end if;
1667 
   end process;
1668 
 
1669 
 
1670 
--  ------------------------------------------------------
1671 
--  DMA Downstream Registers
1672 
--  ------------------------------------------------------
1673 
 
1674 
-- -------------------------------------------------------
1675 
-- Synchronous Registered: DMA_ds_PA_i
1676 
   RxTrn_DMA_ds_PA:
1677 
   process ( trn_clk, trn_lnk_up_n)
1678 
   begin
1679 
      if trn_lnk_up_n = '1' then
1680 
         DMA_ds_PA_i     <= (OTHERS => '0');
1681 
      elsif trn_clk'event and trn_clk = '1' then
1682 
 
1683 
        if dsDMA_Channel_Rst_i = '1' then
1684 
            DMA_ds_PA_i <= (OTHERS => '0');
1685 
        else
1686 
 
1687 
          if Regs_WrEn_r2='1' and Reg_WrMuxer_Hi(CINT_ADDR_DMA_DS_PAH)='1' then
1688 
            DMA_ds_PA_i(C_DBUS_WIDTH-1 downto 32)  <= Regs_WrDin_r2(C_DBUS_WIDTH-1 downto 32);
1689 
          elsif Regs_WrEn_r2='1' and Reg_WrMuxer_Lo(CINT_ADDR_DMA_DS_PAH)='1' then
1690 
            DMA_ds_PA_i(C_DBUS_WIDTH-1 downto 32)  <= Regs_WrDin_r2(32-1 downto 0);
1691 
          else
1692 
            DMA_ds_PA_i(C_DBUS_WIDTH-1 downto 32)  <= DMA_ds_PA_i(C_DBUS_WIDTH-1 downto 32);
1693 
          end if;
1694 
 
1695 
          if Regs_WrEn_r2='1' and Reg_WrMuxer_Hi(CINT_ADDR_DMA_DS_PAL)='1' then
1696 
            DMA_ds_PA_i(32-1 downto 0)  <= Regs_WrDin_r2(C_DBUS_WIDTH-1 downto 32);
1697 
          elsif Regs_WrEn_r2='1' and Reg_WrMuxer_Lo(CINT_ADDR_DMA_DS_PAL)='1' then
1698 
            DMA_ds_PA_i(32-1 downto 0)  <= Regs_WrDin_r2(32-1 downto 0);
1699 
          else
1700 
            DMA_ds_PA_i(32-1 downto 0)  <= DMA_ds_PA_i(32-1 downto 0);
1701 
          end if;
1702 
 
1703 
        end if;
1704 
 
1705 
      end if;
1706 
   end process;
1707 
 
1708 
 
1709 
-- -------------------------------------------------------
1710 
-- Synchronous Registered: DMA_ds_HA_i
1711 
   RxTrn_DMA_ds_HA:
1712 
   process ( trn_clk, trn_lnk_up_n)
1713 
   begin
1714 
      if trn_lnk_up_n = '1' then
1715 
         DMA_ds_HA_i     <= (OTHERS => '1');
1716 
         dsHA_is_64b_i   <= '0';
1717 
      elsif trn_clk'event and trn_clk = '1' then
1718 
 
1719 
        if dsDMA_Channel_Rst_i = '1' then
1720 
            DMA_ds_HA_i <= (OTHERS => '1');
1721 
            dsHA_is_64b_i <= '0';
1722 
        else
1723 
 
1724 
          if Regs_WrEn_r2='1' and Reg_WrMuxer_Hi(CINT_ADDR_DMA_DS_HAH)='1' then
1725 
            DMA_ds_HA_i(C_DBUS_WIDTH-1 downto 32)  <= Regs_WrDin_r2(C_DBUS_WIDTH-1 downto 32);
1726 
            dsHA_is_64b_i   <=  WrDin_r2_not_Zero_Hi;
1727 
          elsif Regs_WrEn_r2='1' and Reg_WrMuxer_Lo(CINT_ADDR_DMA_DS_HAH)='1' then
1728 
            DMA_ds_HA_i(C_DBUS_WIDTH-1 downto 32)  <= Regs_WrDin_r2(32-1 downto 0);
1729 
            dsHA_is_64b_i   <=  WrDin_r2_not_Zero_Lo;
1730 
          else
1731 
            DMA_ds_HA_i(C_DBUS_WIDTH-1 downto 32)  <= DMA_ds_HA_i(C_DBUS_WIDTH-1 downto 32);
1732 
            dsHA_is_64b_i   <=  dsHA_is_64b_i;
1733 
          end if;
1734 
 
1735 
          if Regs_WrEn_r2='1' and Reg_WrMuxer_Hi(CINT_ADDR_DMA_DS_HAL)='1' then
1736 
            DMA_ds_HA_i(32-1 downto 0)  <= Regs_WrDin_r2(C_DBUS_WIDTH-1 downto 32);
1737 
          elsif Regs_WrEn_r2='1' and Reg_WrMuxer_Lo(CINT_ADDR_DMA_DS_HAL)='1' then
1738 
            DMA_ds_HA_i(32-1 downto 0)  <= Regs_WrDin_r2(32-1 downto 0);
1739 
          else
1740 
            DMA_ds_HA_i(32-1 downto 0)  <= DMA_ds_HA_i(32-1 downto 0);
1741 
          end if;
1742 
 
1743 
        end if;
1744 
 
1745 
      end if;
1746 
   end process;
1747 
 
1748 
 
1749 
-- -------------------------------------------------------
1750 
-- Synchronous output: DMA_ds_BDA_i
1751 
   Syn_Output_DMA_ds_BDA:
1752 
   process ( trn_clk, trn_lnk_up_n)
1753 
   begin
1754 
      if trn_lnk_up_n = '1' then
1755 
         DMA_ds_BDA_i    <= (OTHERS =>'0');
1756 
         dsBDA_is_64b_i  <= '0';
1757 
      elsif trn_clk'event and trn_clk = '1' then
1758 
 
1759 
        if dsDMA_Channel_Rst_i = '1' then
1760 
            DMA_ds_BDA_i <= (OTHERS => '0');
1761 
            dsBDA_is_64b_i <= '0';
1762 
        else
1763 
 
1764 
          if Regs_WrEn_r2='1' and Reg_WrMuxer_Hi(CINT_ADDR_DMA_DS_BDAH)='1' then
1765 
            DMA_ds_BDA_i(C_DBUS_WIDTH-1 downto 32)  <= Regs_WrDin_r2(C_DBUS_WIDTH-1 downto 32);
1766 
            dsBDA_is_64b_i   <=  WrDin_r2_not_Zero_Hi;
1767 
          elsif Regs_WrEn_r2='1' and Reg_WrMuxer_Lo(CINT_ADDR_DMA_DS_BDAH)='1' then
1768 
            DMA_ds_BDA_i(C_DBUS_WIDTH-1 downto 32)  <= Regs_WrDin_r2(32-1 downto 0);
1769 
            dsBDA_is_64b_i   <=  WrDin_r2_not_Zero_Lo;
1770 
          else
1771 
            DMA_ds_BDA_i(C_DBUS_WIDTH-1 downto 32)  <= DMA_ds_BDA_i(C_DBUS_WIDTH-1 downto 32);
1772 
            dsBDA_is_64b_i   <=  dsBDA_is_64b_i;
1773 
          end if;
1774 
 
1775 
          if Regs_WrEn_r2='1' and Reg_WrMuxer_Hi(CINT_ADDR_DMA_DS_BDAL)='1' then
1776 
            DMA_ds_BDA_i(32-1 downto 0)  <= Regs_WrDin_r2(C_DBUS_WIDTH-1 downto 32);
1777 
          elsif Regs_WrEn_r2='1' and Reg_WrMuxer_Lo(CINT_ADDR_DMA_DS_BDAL)='1' then
1778 
            DMA_ds_BDA_i(32-1 downto 0)  <= Regs_WrDin_r2(32-1 downto 0);
1779 
          else
1780 
            DMA_ds_BDA_i(32-1 downto 0)  <= DMA_ds_BDA_i(32-1 downto 0);
1781 
          end if;
1782 
 
1783 
        end if;
1784 
      end if;
1785 
   end process;
1786 
 
1787 
 
1788 
 
1789 
-- Synchronous Registered: DMA_ds_Length_i
1790 
   RxTrn_DMA_ds_Length:
1791 
   process ( trn_clk, trn_lnk_up_n)
1792 
   begin
1793 
      if trn_lnk_up_n = '1' then
1794 
         DMA_ds_Length_i     <= (OTHERS => '0');
1795 
         dsLeng_Hi19b_True_i <= '0';
1796 
         dsLeng_Lo7b_True_i  <= '0';
1797 
      elsif trn_clk'event and trn_clk = '1' then
1798 
 
1799 
         if dsDMA_Channel_Rst_i = '1' then
1800 
            DMA_ds_Length_i <= (OTHERS => '0');
1801 
            dsLeng_Hi19b_True_i <= '0';
1802 
            dsLeng_Lo7b_True_i  <= '0';
1803 
 
1804 
         elsif Regs_WrEn_r2='1' and Reg_WrMuxer_Hi(CINT_ADDR_DMA_DS_LENG)='1' then
1805 
            DMA_ds_Length_i(32-1 downto 0)     <= Regs_WrDin_r2(C_DBUS_WIDTH-1 downto 32);
1806 
            dsLeng_Hi19b_True_i <= Regs_WrDin_Hi19b_True_hq_r2;
1807 
            dsLeng_Lo7b_True_i  <= Regs_WrDin_Lo7b_True_hq_r2;
1808 
         elsif Regs_WrEn_r2='1' and Reg_WrMuxer_Lo(CINT_ADDR_DMA_DS_LENG)='1' then
1809 
            DMA_ds_Length_i(32-1 downto 0)     <= Regs_WrDin_r2(32-1 downto 0);
1810 
            dsLeng_Hi19b_True_i <= Regs_WrDin_Hi19b_True_lq_r2;
1811 
            dsLeng_Lo7b_True_i  <= Regs_WrDin_Lo7b_True_lq_r2;
1812 
         else
1813 
            DMA_ds_Length_i     <= DMA_ds_Length_i;
1814 
            dsLeng_Hi19b_True_i <= dsLeng_Hi19b_True_i;
1815 
            dsLeng_Lo7b_True_i  <= dsLeng_Lo7b_True_i;
1816 
 
1817 
         end if;
1818 
 
1819 
      end if;
1820 
   end process;
1821 
 
1822 
 
1823 
 
1824 
-- -------------------------------------------------------
1825 
-- Synchronous ds_Param_Modified
1826 
   SynReg_ds_Param_Modified:
1827 
   process ( trn_clk, trn_lnk_up_n)
1828 
   begin
1829 
      if trn_lnk_up_n = '1' then
1830 
         ds_Param_Modified     <= '0';
1831 
 
1832 
      elsif trn_clk'event and trn_clk = '1' then
1833 
 
1834 
        if dsDMA_Channel_Rst_i = '1'
1835 
           or dsDMA_Start_i = '1'
1836 
           or dsDMA_Start2_i = '1'
1837 
           then
1838 
             ds_Param_Modified     <= '0';
1839 
        elsif Regs_WrEn_r2='1' and
1840 
                (
1841 
--                    Reg_WrMuxer(CINT_ADDR_DMA_DS_PAH) ='1'
1842 
--                 or
1843 
                    Reg_WrMuxer_Hi(CINT_ADDR_DMA_DS_PAL) ='1'
1844 
                 or Reg_WrMuxer_Lo(CINT_ADDR_DMA_DS_PAL) ='1'
1845 
                 or Reg_WrMuxer_Hi(CINT_ADDR_DMA_DS_HAH) ='1'
1846 
                 or Reg_WrMuxer_Lo(CINT_ADDR_DMA_DS_HAH) ='1'
1847 
                 or Reg_WrMuxer_Hi(CINT_ADDR_DMA_DS_HAL) ='1'
1848 
                 or Reg_WrMuxer_Lo(CINT_ADDR_DMA_DS_HAL) ='1'
1849 
                 or Reg_WrMuxer_Hi(CINT_ADDR_DMA_DS_BDAH)='1'
1850 
                 or Reg_WrMuxer_Lo(CINT_ADDR_DMA_DS_BDAH)='1'
1851 
                 or Reg_WrMuxer_Hi(CINT_ADDR_DMA_DS_BDAL)='1'
1852 
                 or Reg_WrMuxer_Lo(CINT_ADDR_DMA_DS_BDAL)='1'
1853 
                 or Reg_WrMuxer_Hi(CINT_ADDR_DMA_DS_LENG)='1'
1854 
                 or Reg_WrMuxer_Lo(CINT_ADDR_DMA_DS_LENG)='1'
1855 
                )
1856 
           then
1857 
             ds_Param_Modified     <= '1';
1858 
        else
1859 
             ds_Param_Modified     <= ds_Param_Modified;
1860 
 
1861 
        end if;
1862 
 
1863 
      end if;
1864 
   end process;
1865 
 
1866 
 
1867 
 
1868 
-- -------------------------------------------------------
1869 
-- Synchronous output: DMA_ds_Control_i
1870 
   Syn_Output_DMA_ds_Control:
1871 
   process ( trn_clk, trn_lnk_up_n)
1872 
   begin
1873 
      if trn_lnk_up_n = '1' then
1874 
         DMA_ds_Control_i <= (OTHERS =>'0');
1875 
 
1876 
      elsif trn_clk'event and trn_clk = '1' then
1877 
 
1878 
         if     Regs_Wr_dma_V_nE_Hi_r2='1'
1879 
            and Reg_WrMuxer_Hi(CINT_ADDR_DMA_DS_CTRL)='1'
1880 
--            and Regs_WrDin_r2(CINT_BIT_DMA_CTRL_VALID+32)='1'
1881 
--            and Regs_WrDin_r2(CINT_BIT_DMA_CTRL_END+32)='0'
1882 
            and ds_Param_Modified='1'
1883 
            and dsDMA_Stop_i='0'
1884 
            then
1885 
               DMA_ds_Control_i(32-1 downto 0) <= Regs_WrDin_r2(C_DBUS_WIDTH-1 downto 8+32)& X"00";
1886 
         elsif  Regs_Wr_dma_V_nE_Lo_r2='1'
1887 
            and Reg_WrMuxer_Lo(CINT_ADDR_DMA_DS_CTRL)='1'
1888 
--            and Regs_WrDin_r2(CINT_BIT_DMA_CTRL_VALID)='1'
1889 
--            and Regs_WrDin_r2(CINT_BIT_DMA_CTRL_END)='0'
1890 
            and ds_Param_Modified='1'
1891 
            and dsDMA_Stop_i='0'
1892 
            then
1893 
               DMA_ds_Control_i(32-1 downto 0) <= Regs_WrDin_r2(32-1 downto 8)& X"00";
1894 
         elsif  Regs_Wr_dma_nV_Hi_r2='1'
1895 
            and (Reg_WrMuxer_Hi(CINT_ADDR_DMA_DS_CTRL)='1' or Reg_WrMuxer_Lo(CINT_ADDR_DMA_DS_CTRL)='1')
1896 
--            and Regs_WrDin_r2(CINT_BIT_DMA_CTRL_VALID)='0'
1897 
            then
1898 
               DMA_ds_Control_i <= Last_Ctrl_Word_ds;
1899 
         else
1900 
            DMA_ds_Control_i  <= DMA_ds_Control_i;
1901 
         end if;
1902 
 
1903 
      end if;
1904 
   end process;
1905 
 
1906 
 
1907 
-- -------------------------------------------------------
1908 
-- Synchronous Register: Last_Ctrl_Word_ds
1909 
   Hold_Last_Ctrl_Word_ds:
1910 
   process ( trn_clk, trn_lnk_up_n)
1911 
   begin
1912 
      if trn_lnk_up_n = '1' then
1913 
         Last_Ctrl_Word_ds  <= C_DEF_DMA_CTRL_WORD;
1914 
      elsif trn_clk'event and trn_clk = '1' then
1915 
 
1916 
        if dsDMA_Channel_Rst_i = '1' then
1917 
            Last_Ctrl_Word_ds <= C_DEF_DMA_CTRL_WORD;
1918 
        elsif Regs_Wr_dma_V_nE_Hi_r2='1'
1919 
          and Reg_WrMuxer_Hi(CINT_ADDR_DMA_DS_CTRL)='1'
1920 
--          and Regs_WrDin_r2(CINT_BIT_DMA_CTRL_VALID+32)='1'
1921 
--          and Regs_WrDin_r2(CINT_BIT_DMA_CTRL_END+32)='0'
1922 
          and ds_Param_Modified='1'
1923 
          and dsDMA_Stop_i='0'
1924 
          then
1925 
            Last_Ctrl_Word_ds(32-1 downto 0) <= Regs_WrDin_r2(C_DBUS_WIDTH-1 downto 8+32) & X"00";
1926 
        elsif Regs_Wr_dma_V_nE_Lo_r2='1'
1927 
          and Reg_WrMuxer_Lo(CINT_ADDR_DMA_DS_CTRL)='1'
1928 
--          and Regs_WrDin_r2(CINT_BIT_DMA_CTRL_VALID)='1'
1929 
--          and Regs_WrDin_r2(CINT_BIT_DMA_CTRL_END)='0'
1930 
          and ds_Param_Modified='1'
1931 
          and dsDMA_Stop_i='0'
1932 
          then
1933 
            Last_Ctrl_Word_ds(32-1 downto 0) <= Regs_WrDin_r2(32-1 downto 8) & X"00";
1934 
        else
1935 
            Last_Ctrl_Word_ds <= Last_Ctrl_Word_ds;
1936 
        end if;
1937 
 
1938 
      end if;
1939 
   end process;
1940 
 
1941 
 
1942 
-- -------------------------------------------------------
1943 
-- Synchronous output: DMA_ds_Start_Stop
1944 
   Syn_Output_DMA_ds_Start_Stop:
1945 
   process ( trn_clk, trn_lnk_up_n)
1946 
   begin
1947 
      if trn_lnk_up_n = '1' then
1948 
         dsDMA_Start_i  <= '0';
1949 
         dsDMA_Stop_i   <= '0';
1950 
 
1951 
      elsif trn_clk'event and trn_clk = '1' then
1952 
 
1953 
         if     Regs_WrEnA_r2='1'
1954 
            and Reg_WrMuxer_Hi(CINT_ADDR_DMA_DS_CTRL)='1'
1955 
            and Regs_WrDin_r2(CINT_BIT_DMA_CTRL_VALID+32)='1'
1956 
            then
1957 
               dsDMA_Start_i <= not Regs_WrDin_r2(CINT_BIT_DMA_CTRL_END+32)
1958 
                            and not dsDMA_Stop_i
1959 
                            and not Command_is_Reset_Hi
1960 
                            and ds_Param_Modified
1961 
                            ;
1962 
               dsDMA_Stop_i  <= Regs_WrDin_r2(CINT_BIT_DMA_CTRL_END+32)
1963 
                            and not Command_is_Reset_Hi
1964 
                            ;
1965 
         elsif  Regs_WrEnA_r2='1'
1966 
            and Reg_WrMuxer_Lo(CINT_ADDR_DMA_DS_CTRL)='1'
1967 
            and Regs_WrDin_r2(CINT_BIT_DMA_CTRL_VALID)='1'
1968 
            then
1969 
               dsDMA_Start_i <= not Regs_WrDin_r2(CINT_BIT_DMA_CTRL_END)
1970 
                            and not dsDMA_Stop_i
1971 
                            and not Command_is_Reset_Lo
1972 
                            and ds_Param_Modified
1973 
                            ;
1974 
               dsDMA_Stop_i  <= Regs_WrDin_r2(CINT_BIT_DMA_CTRL_END)
1975 
                            and not Command_is_Reset_Lo
1976 
                            ;
1977 
         elsif  Regs_WrEnA_r2='1'
1978 
            and (Reg_WrMuxer_Hi(CINT_ADDR_DMA_DS_CTRL)='1' or Reg_WrMuxer_Lo(CINT_ADDR_DMA_DS_CTRL)='1')
1979 
            and Regs_WrDin_r2(CINT_BIT_DMA_CTRL_VALID+32)='0'
1980 
            then
1981 
               dsDMA_Start_i <= not Last_Ctrl_Word_ds(CINT_BIT_DMA_CTRL_END)
1982 
                            and ds_Param_Modified
1983 
                            ;
1984 
               dsDMA_Stop_i  <= Last_Ctrl_Word_ds(CINT_BIT_DMA_CTRL_END);
1985 
         elsif dsDMA_Cmd_Ack='1'
1986 
            then
1987 
               dsDMA_Start_i <= '0';
1988 
               dsDMA_Stop_i  <= dsDMA_Stop_i;
1989 
         else
1990 
               dsDMA_Start_i <= dsDMA_Start_i;
1991 
               dsDMA_Stop_i  <= dsDMA_Stop_i;
1992 
         end if;
1993 
 
1994 
      end if;
1995 
   end process;
1996 
 
1997 
 
1998 
-- -------------------------------------------------------
1999 
-- Synchronous output: DMA_ds_Start2_Stop2
2000 
   Syn_Output_DMA_ds_Start2_Stop2:
2001 
   process ( trn_clk, trn_lnk_up_n)
2002 
   begin
2003 
      if trn_lnk_up_n = '1' then
2004 
         dsDMA_Start2_i <= '0';
2005 
         dsDMA_Stop2_i  <= '0';
2006 
 
2007 
      elsif trn_clk'event and trn_clk = '1' then
2008 
 
2009 
         if dsDMA_Channel_Rst_i='1' then
2010 
               dsDMA_Start2_i <= '0';
2011 
               dsDMA_Stop2_i  <= '0';
2012 
         elsif     Regs_WrEnB_r2='1'
2013 
            and Reg_WrMuxer_Hi(CINT_ADDR_DMA_DS_CTRL)='1'
2014 
            and Regs_WrDin_r2(CINT_BIT_DMA_CTRL_VALID+32)='1'
2015 
            then
2016 
               dsDMA_Start2_i <= not Regs_WrDin_r2(CINT_BIT_DMA_CTRL_END+32) and not Command_is_Reset_Hi;
2017 
               dsDMA_Stop2_i  <= Regs_WrDin_r2(CINT_BIT_DMA_CTRL_END+32) and not Command_is_Reset_Hi;
2018 
         elsif  Regs_WrEnB_r2='1'
2019 
            and Reg_WrMuxer_Lo(CINT_ADDR_DMA_DS_CTRL)='1'
2020 
            and Regs_WrDin_r2(CINT_BIT_DMA_CTRL_VALID)='1'
2021 
            then
2022 
               dsDMA_Start2_i <= not Regs_WrDin_r2(CINT_BIT_DMA_CTRL_END) and not Command_is_Reset_Lo;
2023 
               dsDMA_Stop2_i  <= Regs_WrDin_r2(CINT_BIT_DMA_CTRL_END) and not Command_is_Reset_Lo;
2024 
         elsif  Regs_WrEnB_r2='1'
2025 
            and Reg_WrMuxer_Hi(CINT_ADDR_DMA_DS_CTRL)='1'
2026 
            and Regs_WrDin_r2(CINT_BIT_DMA_CTRL_VALID+32)='0'
2027 
            then
2028 
               dsDMA_Start2_i <= not Last_Ctrl_Word_ds(CINT_BIT_DMA_CTRL_END);
2029 
               dsDMA_Stop2_i  <= Last_Ctrl_Word_ds(CINT_BIT_DMA_CTRL_END);
2030 
         elsif  Regs_WrEnB_r2='1'
2031 
            and Reg_WrMuxer_Lo(CINT_ADDR_DMA_DS_CTRL)='1'
2032 
            and Regs_WrDin_r2(CINT_BIT_DMA_CTRL_VALID)='0'
2033 
            then
2034 
               dsDMA_Start2_i <= not Last_Ctrl_Word_ds(CINT_BIT_DMA_CTRL_END);
2035 
               dsDMA_Stop2_i  <= Last_Ctrl_Word_ds(CINT_BIT_DMA_CTRL_END);
2036 
         elsif dsDMA_Cmd_Ack='1' then
2037 
               dsDMA_Start2_i <= '0';
2038 
               dsDMA_Stop2_i  <= dsDMA_Stop2_i;
2039 
         else
2040 
               dsDMA_Start2_i <= dsDMA_Start2_i;
2041 
               dsDMA_Stop2_i  <= dsDMA_Stop2_i;
2042 
         end if;
2043 
 
2044 
      end if;
2045 
   end process;
2046 
 
2047 
 
2048 
------------------------------------------------------------------------
2049 
--                          Reset signals                             --
2050 
------------------------------------------------------------------------
2051 
 
2052 
-- --------------------------------------
2053 
-- Identification: Command_is_Reset
2054 
--
2055 
   Synch_Capture_Command_is_Reset:
2056 
   process ( trn_clk, trn_lnk_up_n)
2057 
   begin
2058 
      if trn_lnk_up_n = '1' then
2059 
         Command_is_Reset_Hi    <= '0';
2060 
         Command_is_Reset_Lo    <= '0';
2061 
 
2062 
      elsif trn_clk'event and trn_clk = '1' then
2063 
         if Regs_WrDin_r1(C_FEAT_BITS_WIDTH-1+32 downto 32)=C_CHANNEL_RST_BITS then
2064 
            Command_is_Reset_Hi    <= '1';
2065 
         else
2066 
            Command_is_Reset_Hi    <= '0';
2067 
         end if;
2068 
 
2069 
         if Regs_WrDin_r1(C_FEAT_BITS_WIDTH-1 downto 0)=C_CHANNEL_RST_BITS then
2070 
            Command_is_Reset_Lo    <= '1';
2071 
         else
2072 
            Command_is_Reset_Lo    <= '0';
2073 
         end if;
2074 
      end if;
2075 
   end process;
2076 
 
2077 
 
2078 
-- --------------------------------------
2079 
-- Identification: Command_is_Host_iClr
2080 
--
2081 
   Synch_Capture_Command_is_Host_iClr:
2082 
   process ( trn_clk, trn_lnk_up_n)
2083 
   begin
2084 
      if trn_lnk_up_n = '1' then
2085 
         Command_is_Host_iClr_Hi    <= '0';
2086 
         Command_is_Host_iClr_Lo    <= '0';
2087 
 
2088 
      elsif trn_clk'event and trn_clk = '1' then
2089 
         if Regs_WrDin_r1(C_FEAT_BITS_WIDTH-1+32 downto 32)=C_HOST_ICLR_BITS then
2090 
            Command_is_Host_iClr_Hi    <= '1';
2091 
         else
2092 
            Command_is_Host_iClr_Hi    <= '0';
2093 
         end if;
2094 
 
2095 
         if Regs_WrDin_r1(C_FEAT_BITS_WIDTH-1 downto 0)=C_HOST_ICLR_BITS then
2096 
            Command_is_Host_iClr_Lo    <= '1';
2097 
         else
2098 
            Command_is_Host_iClr_Lo    <= '0';
2099 
         end if;
2100 
      end if;
2101 
   end process;
2102 
 
2103 
-------------------------------------------
2104 
-- Synchronous output: usDMA_Channel_Rst_i
2105 
--
2106 
   Syn_Output_usDMA_Channel_Rst:
2107 
   process ( trn_clk, trn_lnk_up_n)
2108 
   begin
2109 
      if trn_lnk_up_n = '1' then
2110 
         usDMA_Channel_Rst_i <= '1';
2111 
      elsif trn_clk'event and trn_clk = '1' then
2112 
 
2113 
         usDMA_Channel_Rst_i <= (Regs_Wr_dma_V_Hi_r2
2114 
                            and Reg_WrMuxer_Hi(CINT_ADDR_DMA_US_CTRL)
2115 
--                            and Regs_WrDin_r2(CINT_BIT_DMA_CTRL_VALID+32)
2116 
                            and Command_is_Reset_Hi
2117 
                                )
2118 
                            or  (Regs_Wr_dma_V_LO_r2
2119 
                            and Reg_WrMuxer_Lo(CINT_ADDR_DMA_US_CTRL)
2120 
--                            and Regs_WrDin_r2(CINT_BIT_DMA_CTRL_VALID)
2121 
                            and Command_is_Reset_Lo
2122 
                                )
2123 
                            ;
2124 
      end if;
2125 
   end process;
2126 
 
2127 
 
2128 
 
2129 
-------------------------------------------
2130 
-- Synchronous output: dsDMA_Channel_Rst_i
2131 
--
2132 
   Syn_Output_dsDMA_Channel_Rst:
2133 
   process ( trn_clk, trn_lnk_up_n)
2134 
   begin
2135 
      if trn_lnk_up_n = '1' then
2136 
         dsDMA_Channel_Rst_i <= '1';
2137 
      elsif trn_clk'event and trn_clk = '1' then
2138 
 
2139 
         dsDMA_Channel_Rst_i <= (Regs_Wr_dma_V_Hi_r2
2140 
                            and Reg_WrMuxer_Hi(CINT_ADDR_DMA_DS_CTRL)
2141 
--                            and Regs_WrDin_r2(CINT_BIT_DMA_CTRL_VALID+32)
2142 
                            and Command_is_Reset_Hi
2143 
                            )
2144 
                            or
2145 
                           (Regs_Wr_dma_V_Lo_r2
2146 
                            and Reg_WrMuxer_Lo(CINT_ADDR_DMA_DS_CTRL)
2147 
--                            and Regs_WrDin_r2(CINT_BIT_DMA_CTRL_VALID)
2148 
                            and Command_is_Reset_Lo
2149 
                            )
2150 
                            ;
2151 
      end if;
2152 
   end process;
2153 
 
2154 
 
2155 
-- -----------------------------------------------
2156 
-- Synchronous output: MRd_Channel_Rst_i
2157 
--
2158 
   Syn_Output_MRd_Channel_Rst:
2159 
   process ( trn_clk, trn_lnk_up_n)
2160 
   begin
2161 
      if trn_lnk_up_n = '1' then
2162 
         MRd_Channel_Rst_i <= '1';
2163 
      elsif trn_clk'event and trn_clk = '1' then
2164 
 
2165 
         MRd_Channel_Rst_i    <= Regs_WrEn_r2
2166 
                             and (
2167 
                                 (Reg_WrMuxer_Hi(CINT_ADDR_MRD_CTRL)
2168 
                                  and Command_is_Reset_Hi)
2169 
                             or
2170 
                                 (Reg_WrMuxer_Lo(CINT_ADDR_MRD_CTRL)
2171 
                                  and Command_is_Reset_Lo)
2172 
                             )
2173 
                             ;
2174 
      end if;
2175 
   end process;
2176 
 
2177 
 
2178 
-- -----------------------------------------------
2179 
-- Synchronous output: Tx_Reset_i
2180 
--
2181 
   Syn_Output_Tx_Reset:
2182 
   process ( trn_clk, trn_lnk_up_n)
2183 
   begin
2184 
      if trn_lnk_up_n = '1' then
2185 
         Tx_Reset_i   <= '1';
2186 
      elsif trn_clk'event and trn_clk = '1' then
2187 
 
2188 
         Tx_Reset_i   <= Regs_WrEn_r2
2189 
                     and ((Reg_WrMuxer_Hi(CINT_ADDR_TX_CTRL)
2190 
                     and Command_is_Reset_Hi)
2191 
                     or  (Reg_WrMuxer_Lo(CINT_ADDR_TX_CTRL)
2192 
                     and Command_is_Reset_Lo))
2193 
                     ;
2194 
      end if;
2195 
   end process;
2196 
 
2197 
 
2198 
-- -----------------------------------------------
2199 
-- Synchronous output: eb_FIFO_Rst_i
2200 
--
2201 
   Syn_Output_eb_FIFO_Rst:
2202 
   process ( trn_clk, trn_lnk_up_n)
2203 
   begin
2204 
      if trn_lnk_up_n = '1' then
2205 
         eb_FIFO_Rst_i    <= '1';
2206 
         eb_FIFO_Rst_b3   <= '1';
2207 
         eb_FIFO_Rst_b2   <= '1';
2208 
         eb_FIFO_Rst_b1   <= '1';
2209 
      elsif trn_clk'event and trn_clk = '1' then
2210 
 
2211 
         eb_FIFO_Rst_i   <= eb_FIFO_Rst_b1 or eb_FIFO_Rst_b2 or eb_FIFO_Rst_b3;
2212 
         eb_FIFO_Rst_b3  <= eb_FIFO_Rst_b2;
2213 
         eb_FIFO_Rst_b2  <= eb_FIFO_Rst_b1;
2214 
         eb_FIFO_Rst_b1  <= Regs_WrEn_r2
2215 
                         and ((Reg_WrMuxer_Hi(CINT_ADDR_EB_STACON)
2216 
                         and Command_is_Reset_Hi)
2217 
                         or  (Reg_WrMuxer_Lo(CINT_ADDR_EB_STACON)
2218 
                         and Command_is_Reset_Lo))
2219 
                         ;
2220 
      end if;
2221 
   end process;
2222 
 
2223 
 
2224 
-- -----------------------------------------------
2225 
-- Synchronous output: protocol_rst
2226 
--
2227 
--            !!!  reset by trn_reset_n  !!!
2228 
--
2229 
   Syn_Output_protocol_rst:
2230 
   process ( trn_clk, trn_reset_n)
2231 
   begin
2232 
      if trn_reset_n = '0' then
2233 
         protocol_rst_i   <= '1';
2234 
         protocol_rst_b1  <= '1';
2235 
         protocol_rst_b2  <= '1';
2236 
      elsif trn_clk'event and trn_clk = '1' then
2237 
 
2238 
         protocol_rst_i  <= protocol_rst_b1 or protocol_rst_b2;
2239 
         protocol_rst_b1 <= protocol_rst_b2;
2240 
         protocol_rst_b2 <= Regs_WrEn_r2
2241 
                         and ((Reg_WrMuxer_Hi(CINT_ADDR_PROTOCOL_STACON)
2242 
                         and Command_is_Reset_Hi)
2243 
                         or  (Reg_WrMuxer_Lo(CINT_ADDR_PROTOCOL_STACON)
2244 
                         and Command_is_Reset_Lo))
2245 
                         ;
2246 
      end if;
2247 
   end process;
2248 
 
2249 
 
2250 
-- -----------------------------------------------
2251 
-- Synchronous Calculation: DMA_us_Transf_Bytes
2252 
--
2253 
   Syn_Calc_DMA_us_Transf_Bytes:
2254 
   process ( trn_clk, trn_lnk_up_n)
2255 
   begin
2256 
      if trn_lnk_up_n = '1' then
2257 
         DMA_us_Transf_Bytes_i   <= (OTHERS=>'0');
2258 
      elsif trn_clk'event and trn_clk = '1' then
2259 
 
2260 
         if usDMA_Channel_Rst_i='1' then
2261 
            DMA_us_Transf_Bytes_i   <= (OTHERS=>'0');
2262 
         elsif us_DMA_Bytes_Add='1' then
2263 
            DMA_us_Transf_Bytes_i(32-1 downto 0)
2264 
                                    <= DMA_us_Transf_Bytes_i(32-1 downto 0)
2265 
                                    +  us_DMA_Bytes;
2266 
         else
2267 
            DMA_us_Transf_Bytes_i   <= DMA_us_Transf_Bytes_i;
2268 
         end if;
2269 
      end if;
2270 
   end process;
2271 
 
2272 
 
2273 
-- -----------------------------------------------
2274 
-- Synchronous Calculation: DMA_ds_Transf_Bytes
2275 
--
2276 
   Syn_Calc_DMA_ds_Transf_Bytes:
2277 
   process ( trn_clk, trn_lnk_up_n)
2278 
   begin
2279 
      if trn_lnk_up_n = '1' then
2280 
         DMA_ds_Transf_Bytes_i   <= (OTHERS=>'0');
2281 
      elsif trn_clk'event and trn_clk = '1' then
2282 
 
2283 
         if dsDMA_Channel_Rst_i='1' then
2284 
            DMA_ds_Transf_Bytes_i   <= (OTHERS=>'0');
2285 
         elsif ds_DMA_Bytes_Add='1' then
2286 
            DMA_ds_Transf_Bytes_i(32-1 downto 0)
2287 
                                    <= DMA_ds_Transf_Bytes_i(32-1 downto 0)
2288 
                                    +  ds_DMA_Bytes;
2289 
         else
2290 
            DMA_ds_Transf_Bytes_i   <= DMA_ds_Transf_Bytes_i;
2291 
         end if;
2292 
      end if;
2293 
   end process;
2294 
 
2295 
 
2296 
 
2297 
----------------------------------------------------------
2298 
---------------  Tx reading registers  -------------------
2299 
----------------------------------------------------------
2300 
 
2301 
----------------------------------------------------------
2302 
-- Synch Register:  Read Selection
2303 
--
2304 
   Tx_DMA_Reg_RdMuxer:
2305 
   process ( trn_clk, trn_lnk_up_n)
2306 
   begin
2307 
      if trn_lnk_up_n = '1' then
2308 
           Reg_RdMuxer_Hi     <= (Others =>'0');
2309 
           Reg_RdMuxer_Lo     <= (Others =>'0');
2310 
 
2311 
      elsif trn_clk'event and trn_clk = '1' then
2312 
 
2313 
         FOR k IN 0 TO C_NUM_OF_ADDRESSES-1 LOOP
2314 
            if Regs_RdAddr_i(C_DECODE_BIT_TOP downto C_DECODE_BIT_BOT)= C_REGS_BASE_ADDR(C_DECODE_BIT_TOP downto C_DECODE_BIT_BOT)
2315 
               and Regs_RdAddr_i(C_DECODE_BIT_BOT-1 downto 2)=CONV_STD_LOGIC_VECTOR(k, C_DECODE_BIT_BOT-2)
2316 
               and Regs_RdAddr_i(2-1 downto 0)="00"
2317 
               then
2318 
               Reg_RdMuxer_Hi(k) <= '1';
2319 
            else
2320 
               Reg_RdMuxer_Hi(k) <= '0';
2321 
            end if;
2322 
         END LOOP;
2323 
 
2324 
         if Regs_RdAddr_i(C_DECODE_BIT_TOP downto C_DECODE_BIT_BOT)= C_ALL_ONES(C_DECODE_BIT_TOP downto C_DECODE_BIT_BOT)
2325 
            and Regs_RdAddr_i(C_DECODE_BIT_BOT-1 downto 2)=C_ALL_ONES(C_DECODE_BIT_BOT-1 downto 2)
2326 
            and Regs_RdAddr_i(2-1 downto 0)="00"
2327 
            then
2328 
            Reg_RdMuxer_Lo(0) <= '1';
2329 
         else
2330 
            Reg_RdMuxer_Lo(0) <= '0';
2331 
         end if;
2332 
         FOR k IN 1 TO C_NUM_OF_ADDRESSES-1 LOOP
2333 
            if Regs_RdAddr_i(C_DECODE_BIT_TOP downto C_DECODE_BIT_BOT)= C_REGS_BASE_ADDR(C_DECODE_BIT_TOP downto C_DECODE_BIT_BOT)
2334 
               and Regs_RdAddr_i(C_DECODE_BIT_BOT-1 downto 2)=CONV_STD_LOGIC_VECTOR(k-1, C_DECODE_BIT_BOT-2)
2335 
               and Regs_RdAddr_i(2-1 downto 0)="00"
2336 
               then
2337 
               Reg_RdMuxer_Lo(k) <= '1';
2338 
            else
2339 
               Reg_RdMuxer_Lo(k) <= '0';
2340 
            end if;
2341 
         END LOOP;
2342 
 
2343 
      end if;
2344 
   end process;
2345 
 
2346 
 
2347 3 weng_ziti 
------------------------------------------------------------
2348 
---- Synch Register:  CTL_TTake
2349 
----
2350 
--   Syn_CTL_ttake:
2351 
--   process ( trn_clk, trn_lnk_up_n)
2352 
--   begin
2353 
--      if trn_lnk_up_n = '1' then
2354 
--         ctl_ttake_i      <= '0';
2355 
--         ctl_t_read_Hi_r1 <= '0';
2356 
--         ctl_t_read_Lo_r1 <= '0';
2357 
--         CTL_read_counter <= (OTHERS=>'0');
2358 
--
2359 
--      elsif trn_clk'event and trn_clk = '1' then
2360 
--         ctl_t_read_Hi_r1 <= Reg_RdMuxer_Hi(CINT_ADDR_CTL_CLASS);
2361 
--         ctl_t_read_Lo_r1 <= Reg_RdMuxer_Lo(CINT_ADDR_CTL_CLASS);
2362 
--         ctl_ttake_i  <= (Reg_RdMuxer_Hi(CINT_ADDR_CTL_CLASS) and not ctl_t_read_Hi_r1)
2363 
--                      or (Reg_RdMuxer_Lo(CINT_ADDR_CTL_CLASS) and not ctl_t_read_Lo_r1)
2364 
--                      ;
2365 
--         if ctl_reset_i='1' then
2366 
--            CTL_read_counter <= (OTHERS=>'0');
2367 
--         else
2368 
--            CTL_read_counter <= CTL_read_counter + ctl_ttake_i;
2369 
--         end if;
2370 
--
2371 
--      end if;
2372 
--   end process;
2373 
--
2374 
------------------------------------------------------------
2375 
---- Synch Register:  class_CTL_Status
2376 
----
2377 
--   Syn_class_CTL_Status:
2378 
--   process ( trn_clk, trn_lnk_up_n)
2379 
--   begin
2380 
--      if trn_lnk_up_n = '1' then
2381 
--         class_CTL_Status_i      <= (OTHERS=>'0');
2382 
--
2383 
--      elsif trn_clk'event and trn_clk = '1' then
2384 
--         class_CTL_Status_i(C_DBUS_WIDTH/2-1 downto 0)      <= ctl_status;
2385 
--
2386 
--      end if;
2387 
--   end process;
2388 2 weng_ziti 
 
2389 
 
2390 
-- -------------------------------------------------------
2391 
--
2392 
   Sys_Int_Status_i     <= (
2393 3 weng_ziti 
--                            CINT_BIT_DLM_IN_ISR     => DLM_irq     ,
2394 
--                            CINT_BIT_CTL_IN_ISR     => CTL_irq     ,
2395 
--                            CINT_BIT_DAQ_IN_ISR     => DAQ_irq     ,
2396 2 weng_ziti 
 
2397 
                            CINT_BIT_DSTOUT_IN_ISR  => DMA_ds_Tout ,
2398 
                            CINT_BIT_USTOUT_IN_ISR  => DMA_us_Tout ,
2399 
 
2400 
                            CINT_BIT_INTGEN_IN_ISR  => IG_Asserting,
2401 
                            CINT_BIT_DS_DONE_IN_ISR => DMA_ds_Done ,
2402 
                            CINT_BIT_US_DONE_IN_ISR => DMA_us_Done ,
2403 
                            OTHERS                  => '0'
2404 
                           );
2405 
 
2406 
   --------------------------------------------------------------------------
2407 
   -- Upstream Registers
2408 
   --------------------------------------------------------------------------
2409 
 
2410 
   --  Peripheral Address Start point
2411 
   DMA_us_PA_o_Hi(C_DBUS_WIDTH-1 downto C_DBUS_WIDTH/2)
2412 
      <= DMA_us_PA_i(C_DBUS_WIDTH-1 downto C_DBUS_WIDTH/2) when Reg_RdMuxer_Hi(CINT_ADDR_DMA_US_PAH)='1'
2413 
         else (Others=>'0');
2414 
 
2415 
   DMA_us_PA_o_Hi(C_DBUS_WIDTH/2-1 downto 0)
2416 
      <= DMA_us_PA_i(C_DBUS_WIDTH/2-1 downto 0) when Reg_RdMuxer_Hi(CINT_ADDR_DMA_US_PAL)='1'
2417 
         else (Others=>'0');
2418 
 
2419 
 
2420 
   --  Host Address Start point
2421 
   DMA_us_HA_o_Hi(C_DBUS_WIDTH-1 downto C_DBUS_WIDTH/2)
2422 
      <= DMA_us_HA_i(C_DBUS_WIDTH-1 downto C_DBUS_WIDTH/2) when Reg_RdMuxer_Hi(CINT_ADDR_DMA_US_HAH)='1'
2423 
         else (Others=>'0');
2424 
 
2425 
   DMA_us_HA_o_Hi(C_DBUS_WIDTH/2-1 downto 0)
2426 
      <= DMA_us_HA_i(C_DBUS_WIDTH/2-1 downto 0) when Reg_RdMuxer_Hi(CINT_ADDR_DMA_US_HAL)='1'
2427 
         else (Others=>'0');
2428 
 
2429 
 
2430 
   --  Next Descriptor Address
2431 
   DMA_us_BDA_o_Hi(C_DBUS_WIDTH-1 downto C_DBUS_WIDTH/2)
2432 
      <= DMA_us_BDA_i(C_DBUS_WIDTH-1 downto C_DBUS_WIDTH/2) when Reg_RdMuxer_Hi(CINT_ADDR_DMA_US_BDAH)='1'
2433 
         else (Others=>'0');
2434 
 
2435 
   DMA_us_BDA_o_Hi(C_DBUS_WIDTH/2-1 downto 0)
2436 
      <= DMA_us_BDA_i(C_DBUS_WIDTH/2-1 downto 0) when Reg_RdMuxer_Hi(CINT_ADDR_DMA_US_BDAL)='1'
2437 
         else (Others=>'0');
2438 
 
2439 
   --  Length
2440 
   DMA_us_Length_o_Hi(32-1 downto 0)
2441 
      <= DMA_us_Length_i(32-1 downto 0) when Reg_RdMuxer_Hi(CINT_ADDR_DMA_US_LENG)='1'
2442 
         else (Others=>'0');
2443 
 
2444 
   --  Control word
2445 
   DMA_us_Control_o_Hi(32-1 downto 0)
2446 
      <= DMA_us_Control_i(32-1 downto 0) when Reg_RdMuxer_Hi(CINT_ADDR_DMA_US_CTRL)='1'
2447 
         else (Others=>'0');
2448 
 
2449 
   --  Status (Read only)
2450 
   DMA_us_Status_o_Hi(32-1 downto 0)
2451 
      <= DMA_us_Status_i(32-1 downto 0) when Reg_RdMuxer_Hi(CINT_ADDR_DMA_US_STA)='1'
2452 
         else (Others=>'0');
2453 
 
2454 
   --  Tranferred bytes (Read only)
2455 
   DMA_us_Transf_Bytes_o_Hi(32-1 downto 0)
2456 
      <= DMA_us_Transf_Bytes_i(32-1 downto 0) when Reg_RdMuxer_Hi(CINT_ADDR_US_TRANSF_BC)='1'
2457 
         else (Others=>'0');
2458 
 
2459 
 
2460 
   --  Peripheral Address Start point
2461 
   DMA_us_PA_o_Lo(C_DBUS_WIDTH-1 downto C_DBUS_WIDTH/2)
2462 
      <= DMA_us_PA_i(C_DBUS_WIDTH-1 downto C_DBUS_WIDTH/2) when Reg_RdMuxer_Lo(CINT_ADDR_DMA_US_PAH)='1'
2463 
         else (Others=>'0');
2464 
 
2465 
   DMA_us_PA_o_Lo(C_DBUS_WIDTH/2-1 downto 0)
2466 
      <= DMA_us_PA_i(C_DBUS_WIDTH/2-1 downto 0) when Reg_RdMuxer_Lo(CINT_ADDR_DMA_US_PAL)='1'
2467 
         else (Others=>'0');
2468 
 
2469 
 
2470 
   --  Host Address Start point
2471 
   DMA_us_HA_o_Lo(C_DBUS_WIDTH-1 downto C_DBUS_WIDTH/2)
2472 
      <= DMA_us_HA_i(C_DBUS_WIDTH-1 downto C_DBUS_WIDTH/2) when Reg_RdMuxer_Lo(CINT_ADDR_DMA_US_HAH)='1'
2473 
         else (Others=>'0');
2474 
 
2475 
   DMA_us_HA_o_Lo(C_DBUS_WIDTH/2-1 downto 0)
2476 
      <= DMA_us_HA_i(C_DBUS_WIDTH/2-1 downto 0) when Reg_RdMuxer_Lo(CINT_ADDR_DMA_US_HAL)='1'
2477 
         else (Others=>'0');
2478 
 
2479 
 
2480 
   --  Next Descriptor Address
2481 
   DMA_us_BDA_o_Lo(C_DBUS_WIDTH-1 downto C_DBUS_WIDTH/2)
2482 
      <= DMA_us_BDA_i(C_DBUS_WIDTH-1 downto C_DBUS_WIDTH/2) when Reg_RdMuxer_Lo(CINT_ADDR_DMA_US_BDAH)='1'
2483 
         else (Others=>'0');
2484 
 
2485 
   DMA_us_BDA_o_Lo(C_DBUS_WIDTH/2-1 downto 0)
2486 
      <= DMA_us_BDA_i(C_DBUS_WIDTH/2-1 downto 0) when Reg_RdMuxer_Lo(CINT_ADDR_DMA_US_BDAL)='1'
2487 
         else (Others=>'0');
2488 
 
2489 
   --  Length
2490 
   DMA_us_Length_o_Lo(32-1 downto 0)
2491 
      <= DMA_us_Length_i(32-1 downto 0) when Reg_RdMuxer_Lo(CINT_ADDR_DMA_US_LENG)='1'
2492 
         else (Others=>'0');
2493 
 
2494 
   --  Control word
2495 
   DMA_us_Control_o_Lo(32-1 downto 0)
2496 
      <= DMA_us_Control_i(32-1 downto 0) when Reg_RdMuxer_Lo(CINT_ADDR_DMA_US_CTRL)='1'
2497 
         else (Others=>'0');
2498 
 
2499 
   --  Status (Read only)
2500 
   DMA_us_Status_o_Lo(32-1 downto 0)
2501 
      <= DMA_us_Status_i(32-1 downto 0) when Reg_RdMuxer_Lo(CINT_ADDR_DMA_US_STA)='1'
2502 
         else (Others=>'0');
2503 
 
2504 
   --  Tranferred bytes (Read only)
2505 
   DMA_us_Transf_Bytes_o_Lo(32-1 downto 0)
2506 
      <= DMA_us_Transf_Bytes_i(32-1 downto 0) when Reg_RdMuxer_Lo(CINT_ADDR_US_TRANSF_BC)='1'
2507 
         else (Others=>'0');
2508 
 
2509 
   --------------------------------------------------------------------------
2510 
   -- Downstream Registers
2511 
   --------------------------------------------------------------------------
2512 
 
2513 
   --  Peripheral Address Start point
2514 
   DMA_ds_PA_o_Hi(C_DBUS_WIDTH-1 downto C_DBUS_WIDTH/2)
2515 
      <= DMA_ds_PA_i(C_DBUS_WIDTH-1 downto C_DBUS_WIDTH/2) when Reg_RdMuxer_Hi(CINT_ADDR_DMA_DS_PAH)='1'
2516 
         else (Others=>'0');
2517 
 
2518 
   DMA_ds_PA_o_Hi(C_DBUS_WIDTH/2-1 downto 0)
2519 
      <= DMA_ds_PA_i(C_DBUS_WIDTH/2-1 downto 0) when Reg_RdMuxer_Hi(CINT_ADDR_DMA_DS_PAL)='1'
2520 
         else (Others=>'0');
2521 
 
2522 
   --  Host Address Start point
2523 
   DMA_ds_HA_o_Hi(C_DBUS_WIDTH-1 downto C_DBUS_WIDTH/2)
2524 
      <= DMA_ds_HA_i(C_DBUS_WIDTH-1 downto C_DBUS_WIDTH/2) when Reg_RdMuxer_Hi(CINT_ADDR_DMA_DS_HAH)='1'
2525 
         else (Others=>'0');
2526 
 
2527 
   DMA_ds_HA_o_Hi(C_DBUS_WIDTH/2-1 downto 0)
2528 
      <= DMA_ds_HA_i(C_DBUS_WIDTH/2-1 downto 0) when Reg_RdMuxer_Hi(CINT_ADDR_DMA_DS_HAL)='1'
2529 
         else (Others=>'0');
2530 
 
2531 
   --  Next Descriptor Address
2532 
   DMA_ds_BDA_o_Hi(C_DBUS_WIDTH-1 downto C_DBUS_WIDTH/2)
2533 
      <= DMA_ds_BDA_i(C_DBUS_WIDTH-1 downto C_DBUS_WIDTH/2) when Reg_RdMuxer_Hi(CINT_ADDR_DMA_DS_BDAH)='1'
2534 
         else (Others=>'0');
2535 
 
2536 
   DMA_ds_BDA_o_Hi(C_DBUS_WIDTH/2-1 downto 0)
2537 
      <= DMA_ds_BDA_i(C_DBUS_WIDTH/2-1 downto 0) when Reg_RdMuxer_Hi(CINT_ADDR_DMA_DS_BDAL)='1'
2538 
         else (Others=>'0');
2539 
 
2540 
   --  Length
2541 
   DMA_ds_Length_o_Hi(32-1 downto 0)
2542 
      <= DMA_ds_Length_i(32-1 downto 0) when Reg_RdMuxer_Hi(CINT_ADDR_DMA_DS_LENG)='1'
2543 
         else (Others=>'0');
2544 
 
2545 
   --  Control word
2546 
   DMA_ds_Control_o_Hi(32-1 downto 0)
2547 
      <= DMA_ds_Control_i(32-1 downto 0) when Reg_RdMuxer_Hi(CINT_ADDR_DMA_DS_CTRL)='1'
2548 
         else (Others=>'0');
2549 
 
2550 
   --  Status (Read only)
2551 
   DMA_ds_Status_o_Hi(32-1 downto 0)
2552 
      <= DMA_ds_Status_i(32-1 downto 0) when Reg_RdMuxer_Hi(CINT_ADDR_DMA_DS_STA)='1'
2553 
         else (Others=>'0');
2554 
 
2555 
   --  Tranferred bytes (Read only)
2556 
   DMA_ds_Transf_Bytes_o_Hi(32-1 downto 0)
2557 
      <= DMA_ds_Transf_Bytes_i(32-1 downto 0) when Reg_RdMuxer_Hi(CINT_ADDR_DS_TRANSF_BC)='1'
2558 
         else (Others=>'0');
2559 
 
2560 
   --  Peripheral Address Start point
2561 
   DMA_ds_PA_o_Lo(C_DBUS_WIDTH-1 downto C_DBUS_WIDTH/2)
2562 
      <= DMA_ds_PA_i(C_DBUS_WIDTH-1 downto C_DBUS_WIDTH/2) when Reg_RdMuxer_Lo(CINT_ADDR_DMA_DS_PAH)='1'
2563 
         else (Others=>'0');
2564 
 
2565 
   DMA_ds_PA_o_Lo(C_DBUS_WIDTH/2-1 downto 0)
2566 
      <= DMA_ds_PA_i(C_DBUS_WIDTH/2-1 downto 0) when Reg_RdMuxer_Lo(CINT_ADDR_DMA_DS_PAL)='1'
2567 
         else (Others=>'0');
2568 
 
2569 
   --  Host Address Start point
2570 
   DMA_ds_HA_o_Lo(C_DBUS_WIDTH-1 downto C_DBUS_WIDTH/2)
2571 
      <= DMA_ds_HA_i(C_DBUS_WIDTH-1 downto C_DBUS_WIDTH/2) when Reg_RdMuxer_Lo(CINT_ADDR_DMA_DS_HAH)='1'
2572 
         else (Others=>'0');
2573 
 
2574 
   DMA_ds_HA_o_Lo(C_DBUS_WIDTH/2-1 downto 0)
2575 
      <= DMA_ds_HA_i(C_DBUS_WIDTH/2-1 downto 0) when Reg_RdMuxer_Lo(CINT_ADDR_DMA_DS_HAL)='1'
2576 
         else (Others=>'0');
2577 
 
2578 
   --  Next Descriptor Address
2579 
   DMA_ds_BDA_o_Lo(C_DBUS_WIDTH-1 downto C_DBUS_WIDTH/2)
2580 
      <= DMA_ds_BDA_i(C_DBUS_WIDTH-1 downto C_DBUS_WIDTH/2) when Reg_RdMuxer_Lo(CINT_ADDR_DMA_DS_BDAH)='1'
2581 
         else (Others=>'0');
2582 
 
2583 
   DMA_ds_BDA_o_Lo(C_DBUS_WIDTH/2-1 downto 0)
2584 
      <= DMA_ds_BDA_i(C_DBUS_WIDTH/2-1 downto 0) when Reg_RdMuxer_Lo(CINT_ADDR_DMA_DS_BDAL)='1'
2585 
         else (Others=>'0');
2586 
 
2587 
   --  Length
2588 
   DMA_ds_Length_o_Lo(32-1 downto 0)
2589 
      <= DMA_ds_Length_i(32-1 downto 0) when Reg_RdMuxer_Lo(CINT_ADDR_DMA_DS_LENG)='1'
2590 
         else (Others=>'0');
2591 
 
2592 
   --  Control word
2593 
   DMA_ds_Control_o_Lo(32-1 downto 0)
2594 
      <= DMA_ds_Control_i(32-1 downto 0) when Reg_RdMuxer_Lo(CINT_ADDR_DMA_DS_CTRL)='1'
2595 
         else (Others=>'0');
2596 
 
2597 
   --  Status (Read only)
2598 
   DMA_ds_Status_o_Lo(32-1 downto 0)
2599 
      <= DMA_ds_Status_i(32-1 downto 0) when Reg_RdMuxer_Lo(CINT_ADDR_DMA_DS_STA)='1'
2600 
         else (Others=>'0');
2601 
 
2602 
   --  Tranferred bytes (Read only)
2603 
   DMA_ds_Transf_Bytes_o_Lo(32-1 downto 0)
2604 
      <= DMA_ds_Transf_Bytes_i(32-1 downto 0) when Reg_RdMuxer_Lo(CINT_ADDR_DS_TRANSF_BC)='1'
2605 
         else (Others=>'0');
2606 
 
2607 
 
2608 
   --------------------------------------------------------------------------
2609 
   -- CTL
2610 
   --------------------------------------------------------------------------
2611 
   ctl_td_o_Hi(32-1 downto 0)
2612 
      <= ctl_td_r(32-1 downto 0) when Reg_RdMuxer_Hi(CINT_ADDR_CTL_CLASS)='1'
2613 
         else (Others=>'0');
2614 
 
2615 
   ctl_td_o_Lo(32-1 downto 0)
2616 
      <= ctl_td_r(32-1 downto 0) when Reg_RdMuxer_Lo(CINT_ADDR_CTL_CLASS)='1'
2617 
         else (Others=>'0');
2618 
 
2619 
   --------------------------------------------------------------------------
2620 
   -- DLM
2621 
   --------------------------------------------------------------------------
2622 
   dlm_rd_o_Hi(32-1 downto 0)
2623 
      <= dlm_rd_r(32-1 downto 0) when Reg_RdMuxer_Hi(CINT_ADDR_DLM_CLASS)='1'
2624 
         else (Others=>'0');
2625 
 
2626 
   dlm_rd_o_Lo(32-1 downto 0)
2627 
      <= dlm_rd_r(32-1 downto 0) when Reg_RdMuxer_Lo(CINT_ADDR_DLM_CLASS)='1'
2628 
         else (Others=>'0');
2629 
 
2630 
 
2631 
   --------------------------------------------------------------------------
2632 
   -- System Interrupt Status
2633 
   --------------------------------------------------------------------------
2634 
   Sys_Int_Status_o_Hi(32-1 downto 0)
2635 
      <= (Sys_Int_Status_i(32-1 downto 0) and Sys_Int_Enable_i(32-1 downto 0)) when Reg_RdMuxer_Hi(CINT_ADDR_IRQ_STAT)='1'
2636 
         else (Others=>'0');
2637 
 
2638 
   Sys_Int_Enable_o_Hi(32-1 downto 0)
2639 
      <= Sys_Int_Enable_i(32-1 downto 0) when Reg_RdMuxer_Hi(CINT_ADDR_IRQ_EN)='1'
2640 
         else (Others=>'0');
2641 
 
2642 
   Sys_Int_Status_o_Lo(32-1 downto 0)
2643 
      <= (Sys_Int_Status_i(32-1 downto 0) and Sys_Int_Enable_i(32-1 downto 0)) when Reg_RdMuxer_Lo(CINT_ADDR_IRQ_STAT)='1'
2644 
         else (Others=>'0');
2645 
 
2646 
   Sys_Int_Enable_o_Lo(32-1 downto 0)
2647 
      <= Sys_Int_Enable_i(32-1 downto 0) when Reg_RdMuxer_Lo(CINT_ADDR_IRQ_EN)='1'
2648 
         else (Others=>'0');
2649 
 
2650 
 
2651 
   -- ----------------------------------------------------------------------------------
2652 
   -- ----------------------------------------------------------------------------------
2653 
   Gen_IG_Read:  if IMP_INT_GENERATOR generate
2654 
 
2655 
   --------------------------------------------------------------------------
2656 
   -- Interrupt Generator Latency
2657 
   --------------------------------------------------------------------------
2658 
   IG_Latency_o_Hi(32-1 downto 0)
2659 
      <= IG_Latency_i(32-1 downto 0) when Reg_RdMuxer_Hi(CINT_ADDR_IG_LATENCY)='1'
2660 
         else (Others=>'0');
2661 
 
2662 
   IG_Latency_o_Lo(32-1 downto 0)
2663 
      <= IG_Latency_i(32-1 downto 0) when Reg_RdMuxer_Lo(CINT_ADDR_IG_LATENCY)='1'
2664 
         else (Others=>'0');
2665 
   --------------------------------------------------------------------------
2666 
   -- Interrupt Generator Statistics
2667 
   --------------------------------------------------------------------------
2668 
   IG_Num_Assert_o_Hi(32-1 downto 0)
2669 
      <= IG_Num_Assert_i(32-1 downto 0) when Reg_RdMuxer_Hi(CINT_ADDR_IG_NUM_ASSERT)='1'
2670 
         else (Others=>'0');
2671 
 
2672 
   IG_Num_Deassert_o_Hi(32-1 downto 0)
2673 
      <= IG_Num_Deassert_i(32-1 downto 0) when Reg_RdMuxer_Hi(CINT_ADDR_IG_NUM_DEASSERT)='1'
2674 
         else (Others=>'0');
2675 
 
2676 
   IG_Num_Assert_o_Lo(32-1 downto 0)
2677 
      <= IG_Num_Assert_i(32-1 downto 0) when Reg_RdMuxer_Lo(CINT_ADDR_IG_NUM_ASSERT)='1'
2678 
         else (Others=>'0');
2679 
 
2680 
   IG_Num_Deassert_o_Lo(32-1 downto 0)
2681 
      <= IG_Num_Deassert_i(32-1 downto 0) when Reg_RdMuxer_Lo(CINT_ADDR_IG_NUM_DEASSERT)='1'
2682 
         else (Others=>'0');
2683 
 
2684 
   end generate;
2685 
 
2686 
 
2687 
   NotGen_IG_Read:  if not IMP_INT_GENERATOR generate
2688 
 
2689 
   IG_Latency_o_Hi(32-1 downto 0)      <= (Others=>'0');
2690 
   IG_Latency_o_Lo(32-1 downto 0)      <= (Others=>'0');
2691 
   IG_Num_Assert_o_Hi(32-1 downto 0)   <= (Others=>'0');
2692 
   IG_Num_Deassert_o_Hi(32-1 downto 0) <= (Others=>'0');
2693 
   IG_Num_Assert_o_Lo(32-1 downto 0)   <= (Others=>'0');
2694 
   IG_Num_Deassert_o_Lo(32-1 downto 0) <= (Others=>'0');
2695 
 
2696 
   end generate;
2697 
 
2698 
 
2699 
   --------------------------------------------------------------------------
2700 
   --  System Error
2701 
   --------------------------------------------------------------------------
2702 
   Synch_Sys_Error_i:
2703 
   process ( trn_clk, trn_lnk_up_n)
2704 
   begin
2705 
     if trn_lnk_up_n = '1' then
2706 
        Sys_Error_i                            <= (OTHERS => '0');
2707 
        eb_FIFO_OverWritten                    <= '0';
2708 
     elsif trn_clk'event and trn_clk = '1' then
2709 
        Sys_Error_i(CINT_BIT_TX_TOUT_IN_SER)   <= Tx_TimeOut;
2710 
        Sys_Error_i(CINT_BIT_EB_TOUT_IN_SER)   <= Tx_eb_TimeOut;
2711 
        Sys_Error_i(CINT_BIT_EB_OVERWRITTEN)   <= eb_FIFO_OverWritten;
2712 
        --  !!!!!!!!!!!!!! capture eb_FIFO overflow, temp cleared by MRd_Channel_Rst_i
2713 
        eb_FIFO_OverWritten      <= (not MRd_Channel_Rst_i) and (eb_FIFO_ow or eb_FIFO_OverWritten);
2714 
     end if;
2715 
   end process;
2716 
 
2717 
 
2718 
   --------------------------------------------------------------------------
2719 
   --  General Status and Control
2720 
   --------------------------------------------------------------------------
2721 
   Synch_General_Status_i:
2722 
   process ( trn_clk, trn_lnk_up_n)
2723 
   begin
2724 
     if trn_lnk_up_n = '1' then
2725 
       General_Status_i  <= (OTHERS => '0');
2726 
     elsif trn_clk'event and trn_clk = '1' then
2727 
       General_Status_i(32-1 downto 32-16)
2728 
                       <= cfg_dcommand;
2729 
       General_Status_i(CINT_BIT_LWIDTH_IN_GSR_TOP downto CINT_BIT_LWIDTH_IN_GSR_BOT)
2730 
                       <= pcie_link_width;
2731 
       General_Status_i(CINT_BIT_ICAP_BUSY_IN_GSR)
2732 
                       <= icap_Busy;
2733 3 weng_ziti 
--       General_Status_i(CINT_BIT_DG_AVAIL_IN_GSR)
2734 
--                       <= DG_is_Available;
2735 
--       General_Status_i(CINT_BIT_LINK_ACT_IN_GSR+1 downto CINT_BIT_LINK_ACT_IN_GSR)
2736 
--                       <= protocol_link_act;
2737 2 weng_ziti 
 
2738 
--       General_Status_i(8) <= CTL_read_counter(6-1);   ---- DEBUG !!!
2739 
     end if;
2740 
   end process;
2741 
 
2742 
 
2743 
 
2744 
   Sys_Error_o_Hi(32-1 downto 0)
2745 
      <= Sys_Error_i(32-1 downto 0) when Reg_RdMuxer_Hi(CINT_ADDR_ERROR)='1'
2746 
         else (Others=>'0');
2747 
 
2748 
   General_Status_o_Hi(32-1 downto 0)
2749 
      <= General_Status_i(32-1 downto 0) when Reg_RdMuxer_Hi(CINT_ADDR_STATUS)='1'
2750 
         else (Others=>'0');
2751 
 
2752 
   General_Control_o_Hi(32-1 downto 0)
2753 
      <= General_Control_i(32-1 downto 0) when Reg_RdMuxer_Hi(CINT_ADDR_CONTROL)='1'
2754 
         else (Others=>'0');
2755 
 
2756 
   Sys_Error_o_Lo(32-1 downto 0)
2757 
      <= Sys_Error_i(32-1 downto 0) when Reg_RdMuxer_Lo(CINT_ADDR_ERROR)='1'
2758 
         else (Others=>'0');
2759 
 
2760 
   General_Status_o_Lo(32-1 downto 0)
2761 
      <= General_Status_i(32-1 downto 0) when Reg_RdMuxer_Lo(CINT_ADDR_STATUS)='1'
2762 
         else (Others=>'0');
2763 
 
2764 
   General_Control_o_Lo(32-1 downto 0)
2765 
      <= General_Control_i(32-1 downto 0) when Reg_RdMuxer_Lo(CINT_ADDR_CONTROL)='1'
2766 
         else (Others=>'0');
2767 
 
2768 
 
2769 
   --------------------------------------------------------------------------
2770 
   -- ICAP
2771 
   --------------------------------------------------------------------------
2772 
   icap_O_o_Hi(32-1 downto 0)
2773 
      <= icap_O(32-1 downto 0) when Reg_RdMuxer_Hi(CINT_ADDR_ICAP)='1'
2774 
         else (Others=>'0');
2775 
 
2776 
   icap_O_o_Lo(32-1 downto 0)
2777 
      <= icap_O(32-1 downto 0) when Reg_RdMuxer_Lo(CINT_ADDR_ICAP)='1'
2778 
         else (Others=>'0');
2779 
 
2780 
   --------------------------------------------------------------------------
2781 
   -- FIFO Statuses (read only)
2782 
   --------------------------------------------------------------------------
2783 
   eb_FIFO_Status_o_Hi(32-1 downto 0)
2784 
      <= eb_FIFO_Status_r1(32-1 downto 0) when Reg_RdMuxer_Hi(CINT_ADDR_EB_STACON)='1'
2785 
         else (Others=>'0');
2786 
 
2787 
   eb_FIFO_Status_o_Lo(32-1 downto 0)
2788 
      <= eb_FIFO_Status_r1(32-1 downto 0) when Reg_RdMuxer_Lo(CINT_ADDR_EB_STACON)='1'
2789 
         else (Others=>'0');
2790 
 
2791 3 weng_ziti 
--   --------------------------------------------------------------------------
2792 
--   -- Optical Link Status
2793 
--   --------------------------------------------------------------------------
2794 
--   Opto_Link_Status_o_Hi(32-1 downto 0)
2795 
--      <= Opto_Link_Status_i(32-1 downto 0) when Reg_RdMuxer_Hi(CINT_ADDR_PROTOCOL_STACON)='1'
2796 
--         else (Others=>'0');
2797 
--
2798 
--   Opto_link_Status_o_Lo(32-1 downto 0)
2799 
--      <= Opto_Link_Status_i(32-1 downto 0) when Reg_RdMuxer_Lo(CINT_ADDR_PROTOCOL_STACON)='1'
2800 
--         else (Others=>'0');
2801 
--
2802 
--   --------------------------------------------------------------------------
2803 
--   -- Class CTL status
2804 
--   --------------------------------------------------------------------------
2805 
--   class_CTL_Status_o_Hi(32-1 downto 0)
2806 
--      <= class_CTL_Status_i(32-1 downto 0) when Reg_RdMuxer_Hi(CINT_ADDR_TC_STATUS)='1'
2807 
--         else (Others=>'0');
2808 
--
2809 
--   class_CTL_Status_o_Lo(32-1 downto 0)
2810 
--      <= class_CTL_Status_i(32-1 downto 0) when Reg_RdMuxer_Lo(CINT_ADDR_TC_STATUS)='1'
2811 
--         else (Others=>'0');
2812 
--
2813 
--   --------------------------------------------------------------------------
2814 
--   -- Data generator Status
2815 
--   --------------------------------------------------------------------------
2816 
--   DG_Status_o_Hi(32-1 downto 0)
2817 
--      <= DG_Status_i(32-1 downto 0) when Reg_RdMuxer_Hi(CINT_ADDR_DG_CTRL)='1'
2818 
--         else (Others=>'0');
2819 
--
2820 
--   DG_Status_o_Lo(32-1 downto 0)
2821 
--      <= DG_Status_i(32-1 downto 0) when Reg_RdMuxer_Lo(CINT_ADDR_DG_CTRL)='1'
2822 
--         else (Others=>'0');
2823 2 weng_ziti 
 
2824 
   --------------------------------------------------------------------------
2825 
   -- Hardware version
2826 
   --------------------------------------------------------------------------
2827 
   HW_Version_o_Hi(32-1 downto 0)
2828 
      <= C_DESIGN_ID(32-1 downto 0) when Reg_RdMuxer_Hi(CINT_ADDR_VERSION)='1'
2829 
         else (Others=>'0');
2830 
 
2831 
   HW_Version_o_Lo(32-1 downto 0)
2832 
      <= C_DESIGN_ID(32-1 downto 0) when Reg_RdMuxer_Lo(CINT_ADDR_VERSION)='1'
2833 
         else (Others=>'0');
2834 
 
2835 
-----------------------------------------------------
2836 
-- Sequential : Regs_RdQout_i
2837 
--
2838 
   Synch_Regs_RdQout:
2839 
   process ( trn_clk, trn_lnk_up_n)
2840 
   begin
2841 
      if trn_lnk_up_n = '1' then
2842 
         Regs_RdQout_i <= (OTHERS =>'0');
2843 
 
2844 
      elsif trn_clk'event and trn_clk = '1' then
2845 
 
2846 
         Regs_RdQout_i(64-1 downto 32)        <=
2847 
                                  HW_Version_o_Hi     (32-1 downto 0)
2848 
 
2849 
                              or  Sys_Error_o_Hi      (32-1 downto 0)
2850 
                              or  General_Status_o_Hi (32-1 downto 0)
2851 
                              or  General_Control_o_Hi(32-1 downto 0)
2852 
 
2853 
                              or  Sys_Int_Status_o_Hi (32-1 downto 0)
2854 
                              or  Sys_Int_Enable_o_Hi (32-1 downto 0)
2855 
 
2856 
--                              or  DMA_us_PA_o_Hi      (C_DBUS_WIDTH-1 downto 32)
2857 
                              or  DMA_us_PA_o_Hi      (32-1   downto          0)
2858 
                              or  DMA_us_HA_o_Hi      (C_DBUS_WIDTH-1 downto 32)
2859 
                              or  DMA_us_HA_o_Hi      (32-1   downto          0)
2860 
                              or  DMA_us_BDA_o_Hi     (C_DBUS_WIDTH-1 downto 32)
2861 
                              or  DMA_us_BDA_o_Hi     (32-1   downto          0)
2862 
                              or  DMA_us_Length_o_Hi  (32-1 downto 0)
2863 
                              or  DMA_us_Control_o_Hi (32-1 downto 0)
2864 
                              or  DMA_us_Status_o_Hi  (32-1 downto 0)
2865 
                              or  DMA_us_Transf_Bytes_o_Hi  (32-1 downto 0)
2866 
 
2867 
--                              or  DMA_ds_PA_o_Hi      (C_DBUS_WIDTH-1 downto 32)
2868 
                              or  DMA_ds_PA_o_Hi      (32-1   downto          0)
2869 
                              or  DMA_ds_HA_o_Hi      (C_DBUS_WIDTH-1 downto 32)
2870 
                              or  DMA_ds_HA_o_Hi      (32-1   downto          0)
2871 
                              or  DMA_ds_BDA_o_Hi     (C_DBUS_WIDTH-1 downto 32)
2872 
                              or  DMA_ds_BDA_o_Hi     (32-1   downto          0)
2873 
                              or  DMA_ds_Length_o_Hi  (32-1 downto 0)
2874 
                              or  DMA_ds_Control_o_Hi (32-1 downto 0)
2875 
                              or  DMA_ds_Status_o_Hi  (32-1 downto 0)
2876 
                              or  DMA_ds_Transf_Bytes_o_Hi  (32-1 downto 0)
2877 
 
2878 
                              or  IG_Latency_o_Hi     (32-1 downto 0)
2879 
                              or  IG_Num_Assert_o_Hi  (32-1 downto 0)
2880 
                              or  IG_Num_Deassert_o_Hi(32-1 downto 0)
2881 
 
2882 3 weng_ziti 
--                              or  DG_Status_o_Hi      (32-1 downto 0)
2883 
--                              or  class_CTL_Status_o_Hi  (32-1 downto 0)
2884 2 weng_ziti 
 
2885 
--                              or  icap_O_o_Hi         (32-1 downto 0)
2886 3 weng_ziti 
--                              or  Opto_Link_Status_o_Hi (32-1 downto 0)
2887 2 weng_ziti 
                              or  eb_FIFO_Status_o_Hi (32-1 downto 0)
2888 3 weng_ziti 
--                                                                              or  dlm_rd_o_Hi
2889 
--                                                                              or  ctl_td_o_Hi
2890 2 weng_ziti 
                              ;
2891 
 
2892 
 
2893 
         Regs_RdQout_i(32-1 downto 0)        <=
2894 
                                  HW_Version_o_Lo     (32-1 downto 0)
2895 
 
2896 
                              or  Sys_Error_o_Lo      (32-1 downto 0)
2897 
                              or  General_Status_o_Lo (32-1 downto 0)
2898 
                              or  General_Control_o_Lo(32-1 downto 0)
2899 
 
2900 
                              or  Sys_Int_Status_o_Lo (32-1 downto 0)
2901 
                              or  Sys_Int_Enable_o_Lo (32-1 downto 0)
2902 
 
2903 
--                              or  DMA_us_PA_o_Lo      (C_DBUS_WIDTH-1 downto 32)
2904 
                              or  DMA_us_PA_o_Lo      (32-1   downto          0)
2905 
                              or  DMA_us_HA_o_Lo      (C_DBUS_WIDTH-1 downto 32)
2906 
                              or  DMA_us_HA_o_Lo      (32-1   downto          0)
2907 
                              or  DMA_us_BDA_o_Lo     (C_DBUS_WIDTH-1 downto 32)
2908 
                              or  DMA_us_BDA_o_Lo     (32-1   downto          0)
2909 
                              or  DMA_us_Length_o_Lo  (32-1 downto 0)
2910 
                              or  DMA_us_Control_o_Lo (32-1 downto 0)
2911 
                              or  DMA_us_Status_o_Lo  (32-1 downto 0)
2912 
                              or  DMA_us_Transf_Bytes_o_Lo  (32-1 downto 0)
2913 
 
2914 
--                              or  DMA_ds_PA_o_Lo      (C_DBUS_WIDTH-1 downto 32)
2915 
                              or  DMA_ds_PA_o_Lo      (32-1   downto          0)
2916 
                              or  DMA_ds_HA_o_Lo      (C_DBUS_WIDTH-1 downto 32)
2917 
                              or  DMA_ds_HA_o_Lo      (32-1   downto          0)
2918 
                              or  DMA_ds_BDA_o_Lo     (C_DBUS_WIDTH-1 downto 32)
2919 
                              or  DMA_ds_BDA_o_Lo     (32-1   downto          0)
2920 
                              or  DMA_ds_Length_o_Lo  (32-1 downto 0)
2921 
                              or  DMA_ds_Control_o_Lo (32-1 downto 0)
2922 
                              or  DMA_ds_Status_o_Lo  (32-1 downto 0)
2923 
                              or  DMA_ds_Transf_Bytes_o_Lo  (32-1 downto 0)
2924 
 
2925 
                              or  IG_Latency_o_Lo     (32-1 downto 0)
2926 
                              or  IG_Num_Assert_o_Lo  (32-1 downto 0)
2927 
                              or  IG_Num_Deassert_o_Lo(32-1 downto 0)
2928 
 
2929 3 weng_ziti 
--                              or  DG_Status_o_Lo      (32-1 downto 0)
2930 
--                              or  class_CTL_Status_o_Lo  (32-1 downto 0)
2931 2 weng_ziti 
 
2932 
--                              or  icap_O_o_Lo(32-1 downto 0)
2933 3 weng_ziti 
--                              or  Opto_Link_Status_o_Lo (32-1 downto 0)
2934 2 weng_ziti 
                              or  eb_FIFO_Status_o_Lo (32-1 downto 0)
2935 3 weng_ziti 
--                                                                              or  dlm_rd_o_Lo
2936 
--                                                                              or  ctl_td_o_Lo
2937 2 weng_ziti 
                              ;
2938 
 
2939 
      end if;
2940 
   end process;
2941 
 
2942 
 
2943 
end Behavioral;

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