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[/] [pcie_sg_dma/] [trunk/] [rtl/] [bram_Control.vhd] - Blame information for rev 8

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Line No. Rev Author Line
1 2 weng_ziti 
----------------------------------------------------------------------------------
2 
-- Company:  ziti, Uni. HD
3 
-- Engineer:  wgao
4 
--
5 
-- Create Date:    12:29:46 15 Apr 2008
6 
-- Design Name:
7 
-- Module Name:    bram_Control - Behavioral
8 
-- Project Name:
9 
-- Target Devices:
10 
-- Tool versions:
11 
-- Description:
12 
--
13 
-- Dependencies:
14 
--
15 
-- Revision 1.00 - first release.  16.04.2008
16 
--
17 
-- Additional Comments:
18 
--
19 
----------------------------------------------------------------------------------
20 
library IEEE;
21 
use IEEE.STD_LOGIC_1164.ALL;
22 
use IEEE.STD_LOGIC_ARITH.ALL;
23 
use IEEE.STD_LOGIC_UNSIGNED.ALL;
24 
 
25 
library work;
26 
use work.abb64Package.all;
27 
 
28 
---- Uncomment the following library declaration if instantiating
29 
---- any Xilinx primitives in this code.
30 
--library UNISIM;
31 
--use UNISIM.VComponents.all;
32 
 
33 
entity bram_Control is
34 
    Generic (
35 
             C_ASYNFIFO_WIDTH  :  integer  :=  72 ;
36 
             P_SIMULATION      :  boolean  :=  TRUE
37 
            );
38 
    Port (
39 
 
40 
 
41 
           -- DMA interface
42 
           DDR_wr_sof               : IN    std_logic;
43 
           DDR_wr_eof               : IN    std_logic;
44 
           DDR_wr_v                 : IN    std_logic;
45 
           DDR_wr_FA                : IN    std_logic;
46 
           DDR_wr_Shift             : IN    std_logic;
47 
           DDR_wr_Mask              : IN    std_logic_vector(2-1 downto 0);
48 
           DDR_wr_din               : IN    std_logic_vector(C_DBUS_WIDTH-1 downto 0);
49 
           DDR_wr_full              : OUT   std_logic;
50 
 
51 
           DDR_rdc_sof              : IN    std_logic;
52 
           DDR_rdc_eof              : IN    std_logic;
53 
           DDR_rdc_v                : IN    std_logic;
54 
           DDR_rdc_FA               : IN    std_logic;
55 
           DDR_rdc_Shift            : IN    std_logic;
56 
           DDR_rdc_din              : IN    std_logic_vector(C_DBUS_WIDTH-1 downto 0);
57 
           DDR_rdc_full             : OUT   std_logic;
58 
 
59 
--           DDR_rdD_sof              : OUT   std_logic;
60 
--           DDR_rdD_eof              : OUT   std_logic;
61 
--           DDR_rdDout_V             : OUT   std_logic;
62 
--           DDR_rdDout               : OUT   std_logic_vector(C_DBUS_WIDTH-1 downto 0);
63 
 
64 
           -- DDR payload FIFO Read Port
65 
           DDR_FIFO_RdEn            : IN    std_logic;
66 
           DDR_FIFO_Empty           : OUT   std_logic;
67 
           DDR_FIFO_RdQout          : OUT   std_logic_vector(C_DBUS_WIDTH-1 downto 0);
68 
 
69 
           -- Common interface
70 
           DBG_dma_start            : IN    std_logic;
71 
           DDR_Ready                : OUT   std_logic;
72 
           DDR_blinker              : OUT   std_logic;
73 
           Sim_Zeichen              : OUT   std_logic;
74 
 
75 
           mem_clk                  : IN    std_logic;
76 
           trn_clk                  : IN    std_logic;
77 
           trn_reset_n              : IN    std_logic
78 
          );
79 
end entity bram_Control;
80 
 
81 
 
82 
architecture Behavioral of bram_Control is
83 
 
84 
  -- ----------------------------------------------------------------------------
85 
  --
86 
  -- ----------------------------------------------------------------------------
87 
  COMPONENT DDR_ClkGen
88 
    PORT(
89 
         ddr_Clock              : OUT   std_logic;
90 
         ddr_Clock_n            : OUT   std_logic;
91 
         ddr_Clock90            : OUT   std_logic;
92 
         ddr_Clock90_n          : OUT   std_logic;
93 
         Clk_ddr_rddata         : OUT   std_logic;
94 
         Clk_ddr_rddata_n       : OUT   std_logic;
95 
 
96 
         ddr_DCM_locked         : OUT   std_logic;
97 
 
98 
         clk_in                 : IN    std_logic;
99 
         trn_reset_n            : IN    std_logic
100 
        );
101 
  END COMPONENT;
102 
 
103 
 
104 
  -- ----------------------------------------------------------------------------
105 
  --
106 
  -- ----------------------------------------------------------------------------
107 
 
108 
  COMPONENT asyn_rw_FIFO72
109 
--    GENERIC (
110 
--             OUTPUT_REGISTERED  : BOOLEAN
111 
--            );
112 
    PORT(
113 
        wClk                    : IN     std_logic;
114 
        wEn                     : IN     std_logic;
115 
        Din                     : IN     std_logic_vector(C_ASYNFIFO_WIDTH-1 downto 0);
116 
        aFull                   : OUT    std_logic;
117 
        Full                    : OUT    std_logic;
118 
 
119 
        rClk                    : IN     std_logic;
120 
        rEn                     : IN     std_logic;
121 
        Qout                    : OUT    std_logic_vector(C_ASYNFIFO_WIDTH-1 downto 0);
122 
        aEmpty                  : OUT    std_logic;
123 
        Empty                   : OUT    std_logic;
124 
 
125 
        Rst                     : IN     std_logic
126 
        );
127 
  END COMPONENT;
128 
 
129 
 
130 
  component prim_FIFO_plain
131 
      port (
132 
      wr_clk   : IN  std_logic;
133 
      wr_en    : IN  std_logic;
134 
      din      : IN  std_logic_VECTOR(C_ASYNFIFO_WIDTH-1 downto 0);
135 
      full     : OUT std_logic;
136 
      prog_full: OUT std_logic;
137 
      rd_clk   : IN  std_logic;
138 
      rd_en    : IN  std_logic;
139 
      dout     : OUT std_logic_VECTOR(C_ASYNFIFO_WIDTH-1 downto 0);
140 
      empty    : OUT std_logic;
141 
      rst      : IN  std_logic
142 
      );
143 
  end component;
144 
 
145 
--  component fifo_512x36_v4_2
146 
--    port (
147 
--    wr_clk      : IN  std_logic;
148 
--    wr_en       : IN  std_logic;
149 
--    din         : IN  std_logic_VECTOR(35 downto 0);
150 
--    prog_full   : OUT std_logic;
151 
--    full        : OUT std_logic;
152 
--
153 
--    rd_clk      : IN  std_logic;
154 
--    rd_en       : IN  std_logic;
155 
--    dout        : OUT std_logic_VECTOR(35 downto 0);
156 
--    prog_empty  : OUT std_logic;
157 
--    empty       : OUT std_logic;
158 
--
159 
--    rst         : IN  std_logic
160 
--    );
161 
--  end component;
162 
 
163 
  component fifo_512x72_v4_4
164 
    port (
165 
    wr_clk      : IN  std_logic;
166 
    wr_en       : IN  std_logic;
167 
    din         : IN  std_logic_VECTOR(C_ASYNFIFO_WIDTH-1 downto 0);
168 
    prog_full   : OUT std_logic;
169 
    full        : OUT std_logic;
170 
 
171 
    rd_clk      : IN  std_logic;
172 
    rd_en       : IN  std_logic;
173 
    dout        : OUT std_logic_VECTOR(C_ASYNFIFO_WIDTH-1 downto 0);
174 
--    prog_empty  : OUT std_logic;
175 
    empty       : OUT std_logic;
176 
 
177 
    rst         : IN  std_logic
178 
    );
179 
  end component;
180 
 
181 
 
182 
  ---- Dual-port block RAM for packets
183 
  ---    Core output registered
184 
  --
185 
--  component v5bram4096x32
186 
--    port (
187 
--      clka           : IN  std_logic;
188 
--      addra          : IN  std_logic_vector(C_PRAM_AWIDTH-1 downto 0);
189 
--      wea            : IN  std_logic_vector(0 downto 0);
190 
--      dina           : IN  std_logic_vector(C_DBUS_WIDTH-1 downto 0);
191 
--      douta          : OUT std_logic_vector(C_DBUS_WIDTH-1 downto 0);
192 
--
193 
--      clkb           : IN  std_logic;
194 
--      addrb          : IN  std_logic_vector(C_PRAM_AWIDTH-1 downto 0);
195 
--      web            : IN  std_logic_vector(0 downto 0);
196 
--      dinb           : IN  std_logic_vector(C_DBUS_WIDTH-1 downto 0);
197 
--      doutb          : OUT std_logic_vector(C_DBUS_WIDTH-1 downto 0)
198 
--    );
199 
--  end component;
200 
 
201 
  component bram4096x64
202 
    port (
203 
      clka           : IN  std_logic;
204 
      addra          : IN  std_logic_vector(C_PRAM_AWIDTH-1 downto 0);
205 
      wea            : IN  std_logic_vector(7 downto 0);
206 
      dina           : IN  std_logic_vector(C_DBUS_WIDTH-1 downto 0);
207 
      douta          : OUT std_logic_vector(C_DBUS_WIDTH-1 downto 0);
208 
 
209 
      clkb           : IN  std_logic;
210 
      addrb          : IN  std_logic_vector(C_PRAM_AWIDTH-1 downto 0);
211 
      web            : IN  std_logic_vector(7 downto 0);
212 
      dinb           : IN  std_logic_vector(C_DBUS_WIDTH-1 downto 0);
213 
      doutb          : OUT std_logic_vector(C_DBUS_WIDTH-1 downto 0)
214 
    );
215 
  end component;
216 
 
217 
  -- Blinking  -_-_-_-_-_-_-_-_-_-_-_-_-_-_-
218 
  COMPONENT DDR_Blink
219 
    PORT(
220 
           DDR_Blinker              : OUT   std_logic;
221 
 
222 
           DBG_dma_start            : IN    std_logic;
223 
           DBG_bram_wea             : IN    std_logic_vector(7 downto 0);
224 
           DBG_bram_addra           : IN    std_logic_vector(C_PRAM_AWIDTH-1 downto 0);
225 
 
226 
           DDR_Write                : IN    std_logic;
227 
           DDR_Read                 : IN    std_logic;
228 
           DDR_Both                 : IN    std_logic;
229 
 
230 
           ddr_Clock                : IN    std_logic;
231 
           DDr_Rst_n                : IN    std_logic
232 
          );
233 
  END COMPONENT;
234 
 
235 
  -- ---------------------------------------------------------------------
236 
  signal  ddr_DCM_locked        :  std_logic;
237 
  --  -- ---------------------------------------------------------------------
238 
  signal  Rst_i                 :  std_logic;
239 
  --  -- ---------------------------------------------------------------------
240 
  signal  DDR_Ready_i           :  std_logic;
241 
  --  -- ---------------------------------------------------------------------
242 
  signal  ddr_Clock             :  std_logic;
243 
  signal  ddr_Clock_n           :  std_logic;
244 
  signal  ddr_Clock90           :  std_logic;
245 
  signal  ddr_Clock90_n         :  std_logic;
246 
 
247 
  signal  Clk_ddr_rddata        :  std_logic;
248 
  signal  Clk_ddr_rddata_n      :  std_logic;
249 
 
250 
  -- -- --  Write Pipe Channel
251 
  signal  wpipe_wEn             :  std_logic;
252 
  signal  wpipe_Din             :  std_logic_vector(C_ASYNFIFO_WIDTH-1 downto 0);
253 
  signal  wpipe_aFull           :  std_logic;
254 
  signal  wpipe_Full            :  std_logic;
255 
  --  Earlier calculate for better timing
256 
  signal  DDR_wr_Cross_Row      :  std_logic;
257 
  signal  DDR_wr_din_r1         :  std_logic_vector(C_DBUS_WIDTH-1 downto 0);
258 
  signal  DDR_write_ALC         :  std_logic_vector(11-1 downto 0);
259 
 
260 
  signal  wpipe_rEn             :  std_logic;
261 
  signal  wpipe_Qout            :  std_logic_vector(C_ASYNFIFO_WIDTH-1 downto 0);
262 
--  signal  wpipe_aEmpty          :  std_logic;
263 
  signal  wpipe_Empty           :  std_logic;
264 
  signal  wpipe_Qout_latch      :  std_logic_vector(C_ASYNFIFO_WIDTH-1 downto 0);
265 
 
266 
  -- -- --  Read Pipe Command Channel
267 
  signal  rpipec_wEn            :  std_logic;
268 
  signal  rpipec_Din            :  std_logic_vector(C_ASYNFIFO_WIDTH-1 downto 0);
269 
  signal  rpipec_Din_r          :  std_logic_vector(C_ASYNFIFO_WIDTH-1 downto 0);
270 
--  signal  rpipec_aFull          :  std_logic;
271 
--  signal  rpipec_Full           :  std_logic;
272 
  --  Earlier calculate for better timing
273 
  signal  DDR_rd_Cross_Row      :  std_logic;
274 
  signal  DDR_rdc_din_r1        :  std_logic_vector(C_DBUS_WIDTH-1 downto 0);
275 
  signal  DDR_read_ALC          :  std_logic_vector(11-1 downto 0);
276 
 
277 
--  signal  rpipec_rEn            :  std_logic;
278 
--  signal  rpipec_Qout           :  std_logic_vector(C_ASYNFIFO_WIDTH-1 downto 0);
279 
----  signal  rpipec_aEmpty         :  std_logic;
280 
--  signal  rpipec_Empty          :  std_logic;
281 
 
282 
  -- -- --  Read Pipe Data Channel
283 
  signal  rpiped_wEn            :  std_logic;
284 
  signal  rpiped_Din            :  std_logic_vector(C_ASYNFIFO_WIDTH-1 downto 0);
285 
  signal  rpiped_aFull          :  std_logic;
286 
  signal  rpiped_Full           :  std_logic;
287 
 
288 
--  signal  rpiped_rEn            :  std_logic;
289 
  signal  rpiped_Qout           :  std_logic_vector(C_ASYNFIFO_WIDTH-1 downto 0);
290 
--  signal  rpiped_aEmpty         :  std_logic;
291 
--  signal  rpiped_Empty          :  std_logic;
292 
 
293 
 
294 
  --   write State machine
295 
  type bram_wrStates is          ( wrST_bram_RESET
296 
                                 , wrST_bram_IDLE
297 
--                                 , wrST_bram_Address
298 
                                 , wrST_bram_1st_Data
299 
                                 , wrST_bram_1st_Data_b2b
300 
                                 , wrST_bram_more_Data
301 
                                 , wrST_bram_last_DW
302 
                                 );
303 
 
304 
  -- State variables
305 
  signal pseudo_DDR_wr_State     : bram_wrStates;
306 
 
307 
  --       Block RAM
308 
  signal   pRAM_weA              : std_logic_vector(7 downto 0);
309 
  signal   pRAM_addrA            : std_logic_vector(C_PRAM_AWIDTH-1 downto 0);
310 
  signal   pRAM_dinA             : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
311 
  signal   pRAM_doutA            : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
312 
 
313 
  signal   pRAM_weB              : std_logic_vector(7 downto 0);
314 
  signal   pRAM_addrB            : std_logic_vector(C_PRAM_AWIDTH-1 downto 0);
315 
  signal   pRAM_dinB             : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
316 
  signal   pRAM_doutB            : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
317 
  signal   pRAM_doutB_r1         : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
318 
  signal   pRAM_doutB_shifted    : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
319 
 
320 
  signal   wpipe_qout_lo32b      : std_logic_vector(33-1 downto 0);
321 
  signal   wpipe_QW_Aligned      : std_logic;
322 
  signal   pRAM_AddrA_Inc        : std_logic;
323 
  signal   wpipe_read_valid      : std_logic;
324 
 
325 
 
326 
  --   read State machine
327 
  type bram_rdStates is          ( rdST_bram_RESET
328 
                                 , rdST_bram_IDLE
329 
--                                 , rdST_bram_b4_LA
330 
                                 , rdST_bram_LA
331 
--                                 , rdST_bram_b4_Length
332 
--                                 , rdST_bram_Length
333 
--                                 , rdST_bram_b4_Address
334 
--                                 , rdST_bram_Address
335 
                                 , rdST_bram_Data
336 
--                                 , rdST_bram_Data_shift
337 
                                 );
338 
 
339 
  -- State variables
340 
  signal pseudo_DDR_rd_State     : bram_rdStates;
341 
 
342 
  signal rpiped_rd_counter       : std_logic_vector(10-1 downto 0);
343 
  signal rpiped_wEn_b3           : std_logic;
344 
  signal rpiped_wEn_b2           : std_logic;
345 
  signal rpiped_wEn_b1           : std_logic;
346 
  signal rpiped_wr_EOF           : std_logic;
347 
  signal rpiped_wr_skew          : std_logic;
348 
  signal rpiped_wr_postpone      : std_logic;
349 
 
350 
 
351 
begin
352 
 
353 
 
354 
  Rst_i              <=  not trn_reset_n;
355 
  DDR_Ready          <=  DDR_Ready_i;
356 
 
357 
  pRAM_doutB_shifted  <= pRAM_doutB_r1(32-1 downto 0) & pRAM_doutB(64-1 downto 32);
358 
 
359 
  --  Delay
360 
  Syn_Shifting_pRAM_doutB:
361 
  process ( trn_clk)
362 
  begin
363 
     if trn_clk'event and trn_clk = '1' then
364 
        pRAM_doutB_r1 <= pRAM_doutB;
365 
     end if;
366 
  end process;
367 
 
368 
  -- -----------------------------------------------
369 
  --
370 
  Syn_DDR_CKE:
371 
  process (trn_clk, Rst_i)
372 
  begin
373 
    if Rst_i = '1' then
374 
       DDR_Ready_i       <=  '0';
375 
    elsif trn_clk'event and trn_clk = '1' then
376 
       DDR_Ready_i       <=  '1';   -- ddr_DCM_locked;
377 
    end if;
378 
  end process;
379 
 
380 
  -- ----------------------------------------------------------------------------
381 
  --
382 
  -- ----------------------------------------------------------------------------
383 
--  DDR_Clock_Generator:
384 
--  DDR_ClkGen
385 
--  PORT MAP(
386 
--           ddr_Clock            =>  ddr_Clock             , -- OUT   std_logic;
387 
--           ddr_Clock_n          =>  ddr_Clock_n           , -- OUT   std_logic;
388 
--           ddr_Clock90          =>  ddr_Clock90           , -- OUT   std_logic;
389 
--           ddr_Clock90_n        =>  ddr_Clock90_n         , -- OUT   std_logic;
390 
--           Clk_ddr_rddata       =>  Clk_ddr_rddata        , -- OUT   std_logic;
391 
--           Clk_ddr_rddata_n     =>  Clk_ddr_rddata_n      , -- OUT   std_logic;
392 
--           ddr_DCM_locked       =>  ddr_DCM_locked        , -- OUT   std_logic;
393 
--
394 
--           clk_in               =>  mem_clk               , -- IN    std_logic;
395 
--           trn_reset_n          =>  trn_reset_n             -- IN    std_logic
396 
--          );
397 
 
398 
 
399 
  -- ----------------------------------------------------------------------------
400 
  --
401 
  -- ----------------------------------------------------------------------------
402 
--  DDR_pipe_write_fifo:
403 
--  asyn_rw_FIFO
404 
--  GENERIC MAP (
405 
--               OUTPUT_REGISTERED    => TRUE
406 
--              )
407 
--  PORT MAP(
408 
--           wClk          =>  trn_clk         ,
409 
--           wEn           =>  wpipe_wEn       ,
410 
--           Din           =>  wpipe_Din       ,
411 
--           aFull         =>  wpipe_aFull     ,
412 
--           Full          =>  wpipe_Full      ,
413 
--
414 
--           rClk          =>  ddr_Clock       ,  -- ddr_Clock_n     ,
415 
--           rEn           =>  wpipe_rEn       ,
416 
--           Qout          =>  wpipe_Qout      ,
417 
--           aEmpty        =>  wpipe_aEmpty    ,
418 
--           Empty         =>  wpipe_Empty     ,
419 
--
420 
--           Rst           =>  Rst_i
421 
--          );
422 
 
423 
--  DDR_pipe_write_fifo:
424 
--  asyn_rw_FIFO72
425 
--  PORT MAP(
426 
--           wClk          =>  trn_clk       ,
427 
--           wEn           =>  wpipe_wEn     ,
428 
--           Din           =>  wpipe_Din     ,
429 
--           aFull         =>  wpipe_aFull   ,
430 
--           Full          =>  open          ,
431 
--
432 
--           rClk          =>  ddr_Clock     ,
433 
--           rEn           =>  wpipe_rEn     ,
434 
--           Qout          =>  wpipe_Qout    ,
435 
--           aEmpty        =>  open          ,
436 
--           Empty         =>  wpipe_Empty   ,
437 
--
438 
--           Rst           =>  Rst_i
439 
--          );
440 
 
441 
  DDR_pipe_write_fifo:
442 
  prim_FIFO_plain
443 
  PORT MAP(
444 
    wr_clk       =>  trn_clk      , -- IN  std_logic;
445 
    wr_en        =>  wpipe_wEn    , -- IN  std_logic;
446 
    din          =>  wpipe_Din    , -- IN  std_logic_VECTOR(35 downto 0);
447 
    prog_full    =>  wpipe_aFull  , -- OUT std_logic;
448 
    full         =>  wpipe_Full   , -- OUT std_logic;
449 
 
450 
    rd_clk       =>  trn_clk    , -- IN  std_logic;
451 
    rd_en        =>  wpipe_rEn    , -- IN  std_logic;
452 
    dout         =>  wpipe_Qout   , -- OUT std_logic_VECTOR(35 downto 0);
453 
    empty        =>  wpipe_Empty  , -- OUT std_logic;
454 
 
455 
    rst          =>  Rst_i          -- IN  std_logic
456 
    );
457 
 
458 
 
459 
  wpipe_wEn              <=  DDR_wr_v;
460 
  wpipe_Din              <=  DDR_wr_Mask & DDR_wr_Shift & '0' & DDR_wr_sof & DDR_wr_eof & DDR_wr_Cross_Row & DDR_wr_FA & DDR_wr_din;
461 
  DDR_wr_full            <=  wpipe_aFull;
462 
  Sim_Zeichen            <=  wpipe_Empty;
463 
 
464 
 
465 
  Syn_DDR_wrD_Cross_Row:
466 
  process (trn_clk)
467 
  begin
468 
    if trn_clk'event and trn_clk = '1' then
469 
       DDR_wr_din_r1(64-1 downto 10)     <= (OTHERS=>'0');
470 
       DDR_wr_din_r1( 9 downto  0)     <= DDR_wr_din(9 downto  0) - "100";
471 
    end if;
472 
  end process;
473 
 
474 
  DDR_write_ALC      <= (DDR_wr_din_r1(10 downto 2) &"00") + ('0' & DDR_wr_din(9 downto 2) &"00");
475 
  DDR_wr_Cross_Row   <= '0';   -- DDR_write_ALC(10);
476 
 
477 
  -- ----------------------------------------------------------------------------
478 
  --
479 
  -- ----------------------------------------------------------------------------
480 
 
481 
--  DDR_pipe_read_C_fifo:
482 
--  asyn_rw_FIFO
483 
--  GENERIC MAP (
484 
--               OUTPUT_REGISTERED    => TRUE
485 
--              )
486 
--  PORT MAP(
487 
--           wClk          =>  trn_clk         ,
488 
--           wEn           =>  rpipec_wEn      ,
489 
--           Din           =>  rpipec_Din      ,
490 
--           aFull         =>  rpipec_aFull    ,
491 
--           Full          =>  rpipec_Full     ,
492 
--
493 
--           rClk          =>  ddr_Clock       ,  -- ddr_Clock_n     ,
494 
--           rEn           =>  rpipec_rEn      ,
495 
--           Qout          =>  rpipec_Qout     ,
496 
--           aEmpty        =>  rpipec_aEmpty   ,
497 
--           Empty         =>  rpipec_Empty    ,
498 
--
499 
--           Rst           =>  Rst_i
500 
--          );
501 
--
502 
 
503 
--  DDR_pipe_read_C_fifo:
504 
--  asyn_rw_FIFO72
505 
--  PORT MAP(
506 
--           wClk          =>  trn_clk       ,
507 
--           wEn           =>  rpipec_wEn     ,
508 
--           Din           =>  rpipec_Din     ,
509 
--           aFull         =>  rpipec_aFull   ,
510 
--           Full          =>  open          ,
511 
--
512 
--           rClk          =>  ddr_Clock     ,
513 
--           rEn           =>  rpipec_rEn     ,
514 
--           Qout          =>  rpipec_Qout    ,
515 
--           aEmpty        =>  open          ,
516 
--           Empty         =>  rpipec_Empty   ,
517 
--
518 
--           Rst           =>  Rst_i
519 
--          );
520 
 
521 
--  DDR_pipe_read_C_fifo:
522 
--  prim_FIFO_plain
523 
--  PORT MAP(
524 
--    wr_clk       =>  trn_clk        , -- IN  std_logic;
525 
--    wr_en        =>  rpipec_wEn     , -- IN  std_logic;
526 
--    din          =>  rpipec_Din     , -- IN  std_logic_VECTOR(35 downto 0);
527 
--    prog_full    =>  rpipec_aFull   , -- OUT std_logic;
528 
--    full         =>  open,   --rpipec_Full    , -- OUT std_logic;
529 
--
530 
--    rd_clk       =>  trn_clk      , -- IN  std_logic;
531 
--    rd_en        =>  rpipec_rEn     , -- IN  std_logic;
532 
--    dout         =>  rpipec_Qout    , -- OUT std_logic_VECTOR(35 downto 0);
533 
--    empty        =>  rpipec_Empty   , -- OUT std_logic;
534 
--
535 
--    rst          =>  Rst_i            -- IN  std_logic
536 
--    );
537 
 
538 
 
539 
  rpipec_wEn             <=  DDR_rdc_v;
540 
  rpipec_Din             <=  "00" & DDR_rdc_Shift & '0' & DDR_rdc_sof & DDR_rdc_eof & DDR_rd_Cross_Row & DDR_rdc_FA & DDR_rdc_din;
541 
  DDR_rdc_full           <=  '0';  --rpipec_aFull;
542 
 
543 
 
544 
  Syn_DDR_rdC_Cross_Row:
545 
  process (trn_clk)
546 
  begin
547 
    if trn_clk'event and trn_clk = '1' then
548 
       DDR_rdc_din_r1(64-1 downto 10)   <= (OTHERS=>'0');
549 
       DDR_rdc_din_r1( 9 downto  0)     <= DDR_rdc_din(9 downto  0) - "100";
550 
    end if;
551 
  end process;
552 
 
553 
  DDR_read_ALC       <= (DDR_rdc_din_r1(10 downto 2) &"00") + ('0' & DDR_rdc_din(9 downto 2) &"00");
554 
  DDR_rd_Cross_Row   <= '0';   -- DDR_read_ALC(10);
555 
 
556 
  -- ----------------------------------------------------------------------------
557 
  --
558 
  -- ----------------------------------------------------------------------------
559 
--  DDR_pipe_read_D_fifo:
560 
--  asyn_rw_FIFO
561 
--  GENERIC MAP (
562 
--               OUTPUT_REGISTERED    => TRUE
563 
--              )
564 
--  PORT MAP(
565 
--           wClk          =>  ddr_Clock,       -- Clk_ddr_rddata  ,  -- ddr_Clock       ,  -- ddr_Clock_n     ,
566 
--           wEn           =>  rpiped_wEn      ,
567 
--           Din           =>  rpiped_Din      ,
568 
--           aFull         =>  rpiped_aFull    ,
569 
--           Full          =>  rpiped_Full     ,
570 
--
571 
--           rClk          =>  trn_clk         ,
572 
--           rEn           =>  DDR_FIFO_RdEn   ,  -- rpiped_rEn      ,
573 
--           Qout          =>  rpiped_Qout     ,
574 
--           aEmpty        =>  open            ,  -- rpiped_aEmpty   ,
575 
--           Empty         =>  DDR_FIFO_Empty  ,  -- rpiped_Empty    ,
576 
--
577 
--           Rst           =>  Rst_i
578 
--          );
579 
 
580 
--  DDR_pipe_read_D_fifo:
581 
--  asyn_rw_FIFO72
582 
--  PORT MAP(
583 
--           wClk          =>  ddr_Clock       ,
584 
--           wEn           =>  rpiped_wEn     ,
585 
--           Din           =>  rpiped_Din     ,
586 
--           aFull         =>  rpiped_aFull   ,
587 
--           Full          =>  open          ,
588 
--
589 
--           rClk          =>  trn_clk     ,
590 
--           rEn           =>  DDR_FIFO_RdEn     ,
591 
--           Qout          =>  rpiped_Qout    ,
592 
--           aEmpty        =>  open          ,
593 
--           Empty         =>  DDR_FIFO_Empty   ,
594 
--
595 
--           Rst           =>  Rst_i
596 
--          );
597 
 
598 
  DDR_pipe_read_D_fifo:
599 
  prim_FIFO_plain
600 
  PORT MAP(
601 
    wr_clk       =>  trn_clk      , -- IN  std_logic;
602 
    wr_en        =>  rpiped_wEn      , -- IN  std_logic;
603 
    din          =>  rpiped_Din      , -- IN  std_logic_VECTOR(35 downto 0);
604 
    prog_full    =>  rpiped_aFull    , -- OUT std_logic;
605 
    full         =>  open,    -- rpiped_Full     , -- OUT std_logic;
606 
 
607 
    rd_clk       =>  trn_clk         , -- IN  std_logic;
608 
    rd_en        =>  DDR_FIFO_RdEn   , -- IN  std_logic;
609 
    dout         =>  rpiped_Qout     , -- OUT std_logic_VECTOR(35 downto 0);
610 
    empty        =>  DDR_FIFO_Empty  , -- OUT std_logic;
611 
 
612 
    rst          =>  Rst_i             -- IN  std_logic
613 
    );
614 
 
615 
 
616 
    DDR_FIFO_RdQout      <=  rpiped_Qout(C_DBUS_WIDTH-1 downto 0);
617 
 
618 
 
619 
 
620 
    -- -------------------------------------------------
621 
    -- pkt_RAM instantiate
622 
    --
623 
    pkt_RAM:
624 
    bram4096x64
625 
      port map (
626 
         clka      =>    trn_clk  ,
627 
         addra     =>    pRAM_addrA ,
628 
         wea       =>    pRAM_weA   ,
629 
         dina      =>    pRAM_dinA  ,
630 
         douta     =>    pRAM_doutA ,
631 
 
632 
         clkb      =>    trn_clk  ,
633 
         addrb     =>    pRAM_addrB ,
634 
         web       =>    pRAM_weB   ,
635 
         dinb      =>    pRAM_dinB  ,
636 
         doutb     =>    pRAM_doutB
637 
       );
638 
 
639 
    pRAM_weB       <= X"00";
640 
    pRAM_dinB      <= (Others =>'0');
641 
 
642 
 
643 
-- ------------------------------------------------
644 
-- write States synchronous
645 
--
646 
   Syn_Pseudo_DDR_wr_States:
647 
   process ( trn_clk, trn_reset_n)
648 
   begin
649 
      if trn_reset_n = '0' then
650 
         pseudo_DDR_wr_State   <= wrST_bram_RESET;
651 
         pRAM_addrA            <= (OTHERS=>'1');
652 
         pRAM_weA              <= (OTHERS=>'0');
653 
         pRAM_dinA             <= (OTHERS=>'0');
654 
         wpipe_qout_lo32b      <= (OTHERS=>'0');
655 
         wpipe_QW_Aligned      <= '1';
656 
         pRAM_AddrA_Inc        <= '1';
657 
 
658 
      elsif trn_clk'event and trn_clk = '1' then
659 
 
660 
        case pseudo_DDR_wr_State  is
661 
 
662 
          when wrST_bram_RESET =>
663 
             pseudo_DDR_wr_State   <= wrST_bram_IDLE;
664 
             pRAM_addrA            <= (OTHERS=>'1');
665 
             wpipe_QW_Aligned      <= '1';
666 
             wpipe_qout_lo32b      <= (OTHERS=>'0');
667 
             pRAM_weA              <= (OTHERS=>'0');
668 
             pRAM_dinA             <= (OTHERS=>'0');
669 
             pRAM_AddrA_Inc        <= '1';
670 
 
671 
          when wrST_bram_IDLE =>
672 
             pRAM_addrA            <= wpipe_Qout(14 downto 3);
673 
             pRAM_AddrA_Inc        <= wpipe_Qout(2);
674 
             wpipe_QW_Aligned      <= not wpipe_Qout(69);
675 
             wpipe_qout_lo32b      <= (32=>'1', OTHERS=>'0');
676 
             pRAM_weA              <= (OTHERS=>'0');
677 
             pRAM_dinA             <= pRAM_dinA;
678 
             if wpipe_read_valid = '1' then
679 
               pseudo_DDR_wr_State   <= wrST_bram_1st_Data;  -- wrST_bram_Address;
680 
             else
681 
               pseudo_DDR_wr_State   <= wrST_bram_IDLE;
682 
             end if;
683 
 
684 
 
685 
          when wrST_bram_1st_Data =>
686 
             pRAM_addrA          <= pRAM_addrA;
687 
             if wpipe_read_valid = '0' then
688 
               pseudo_DDR_wr_State <= wrST_bram_1st_Data;
689 
               pRAM_weA            <= (OTHERS=>'0'); --pRAM_weA;
690 
               pRAM_dinA           <= pRAM_dinA;
691 
             elsif wpipe_Qout(66)='1' then   -- eof
692 
                if wpipe_QW_Aligned='1' then
693 
                  pseudo_DDR_wr_State <= wrST_bram_IDLE;
694 
                  pRAM_weA            <= not ( wpipe_Qout(71) & wpipe_Qout(71) & wpipe_Qout(71) & wpipe_Qout(71)
695 
                                             & wpipe_Qout(70) & wpipe_Qout(70) & wpipe_Qout(70) & wpipe_Qout(70)
696 
                                             );
697 
                  pRAM_dinA           <= wpipe_Qout(C_DBUS_WIDTH-1 downto 0);
698 
                elsif wpipe_Qout(70)='1' then     -- mask(0)
699 
                  pseudo_DDR_wr_State <= wrST_bram_IDLE;
700 
                  pRAM_weA            <= not ( wpipe_qout_lo32b(32) & wpipe_qout_lo32b(32) & wpipe_qout_lo32b(32) & wpipe_qout_lo32b(32)
701 
                                             & wpipe_Qout(71) & wpipe_Qout(71) & wpipe_Qout(71) & wpipe_Qout(71)
702 
                                             );
703 
                  pRAM_dinA           <= wpipe_qout_lo32b(32-1 downto 0) & wpipe_Qout(C_DBUS_WIDTH-1 downto 32);
704 
                elsif wpipe_Qout(71)='1' then     -- mask(1)
705 
                  pseudo_DDR_wr_State <= wrST_bram_IDLE;
706 
                  pRAM_weA            <= X"F0";
707 
                  pRAM_dinA           <= wpipe_Qout(C_DBUS_WIDTH-1-32 downto 0) & X"00000000";
708 
                else
709 
                  pseudo_DDR_wr_State <= wrST_bram_last_DW;
710 
                  pRAM_weA            <= not ( wpipe_qout_lo32b(32) & wpipe_qout_lo32b(32) & wpipe_qout_lo32b(32) & wpipe_qout_lo32b(32)
711 
                                             & wpipe_Qout(71) & wpipe_Qout(71) & wpipe_Qout(71) & wpipe_Qout(71)
712 
                                             );
713 
                  pRAM_dinA           <= wpipe_qout_lo32b(32-1 downto 0) & wpipe_Qout(C_DBUS_WIDTH-1 downto 32);
714 
                  wpipe_qout_lo32b    <= '0' & wpipe_Qout(32-1 downto 0);
715 
                end if;
716 
             else
717 
                if wpipe_QW_Aligned='1' then
718 
                  pseudo_DDR_wr_State <= wrST_bram_more_Data;
719 
                  pRAM_weA            <= not ( wpipe_Qout(71) & wpipe_Qout(71) & wpipe_Qout(71) & wpipe_Qout(71)
720 
                                             & wpipe_Qout(70) & wpipe_Qout(70) & wpipe_Qout(70) & wpipe_Qout(70)
721 
                                             );
722 
                  pRAM_dinA           <= wpipe_Qout(C_DBUS_WIDTH-1 downto 0);
723 
                elsif pRAM_AddrA_Inc='1' then
724 
                  pseudo_DDR_wr_State <= wrST_bram_more_Data;
725 
                  pRAM_weA            <= not ( wpipe_qout_lo32b(32) & wpipe_qout_lo32b(32) & wpipe_qout_lo32b(32) & wpipe_qout_lo32b(32)
726 
                                             & wpipe_Qout(71) & wpipe_Qout(71) & wpipe_Qout(71) & wpipe_Qout(71)
727 
                                             );
728 
                  pRAM_dinA           <= wpipe_qout_lo32b(32-1 downto 0) & wpipe_Qout(C_DBUS_WIDTH-1 downto 32);
729 
                  wpipe_qout_lo32b    <= '0' & wpipe_Qout(32-1 downto 0);
730 
                else
731 
                  pseudo_DDR_wr_State <= wrST_bram_1st_Data;
732 
                  pRAM_AddrA_Inc      <= '1';
733 
                  pRAM_weA            <= X"00";
734 
                  pRAM_dinA           <= pRAM_dinA;
735 
                  wpipe_qout_lo32b    <= wpipe_Qout(70) & wpipe_Qout(32-1 downto 0);
736 
                end if;
737 
             end if;
738 
 
739 
          when wrST_bram_more_Data =>
740 
             if wpipe_read_valid = '0' then
741 
               pseudo_DDR_wr_State <= wrST_bram_more_Data;  -- wrST_bram_1st_Data;
742 
               pRAM_weA            <= (OTHERS=>'0'); --pRAM_weA;
743 
               pRAM_addrA          <= pRAM_addrA;
744 
               pRAM_dinA           <= pRAM_dinA;
745 
             elsif wpipe_Qout(66)='1' then   -- eof
746 
                if wpipe_QW_Aligned='1' then
747 
                  pseudo_DDR_wr_State <= wrST_bram_IDLE;
748 
                  pRAM_weA            <= not ( wpipe_Qout(71) & wpipe_Qout(71) & wpipe_Qout(71) & wpipe_Qout(71)
749 
                                             & wpipe_Qout(70) & wpipe_Qout(70) & wpipe_Qout(70) & wpipe_Qout(70)
750 
                                             );
751 
                  pRAM_addrA          <= pRAM_addrA + '1';
752 
                  pRAM_dinA           <= wpipe_Qout(C_DBUS_WIDTH-1 downto 0);
753 
                elsif wpipe_Qout(70)='1' then  -- mask(0)
754 
                  pseudo_DDR_wr_State <= wrST_bram_IDLE;
755 
                  pRAM_weA            <= not ( wpipe_qout_lo32b(32) & wpipe_qout_lo32b(32) & wpipe_qout_lo32b(32) & wpipe_qout_lo32b(32)
756 
                                             & wpipe_Qout(71) & wpipe_Qout(71) & wpipe_Qout(71) & wpipe_Qout(71)
757 
                                             );
758 
                  pRAM_addrA          <= pRAM_addrA + '1';
759 
                  pRAM_dinA           <= wpipe_qout_lo32b(32-1 downto 0) & wpipe_Qout(C_DBUS_WIDTH-1 downto 32);
760 
                else
761 
                  pseudo_DDR_wr_State <= wrST_bram_last_DW;
762 
                  pRAM_weA            <= not ( wpipe_qout_lo32b(32) & wpipe_qout_lo32b(32) & wpipe_qout_lo32b(32) & wpipe_qout_lo32b(32)
763 
                                             & wpipe_Qout(71) & wpipe_Qout(71) & wpipe_Qout(71) & wpipe_Qout(71)
764 
                                             );
765 
                  pRAM_addrA          <= pRAM_addrA + '1';
766 
                  pRAM_dinA           <= wpipe_qout_lo32b(32-1 downto 0) & wpipe_Qout(C_DBUS_WIDTH-1 downto 32);
767 
                  wpipe_qout_lo32b    <= '0' & wpipe_Qout(32-1 downto 0);
768 
                end if;
769 
             else
770 
                if wpipe_QW_Aligned='1' then
771 
                  pseudo_DDR_wr_State <= wrST_bram_more_Data;
772 
                  pRAM_weA            <= not ( wpipe_Qout(71) & wpipe_Qout(71) & wpipe_Qout(71) & wpipe_Qout(71)
773 
                                             & wpipe_Qout(70) & wpipe_Qout(70) & wpipe_Qout(70) & wpipe_Qout(70)
774 
                                             );
775 
                  pRAM_addrA          <= pRAM_addrA + '1';
776 
                  pRAM_dinA           <= wpipe_Qout(C_DBUS_WIDTH-1 downto 0);
777 
                else
778 
                  pseudo_DDR_wr_State <= wrST_bram_more_Data;
779 
                  pRAM_weA            <= not ( wpipe_qout_lo32b(32) & wpipe_qout_lo32b(32) & wpipe_qout_lo32b(32) & wpipe_qout_lo32b(32)
780 
                                             & wpipe_Qout(71) & wpipe_Qout(71) & wpipe_Qout(71) & wpipe_Qout(71)
781 
                                             );
782 
                  pRAM_addrA          <= pRAM_addrA + '1';
783 
                  pRAM_dinA           <= wpipe_qout_lo32b(32-1 downto 0) & wpipe_Qout(C_DBUS_WIDTH-1 downto 32);
784 
                  wpipe_qout_lo32b    <= '0' & wpipe_Qout(32-1 downto 0);
785 
                end if;
786 
             end if;
787 
 
788 
 
789 
          when wrST_bram_last_DW =>
790 
--             pseudo_DDR_wr_State   <= wrST_bram_IDLE;
791 
             pRAM_weA              <= X"F0";
792 
             pRAM_addrA            <= pRAM_addrA + '1';
793 
             pRAM_dinA             <= wpipe_qout_lo32b(32-1 downto 0) & X"00000000";
794 
             if wpipe_read_valid = '1' then
795 
               pseudo_DDR_wr_State         <= wrST_bram_1st_Data_b2b;  -- wrST_bram_Address;
796 
               wpipe_Qout_latch            <= wpipe_Qout;
797 
             else
798 
               pseudo_DDR_wr_State         <= wrST_bram_IDLE;
799 
               wpipe_Qout_latch            <= wpipe_Qout;
800 
             end if;
801 
 
802 
 
803 
          when wrST_bram_1st_Data_b2b =>
804 
             pRAM_addrA            <= wpipe_Qout_latch(14 downto 3);
805 
             wpipe_QW_Aligned      <= not wpipe_Qout_latch(69);
806 
             if wpipe_read_valid = '0' then
807 
               pseudo_DDR_wr_State <= wrST_bram_1st_Data;
808 
               pRAM_weA            <= (OTHERS=>'0'); --pRAM_weA;
809 
               pRAM_dinA           <= pRAM_dinA;
810 
               pRAM_AddrA_Inc      <= wpipe_Qout_latch(2);
811 
               wpipe_qout_lo32b    <= (32=>'1', OTHERS=>'0');
812 
             elsif wpipe_Qout(66)='1' then   -- eof
813 
                if wpipe_Qout_latch(69)='0' then   -- wpipe_QW_Aligned
814 
                  pseudo_DDR_wr_State <= wrST_bram_IDLE;
815 
                  pRAM_weA            <= not ( wpipe_Qout(71) & wpipe_Qout(71) & wpipe_Qout(71) & wpipe_Qout(71)
816 
                                             & wpipe_Qout(70) & wpipe_Qout(70) & wpipe_Qout(70) & wpipe_Qout(70)
817 
                                             );
818 
                  pRAM_dinA           <= wpipe_Qout(C_DBUS_WIDTH-1 downto 0);
819 
                  pRAM_AddrA_Inc      <= wpipe_Qout_latch(2);
820 
                  wpipe_qout_lo32b    <= (32=>'1', OTHERS=>'0');
821 
                elsif wpipe_Qout(70)='1' then     -- mask(0)
822 
                  pseudo_DDR_wr_State <= wrST_bram_IDLE;
823 
                  pRAM_weA            <= not ( X"f"
824 
                                             & wpipe_Qout(71) & wpipe_Qout(71) & wpipe_Qout(71) & wpipe_Qout(71)
825 
                                             );
826 
                  pRAM_dinA           <= X"00000000" & wpipe_Qout(C_DBUS_WIDTH-1 downto 32);
827 
                  pRAM_AddrA_Inc      <= wpipe_Qout_latch(2);
828 
                  wpipe_qout_lo32b    <= (32=>'1', OTHERS=>'0');
829 
                elsif wpipe_Qout(71)='1' then     -- mask(1)
830 
                  pseudo_DDR_wr_State <= wrST_bram_IDLE;
831 
                  pRAM_weA            <= X"F0";
832 
                  pRAM_dinA           <= wpipe_Qout(C_DBUS_WIDTH-1-32 downto 0) & X"00000000";
833 
                  pRAM_AddrA_Inc      <= wpipe_Qout_latch(2);
834 
                  wpipe_qout_lo32b    <= (32=>'1', OTHERS=>'0');
835 
                else
836 
                  pseudo_DDR_wr_State <= wrST_bram_last_DW;
837 
                  pRAM_weA            <= not ( X"f"
838 
                                             & wpipe_Qout(71) & wpipe_Qout(71) & wpipe_Qout(71) & wpipe_Qout(71)
839 
                                             );
840 
                  pRAM_dinA           <= X"00000000" & wpipe_Qout(C_DBUS_WIDTH-1 downto 32);
841 
                  pRAM_AddrA_Inc      <= wpipe_Qout_latch(2);
842 
                  wpipe_qout_lo32b    <= '0' & wpipe_Qout(32-1 downto 0);
843 
                end if;
844 
             else
845 
                if wpipe_Qout_latch(69)='0' then    -- wpipe_QW_Aligned
846 
                  pseudo_DDR_wr_State <= wrST_bram_more_Data;
847 
                  pRAM_weA            <= not ( wpipe_Qout(71) & wpipe_Qout(71) & wpipe_Qout(71) & wpipe_Qout(71)
848 
                                             & wpipe_Qout(70) & wpipe_Qout(70) & wpipe_Qout(70) & wpipe_Qout(70)
849 
                                             );
850 
                  pRAM_dinA           <= wpipe_Qout(C_DBUS_WIDTH-1 downto 0);
851 
                  pRAM_AddrA_Inc      <= wpipe_Qout_latch(2);
852 
                  wpipe_qout_lo32b    <= (32=>'1', OTHERS=>'0');
853 
                elsif wpipe_Qout_latch(2)='1' then   -- pRAM_AddrA_Inc
854 
                  pseudo_DDR_wr_State <= wrST_bram_more_Data;
855 
                  pRAM_weA            <= not ( X"f"
856 
                                             & wpipe_Qout(71) & wpipe_Qout(71) & wpipe_Qout(71) & wpipe_Qout(71)
857 
                                             );
858 
                  pRAM_dinA           <= X"00000000" & wpipe_Qout(C_DBUS_WIDTH-1 downto 32);
859 
                  pRAM_AddrA_Inc      <= wpipe_Qout_latch(2);
860 
                  wpipe_qout_lo32b    <= '0' & wpipe_Qout(32-1 downto 0);
861 
                else
862 
                  pseudo_DDR_wr_State <= wrST_bram_1st_Data;
863 
                  pRAM_AddrA_Inc      <= '1';
864 
                  pRAM_weA            <= X"00";
865 
                  pRAM_dinA           <= pRAM_dinA;
866 
                  wpipe_qout_lo32b    <= wpipe_Qout(70) & wpipe_Qout(32-1 downto 0);
867 
                end if;
868 
             end if;
869 
 
870 
 
871 
          when OTHERS =>
872 
             pseudo_DDR_wr_State   <= wrST_bram_RESET;
873 
             pRAM_addrA            <= (OTHERS=>'1');
874 
             pRAM_weA              <= (OTHERS=>'0');
875 
             pRAM_dinA             <= (OTHERS=>'0');
876 
             wpipe_qout_lo32b      <= (OTHERS=>'0');
877 
             wpipe_QW_Aligned      <= '1';
878 
             pRAM_AddrA_Inc        <= '1';
879 
 
880 
        end case;
881 
 
882 
      end if;
883 
   end process;
884 
 
885 
 
886 
   --
887 
   Syn_wPipe_read:
888 
   process ( trn_clk, DDR_Ready_i)
889 
   begin
890 
      if DDR_Ready_i = '0' then
891 
         wpipe_rEn         <= '0';
892 
         wpipe_read_valid  <= '0';
893 
 
894 
      elsif trn_clk'event and trn_clk = '1' then
895 
 
896 
         wpipe_rEn         <= '1';
897 
         wpipe_read_valid  <= wpipe_rEn and not wpipe_Empty;
898 
 
899 
      end if;
900 
   end process;
901 
 
902 
 
903 
 
904 
   --
905 
   Syn_rPipeC_read:
906 
   process ( trn_clk, DDR_Ready_i)
907 
   begin
908 
      if DDR_Ready_i = '0' then
909 
         rpiped_wr_postpone   <= '0';
910 
         rpiped_wr_skew       <= '0';
911 
 
912 
      elsif trn_clk'event and trn_clk = '1' then
913 
 
914 
         if DDR_rdc_v='1' then
915 
            rpiped_wr_postpone  <= DDR_rdc_din(2) and not DDR_rdc_Shift;
916 
            rpiped_wr_skew      <= DDR_rdc_Shift xor DDR_rdc_din(2);
917 
         else
918 
            rpiped_wr_postpone  <= rpiped_wr_postpone;
919 
            rpiped_wr_skew      <= rpiped_wr_skew;
920 
         end if;
921 
 
922 
      end if;
923 
   end process;
924 
 
925 
-- ------------------------------------------------
926 
-- Read States synchronous
927 
--
928 
   Syn_Pseudo_DDR_rd_States:
929 
   process ( trn_clk, DDR_Ready_i)
930 
   begin
931 
      if DDR_Ready_i = '0' then
932 
         pseudo_DDR_rd_State   <= rdST_bram_RESET;
933 
--         rpipec_rEn            <= '0';
934 
         pRAM_addrB            <= (OTHERS=>'1');
935 
         rpiped_rd_counter     <= (OTHERS=>'0');
936 
         rpiped_wEn_b3         <= '0';
937 
         rpiped_wr_EOF         <= '0';
938 
         rpipec_Din_r          <= (OTHERS=>'0');
939 
 
940 
      elsif trn_clk'event and trn_clk = '1' then
941 
 
942 
        case pseudo_DDR_rd_State  is
943 
 
944 
          when rdST_bram_RESET =>
945 
             pseudo_DDR_rd_State   <= rdST_bram_IDLE;
946 
--             rpipec_rEn            <= '0';
947 
             rpipec_Din_r          <= (OTHERS=>'0');
948 
             pRAM_addrB            <= (OTHERS=>'1');
949 
             rpiped_rd_counter     <= (OTHERS=>'0');
950 
             rpiped_wEn_b3         <= '0';
951 
             rpiped_wr_EOF         <= '0';
952 
 
953 
          when rdST_bram_IDLE =>
954 
             pRAM_addrB            <= pRAM_addrB;
955 
             rpiped_rd_counter     <= (OTHERS=>'0');
956 
             rpiped_wEn_b3         <= '0';
957 
             rpiped_wr_EOF         <= '0';
958 
             if rpipec_wEn = '1' then
959 
--               rpipec_rEn          <= '1';
960 
               rpipec_Din_r        <= rpipec_Din;
961 
               pseudo_DDR_rd_State <= rdST_bram_LA;  --rdST_bram_b4_Length;
962 
             else
963 
--               rpipec_rEn          <= '0';
964 
               rpipec_Din_r        <= rpipec_Din_r;
965 
               pseudo_DDR_rd_State <= rdST_bram_IDLE;
966 
             end if;
967 
 
968 
--          when rdST_bram_b4_LA =>
969 
--             pRAM_addrB            <= pRAM_addrB;
970 
--             rpiped_rd_counter     <= (OTHERS=>'0');
971 
--             rpiped_wEn_b3         <= '0';
972 
--             rpiped_wr_EOF         <= '0';
973 
--             rpipec_rEn            <= '0';
974 
--             pseudo_DDR_rd_State   <= rdST_bram_LA;
975 
 
976 
          when rdST_bram_LA =>
977 
--             rpipec_rEn            <= '0';
978 
             pRAM_addrB            <= rpipec_Din_r(14 downto 3);
979 
             rpiped_wr_EOF         <= '0';
980 
             rpiped_wEn_b3         <= '0';
981 
             if rpipec_Din_r(2+32)='1' then
982 
               rpiped_rd_counter     <= rpipec_Din_r(11+32 downto 2+32) + '1';
983 
             elsif rpipec_Din_r(2)='1' and rpipec_Din_r(69)='1' then
984 
               rpiped_rd_counter     <= rpipec_Din_r(11+32 downto 2+32) + "10";
985 
             elsif rpipec_Din_r(2)='0' and rpipec_Din_r(69)='1' then
986 
               rpiped_rd_counter     <= rpipec_Din_r(11+32 downto 2+32) + "10";
987 
             elsif rpipec_Din_r(2)='1' and rpipec_Din_r(69)='0' then
988 
               rpiped_rd_counter     <= rpipec_Din_r(11+32 downto 2+32);
989 
             else
990 
               rpiped_rd_counter     <= rpipec_Din_r(11+32 downto 2+32);
991 
             end if;
992 
 
993 
--             elsif rpipec_Qout(2)='1' then
994 
--               rpiped_rd_counter     <= rpipec_Qout(11+32 downto 2+32) + "10";
995 
--             elsif rpipec_Qout(69)='1' then
996 
--               rpiped_rd_counter     <= rpipec_Qout(11+32 downto 2+32) + "10";
997 
--             else
998 
--               rpiped_rd_counter     <= rpipec_Qout(11+32 downto 2+32);
999 
--             end if;
1000 
             pseudo_DDR_rd_State   <= rdST_bram_Data;
1001 
 
1002 
 
1003 
          when rdST_bram_Data =>
1004 
--             rpipec_rEn            <= '0';
1005 
             if rpiped_rd_counter = CONV_STD_LOGIC_VECTOR(2, 10) then
1006 
               pRAM_addrB            <= pRAM_addrB + '1';
1007 
               rpiped_rd_counter     <= rpiped_rd_counter;
1008 
               rpiped_wEn_b3         <= '1';
1009 
               rpiped_wr_EOF         <= '1';
1010 
               pseudo_DDR_rd_State   <= rdST_bram_IDLE;
1011 
             elsif rpiped_aFull = '1' then
1012 
               pRAM_addrB            <= pRAM_addrB;
1013 
               rpiped_rd_counter     <= rpiped_rd_counter;
1014 
               rpiped_wEn_b3         <= '0';
1015 
               rpiped_wr_EOF         <= '0';
1016 
               pseudo_DDR_rd_State   <= rdST_bram_Data;
1017 
             else
1018 
               pRAM_addrB            <= pRAM_addrB + '1';
1019 
               rpiped_rd_counter     <= rpiped_rd_counter - "10";
1020 
               rpiped_wEn_b3         <= '1';
1021 
               rpiped_wr_EOF         <= '0';
1022 
               pseudo_DDR_rd_State   <= rdST_bram_Data;
1023 
             end if;
1024 
 
1025 
 
1026 
          when OTHERS =>
1027 
--               rpipec_rEn            <= '0';
1028 
               pRAM_addrB            <= pRAM_addrB;
1029 
               rpiped_rd_counter     <= rpiped_rd_counter;
1030 
               rpiped_wEn_b3         <= '0';
1031 
               rpiped_wr_EOF         <= '0';
1032 
               pseudo_DDR_rd_State   <= rdST_bram_RESET;
1033 
 
1034 
        end case;
1035 
 
1036 
      end if;
1037 
   end process;
1038 
 
1039 
 
1040 
 
1041 
   Syn_Pseudo_DDR_rdd_write:
1042 
   process ( trn_clk, DDR_Ready_i)
1043 
   begin
1044 
      if DDR_Ready_i = '0' then
1045 
         rpiped_wEn_b1      <= '0';
1046 
         rpiped_wEn_b2      <= '0';
1047 
         rpiped_wEn         <= '0';
1048 
         rpiped_Din         <= (OTHERS=>'0');
1049 
 
1050 
      elsif trn_clk'event and trn_clk = '1' then
1051 
 
1052 
         rpiped_wEn_b2      <= rpiped_wEn_b3;
1053 
         rpiped_wEn_b1      <= rpiped_wEn_b2;
1054 
         if rpiped_wr_skew='1' then
1055 
--           rpiped_wEn         <= rpiped_wEn_b2;
1056 
           rpiped_wEn         <= (rpiped_wEn_b2 and not rpiped_wr_postpone)
1057 
                              or (rpiped_wEn_b1 and rpiped_wr_postpone);
1058 
           rpiped_Din         <= "0000" & '0' & rpiped_wr_EOF & "00" & pRAM_doutB_shifted;
1059 
         else
1060 
--           rpiped_wEn         <= rpiped_wEn_b2;
1061 
           rpiped_wEn         <= (rpiped_wEn_b2 and not rpiped_wr_postpone)
1062 
                              or (rpiped_wEn_b1 and rpiped_wr_postpone);
1063 
           rpiped_Din         <= "0000" & '0' & rpiped_wr_EOF & "00" & pRAM_doutB;
1064 
         end if;
1065 
 
1066 
      end if;
1067 
   end process;
1068 
 
1069 
 
1070 
  --
1071 
  DDR_Blinker_Module:
1072 
  DDR_Blink
1073 
  PORT MAP(
1074 
           DDR_Blinker          =>  DDR_Blinker    ,
1075 
 
1076 
           DBG_dma_start        =>  DBG_dma_start  ,
1077 
           DBG_bram_wea         =>  pRAM_weA       ,
1078 
           DBG_bram_addra       =>  pRAM_addrA     ,
1079 
 
1080 
           DDR_Write            =>  wpipe_rEn      ,
1081 
           DDR_Read             =>  rpiped_wEn     ,
1082 
           DDR_Both             =>  '0'            ,
1083 
 
1084 
           ddr_Clock            =>  trn_clk        ,
1085 
           DDr_Rst_n            =>  DDR_Ready_i      -- DDR_CKE_i
1086 
          );
1087 
 
1088 
 
1089 
end architecture Behavioral;

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