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weng_ziti |
-- -------------------------------------------------------------
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--
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-- Purpose: This package defines supplemental types, subtypes,
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-- constants, and functions
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--
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-- Nov 2008 --> 64-bit
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--
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library IEEE;
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use IEEE.STD_LOGIC_1164.ALL;
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use IEEE.STD_LOGIC_ARITH.ALL;
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package abb64Package is
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-- Declare constants
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-- ----------------------------------------------------------------------
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-- Address definitions
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-- The 2 MSB's are for Addressing, i.e.
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--
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-- 0x0000 : Design ID
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-- 0x0008 : Interrupt status
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-- 0x0010 : Interrupt enable
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-- 0x0018 : General error
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-- 0x0020 : General status
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-- 0x0028 : General control
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-- 0x002C ~ 0x004C: DMA upstream registers
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-- 0x0050 ~ 0x0070: DMA upstream registers
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-- 0x0074 : MRd channel control
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-- 0x0078 : CplD channel control
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-- 0x007C : ICAP input/output
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-- 0x0080 ~ 0x008C: Interrupt Generator (IG) registers
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-- 0x4010 : TxFIFO write port
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-- 0x4018 : W - TxFIFO Reset
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-- : R - TxFIFO Vacancy status
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-- 0x4020 : RxFIFO read port
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-- 0x4028 : W - RxFIFO Reset
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-- : R - RxFIFO Occupancy status
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-- 0x8000 ~ 0xBFFF: BRAM space (BAR1)
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-- Others : Reserved
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------------------------------------------------------------------------
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-- Global Constants
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--
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--- Number of Lanes for PCIe, 1, 4 or 8
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Constant C_NUM_PCIE_LANES : integer := 4;
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--- Data bus width
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Constant C_DBUS_WIDTH : integer := 64;
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--- Event Buffer: FIFO Data Count width
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Constant C_FIFO_DC_WIDTH : integer := 26;
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--- Small BRAM FIFO for emulation
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Constant C_EMU_FIFO_DC_WIDTH : integer := 14;
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--- Address width for endpoint device/peripheral
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--
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Constant C_EP_AWIDTH : integer range 10 to 30
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:= 16;
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--- Buffer width from the PCIe Core
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Constant C_TBUF_AWIDTH : integer := 4; -- 5;
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--- Width for Tx output Arbitration
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Constant C_ARBITRATE_WIDTH : integer := 4;
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--- Number of BAR spaces
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Constant CINT_BAR_SPACES : integer := 4;
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--- Max BAR number, 7
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Constant C_BAR_NUMBER : integer := 7;
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--- Encoded BAR number takes 3 bits to represent 0~6. 7 means invalid or don't care
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Constant C_ENCODE_BAR_NUMBER : integer := 3;
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--- Number of Channels, currently 4: Interrupt, PIO MRd, upstream DMA, downstream DMA
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Constant C_CHANNEL_NUMBER : integer := 4;
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--- Data width of the channel buffers (FIFOs)
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Constant C_CHANNEL_BUF_WIDTH : integer := 128;
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--- Higher 4 bits are for tag decoding
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Constant C_TAG_DECODE_BITS : integer := 4;
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--- DDR SDRAM bank address pin number
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Constant C_DDR_BANK_AWIDTH : integer := 2;
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--- DDR SDRAM address pin number
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Constant C_DDR_AWIDTH : integer := 13;
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--- DDR SDRAM data pin number
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Constant C_DDR_DWIDTH : integer := 16;
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--- DDR SDRAM module address width, dependent on total DDR memory capacity.
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-- 128 Mb= 16MB : 24
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-- 256 Mb= 32MB : 25
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-- 512 Mb= 64MB : 26
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-- 1024 Mb= 128MB : 27
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-- 2048 Mb= 256MB : 28
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Constant C_DDR_IAWIDTH : integer range 24 to 28
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:= 26;
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--- Block RAM address bus width. Variation requires BRAM core regeneration.
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Constant C_PRAM_AWIDTH : integer range 8 to 28
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:= 12;
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--- Width for Interrupt generation counter
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Constant C_CNT_GINT_WIDTH : integer := 30;
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-- --- Emulation FIFOs' address width
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-- Constant C_FIFO_AWIDTH : integer := 5;
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--- Tag RAM data bus width, 1 bit for AInc information and 3 bits for BAR number
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Constant C_TAGRAM_DWIDTH : integer := 36;
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--- Configuration command width, e.g. cfg_dcommand, cfg_lcommand.
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Constant C_CFG_COMMAND_DWIDTH : integer := 16;
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--- Tag RAM address bus width, only 6 bits (of 8) are used for MRd from DMA Write Channel
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Constant C_TAGRAM_AWIDTH : integer := 6;
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Constant C_TAG_MAP_WIDTH : integer := 64; -- 2^C_TAGRAM_AWIDTH
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-- TAG map are partitioned into sub-parts
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Constant C_SUB_TAG_MAP_WIDTH : integer := 8;
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--- Address_Increment bit is put in tag RAM
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Constant CBIT_AINC_IN_TAGRAM : integer := C_TAGRAM_DWIDTH-1;
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-- Bit range of BAR field in TAG ram
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Constant C_TAGBAR_BIT_TOP : integer := CBIT_AINC_IN_TAGRAM-1;
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Constant C_TAGBAR_BIT_BOT : integer := C_TAGBAR_BIT_TOP-C_ENCODE_BAR_NUMBER+1;
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--- Number of bits for Last DW BE and 1st DW BE in the header of a TLP
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Constant C_BE_WIDTH : integer := 4;
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--- ICAP width: 8 or 32.
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Constant C_ICAP_WIDTH : integer := 32;
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--- Feature Bits width
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Constant C_FEAT_BITS_WIDTH : integer := 8;
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--- Channel lables
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Constant C_CHAN_INDEX_IRPT : integer := 3;
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Constant C_CHAN_INDEX_MRD : integer := 2;
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Constant C_CHAN_INDEX_DMA_DS : integer := 1;
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Constant C_CHAN_INDEX_DMA_US : integer := 0;
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------------------------------------------------------------------------
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-- Bit ranges
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-- Bits range for Max_Read_Request_Size in cfg_dcommand
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Constant C_CFG_MRS_BIT_TOP : integer := 14;
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Constant C_CFG_MRS_BIT_BOT : integer := 12;
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-- Bits range for Max_Payload_Size in cfg_dcommand
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Constant C_CFG_MPS_BIT_TOP : integer := 7;
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Constant C_CFG_MPS_BIT_BOT : integer := 5;
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-- The bit in minimum Max_Read_Request_Size/Max_Payload_Size that is one
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-- i.e. 0x80 Bytes = 0x20 DW = "000000100000"
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Constant CBIT_SENSE_OF_MAXSIZE : integer := 5;
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-- ------------------------------------------------------------------------
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--
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-- Section for TLP headers' bit definition
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-- ( not shown in user header file)
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--
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-- ------------------------------------------------------------------------
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-- -- The bit in TLP header #0 that means whether the TLP comes with data
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-- Constant CBIT_TLP_HAS_PAYLOAD : integer := 30;
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-- -- The bit in TLP header #0 that means whether the TLP has 4-DW header
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-- Constant CBIT_TLP_HAS_4DW_HEAD : integer := 29;
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-- -- The bit in TLP header #0 that means Cpl/CplD
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-- Constant C_TLP_CPLD_BIT : integer := 27;
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-- The bit in TLP header #0 that means TLP Digest
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Constant C_TLP_TD_BIT : integer := 15 +32;
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-- The bit in TLP header #0 that means Error Poison
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Constant C_TLP_EP_BIT : integer := 14 +32;
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-- Bit range of Format field in TLP header #0
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Constant C_TLP_FMT_BIT_TOP : integer := 30 +32; -- TLP has payload
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Constant C_TLP_FMT_BIT_BOT : integer := 29 +32; -- TLP header has 4 DW
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-- Bit range of Type field in TLP header #0
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Constant C_TLP_TYPE_BIT_TOP : integer := 28 +32;
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Constant C_TLP_TYPE_BIT_BOT : integer := 24 +32;
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-- Bit range of TC field in TLP header #0
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Constant C_TLP_TC_BIT_TOP : integer := 22 +32;
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Constant C_TLP_TC_BIT_BOT : integer := 20 +32;
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-- Bit range of Attribute field in TLP header #0
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Constant C_TLP_ATTR_BIT_TOP : integer := 13 +32;
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Constant C_TLP_ATTR_BIT_BOT : integer := 12 +32;
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-- Bit range of Length field in TLP header #0
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Constant C_TLP_LENG_BIT_TOP : integer := 9 +32;
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Constant C_TLP_LENG_BIT_BOT : integer := 0 +32;
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-- Bit range of Requester ID field in header #1 of non-Cpl/D TLP
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Constant C_TLP_REQID_BIT_TOP : integer := 31;
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Constant C_TLP_REQID_BIT_BOT : integer := 16;
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-- Bit range of Tag field in header #1 of non-Cpl/D TLP
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Constant C_TLP_TAG_BIT_TOP : integer := 15;
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Constant C_TLP_TAG_BIT_BOT : integer := 8;
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-- Bit range of Last BE field in TLP header #1
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Constant C_TLP_LAST_BE_BIT_TOP : integer := 7;
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Constant C_TLP_LAST_BE_BIT_BOT : integer := 4;
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-- Bit range of 1st BE field in TLP header #1
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Constant C_TLP_1ST_BE_BIT_TOP : integer := 3;
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Constant C_TLP_1ST_BE_BIT_BOT : integer := 0;
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-- Bit range of Completion Status field in Cpl/D TLP header #1
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Constant C_CPLD_CS_BIT_TOP : integer := 15;
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Constant C_CPLD_CS_BIT_BOT : integer := 13;
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-- Bit range of Completion Byte Count field in Cpl/D TLP header #1
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Constant C_CPLD_BC_BIT_TOP : integer := 11;
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Constant C_CPLD_BC_BIT_BOT : integer := 0;
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-- Bit range of Completer ID field in header#1 of Cpl/D TLP
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Constant C_CPLD_CPLT_ID_BIT_TOP : integer := C_TLP_REQID_BIT_TOP;
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Constant C_CPLD_CPLT_ID_BIT_BOT : integer := C_TLP_REQID_BIT_BOT;
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-- Bit range of Requester ID field in header#2 of Cpl/D TLP
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Constant C_CPLD_REQID_BIT_TOP : integer := 31 +32;
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Constant C_CPLD_REQID_BIT_BOT : integer := 16 +32;
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-- Bit range of Completion Tag field in Cpl/D TLP 3rd header
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Constant C_CPLD_TAG_BIT_TOP : integer := C_TLP_TAG_BIT_TOP +32;
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Constant C_CPLD_TAG_BIT_BOT : integer := C_TLP_TAG_BIT_BOT +32;
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-- Bit range of Completion Lower Address field in Cpl/D TLP 3rd header
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Constant C_CPLD_LA_BIT_TOP : integer := 6 +32;
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Constant C_CPLD_LA_BIT_BOT : integer := 0 +32;
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-- Bit range of Message Code field in Msg 2nd header
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Constant C_MSG_CODE_BIT_TOP : integer := 7;
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Constant C_MSG_CODE_BIT_BOT : integer := 0;
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-- ----------------------------------------------------------------------
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-- TLP field widths
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-- For PCIe, the length field is 10 bits wide.
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Constant C_TLP_FLD_WIDTH_OF_LENG : integer
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:= C_TLP_LENG_BIT_TOP-C_TLP_LENG_BIT_BOT+1;
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------------------------------------------------------------------------
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--- Tag width in TLP
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Constant C_TAG_WIDTH : integer
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:= C_TLP_TAG_BIT_TOP-C_TLP_TAG_BIT_BOT+1;
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------------------------------------------------------------------------
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--- Width for Local ID
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Constant C_ID_WIDTH : integer
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:= C_TLP_REQID_BIT_TOP-C_TLP_REQID_BIT_BOT+1;
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------------------------------------------------------------------------
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--- Width for Requester ID
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Constant C_REQID_WIDTH : integer
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:= C_TLP_REQID_BIT_TOP-C_TLP_REQID_BIT_BOT+1;
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-- ------------------------------------------------------------------------
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-- Section for Channel Buffer bit definition, referenced to TLP header definition
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-- ( not shown in user header file)
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--
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-- ------------------------------------------------------------------------
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-- Bit range of Length field in Channel Buffer word
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Constant C_CHBUF_LENG_BIT_BOT : integer := 0;
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Constant C_CHBUF_LENG_BIT_TOP : integer := C_CHBUF_LENG_BIT_BOT+C_TLP_FLD_WIDTH_OF_LENG-1; -- 9
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-- Bit range of Attribute field in Channel Buffer word
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Constant C_CHBUF_ATTR_BIT_BOT : integer := C_CHBUF_LENG_BIT_TOP+1; --10;
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Constant C_CHBUF_ATTR_BIT_TOP : integer := C_CHBUF_ATTR_BIT_BOT+C_TLP_ATTR_BIT_TOP-C_TLP_ATTR_BIT_BOT; --11;
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-- The bit in Channel Buffer word that means Error Poison
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Constant C_CHBUF_EP_BIT : integer := C_CHBUF_ATTR_BIT_TOP+1; --12;
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-- The bit in Channel Buffer word that means TLP Digest
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Constant C_CHBUF_TD_BIT : integer := C_CHBUF_EP_BIT+1; --13;
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-- Bit range of TC field in Channel Buffer word
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Constant C_CHBUF_TC_BIT_BOT : integer := C_CHBUF_TD_BIT+1; --14;
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Constant C_CHBUF_TC_BIT_TOP : integer := C_CHBUF_TC_BIT_BOT+C_TLP_TC_BIT_TOP-C_TLP_TC_BIT_BOT; --16;
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-- Bit range of Format field in Channel Buffer word
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Constant C_CHBUF_FMT_BIT_BOT : integer := C_CHBUF_TC_BIT_TOP+1; --17;
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Constant C_CHBUF_FMT_BIT_TOP : integer := C_CHBUF_FMT_BIT_BOT+C_TLP_FMT_BIT_TOP-C_TLP_FMT_BIT_BOT; --18;
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-- Bit range of Tag field in Channel Buffer word except Cpl/D
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Constant C_CHBUF_TAG_BIT_BOT : integer := C_CHBUF_FMT_BIT_TOP+1; --19;
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Constant C_CHBUF_TAG_BIT_TOP : integer := C_CHBUF_TAG_BIT_BOT+C_TLP_TAG_BIT_TOP-C_TLP_TAG_BIT_BOT; --26;
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-- Bit range of BAR Index field in upstream DMA Channel Buffer word
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Constant C_CHBUF_DMA_BAR_BIT_BOT : integer := C_CHBUF_TAG_BIT_TOP+1; --27;
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Constant C_CHBUF_DMA_BAR_BIT_TOP : integer := C_CHBUF_DMA_BAR_BIT_BOT+C_ENCODE_BAR_NUMBER-1; --29;
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-- Bit range of Message Code field in Channel Buffer word for Msg
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Constant C_CHBUF_MSG_CODE_BIT_BOT : integer := C_CHBUF_TAG_BIT_TOP+1; --27;
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Constant C_CHBUF_MSG_CODE_BIT_TOP : integer := C_CHBUF_MSG_CODE_BIT_BOT+C_MSG_CODE_BIT_TOP-C_MSG_CODE_BIT_BOT; --34;
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|
|
-- Bit range of remaining Byte Count field in Cpl/D Channel Buffer word
|
330 |
|
|
Constant C_CHBUF_CPLD_BC_BIT_BOT : integer := C_CHBUF_FMT_BIT_TOP+1; --19;
|
331 |
|
|
Constant C_CHBUF_CPLD_BC_BIT_TOP : integer := C_CHBUF_CPLD_BC_BIT_BOT+C_TLP_FLD_WIDTH_OF_LENG-1+2; --30;
|
332 |
|
|
|
333 |
|
|
-- Bit range of Completion Status field in Cpl/D Channel Buffer word
|
334 |
|
|
Constant C_CHBUF_CPLD_CS_BIT_BOT : integer := C_CHBUF_CPLD_BC_BIT_TOP+1; --31;
|
335 |
|
|
Constant C_CHBUF_CPLD_CS_BIT_TOP : integer := C_CHBUF_CPLD_CS_BIT_BOT+C_CPLD_CS_BIT_TOP-C_CPLD_CS_BIT_BOT; --33;
|
336 |
|
|
|
337 |
|
|
-- Bit range of Lower Address field in Cpl/D Channel Buffer word
|
338 |
|
|
Constant C_CHBUF_CPLD_LA_BIT_BOT : integer := C_CHBUF_CPLD_CS_BIT_TOP+1; --34;
|
339 |
|
|
Constant C_CHBUF_CPLD_LA_BIT_TOP : integer := C_CHBUF_CPLD_LA_BIT_BOT+C_CPLD_LA_BIT_TOP-C_CPLD_LA_BIT_BOT; --40;
|
340 |
|
|
|
341 |
|
|
-- Bit range of Tag field in Cpl/D Channel Buffer word
|
342 |
|
|
Constant C_CHBUF_CPLD_TAG_BIT_BOT : integer := C_CHBUF_CPLD_LA_BIT_TOP+1; --41;
|
343 |
|
|
Constant C_CHBUF_CPLD_TAG_BIT_TOP : integer := C_CHBUF_CPLD_TAG_BIT_BOT+C_CPLD_TAG_BIT_TOP-C_CPLD_TAG_BIT_BOT; --48;
|
344 |
|
|
|
345 |
|
|
-- Bit range of Requester ID field in Cpl/D Channel Buffer word
|
346 |
|
|
Constant C_CHBUF_CPLD_REQID_BIT_BOT : integer := C_CHBUF_CPLD_TAG_BIT_TOP+1; --49;
|
347 |
|
|
Constant C_CHBUF_CPLD_REQID_BIT_TOP : integer := C_CHBUF_CPLD_REQID_BIT_BOT+C_CPLD_REQID_BIT_TOP-C_CPLD_REQID_BIT_BOT; --64;
|
348 |
|
|
|
349 |
|
|
|
350 |
|
|
|
351 |
|
|
-- Bit range of BAR Index field in Cpl/D Channel Buffer word
|
352 |
|
|
Constant C_CHBUF_CPLD_BAR_BIT_BOT : integer := C_CHBUF_CPLD_REQID_BIT_TOP+1; --65;
|
353 |
|
|
Constant C_CHBUF_CPLD_BAR_BIT_TOP : integer := C_CHBUF_CPLD_BAR_BIT_BOT+C_ENCODE_BAR_NUMBER-1; --67;
|
354 |
|
|
|
355 |
|
|
|
356 |
|
|
-- Bit range of host address in Channel Buffer word
|
357 |
|
|
Constant C_CHBUF_HA_BIT_BOT : integer := C_CHBUF_DMA_BAR_BIT_TOP+1; --30;
|
358 |
|
|
-- Constant C_CHBUF_HA_BIT_TOP : integer := C_CHBUF_HA_BIT_BOT+2*C_DBUS_WIDTH-1; --93;
|
359 |
|
|
Constant C_CHBUF_HA_BIT_TOP : integer := C_CHBUF_HA_BIT_BOT+C_DBUS_WIDTH-1; --93;
|
360 |
|
|
|
361 |
|
|
|
362 |
|
|
-- The bit in Channel Buffer word that means whether this TLP is valid for output arbitration
|
363 |
|
|
-- (against channel buffer reset during arbitration)
|
364 |
|
|
Constant C_CHBUF_QVALID_BIT : integer := C_CHBUF_HA_BIT_TOP+1; --94;
|
365 |
|
|
|
366 |
|
|
-- The bit in Channel Buffer word that means address increment
|
367 |
|
|
Constant C_CHBUF_AINC_BIT : integer := C_CHBUF_QVALID_BIT+1; --95;
|
368 |
|
|
|
369 |
|
|
-- The bit in Channel Buffer word that means zero-length
|
370 |
|
|
Constant C_CHBUF_0LENG_BIT : integer := C_CHBUF_AINC_BIT+1; --96;
|
371 |
|
|
|
372 |
|
|
|
373 |
|
|
|
374 |
|
|
-- Bit range of peripheral address in Channel Buffer word
|
375 |
|
|
Constant C_CHBUF_PA_BIT_BOT : integer := C_CHANNEL_BUF_WIDTH-C_EP_AWIDTH; --112;
|
376 |
|
|
Constant C_CHBUF_PA_BIT_TOP : integer := C_CHANNEL_BUF_WIDTH-1; --127;
|
377 |
|
|
|
378 |
|
|
|
379 |
|
|
-- Bit range of BRAM address in Channel Buffer word
|
380 |
|
|
Constant C_CHBUF_MA_BIT_BOT : integer := C_CHANNEL_BUF_WIDTH-C_PRAM_AWIDTH-2; --114;
|
381 |
|
|
Constant C_CHBUF_MA_BIT_TOP : integer := C_CHANNEL_BUF_WIDTH-1; --127;
|
382 |
|
|
|
383 |
|
|
-- Bit range of DDR address in Channel Buffer word
|
384 |
|
|
Constant C_CHBUF_DDA_BIT_BOT : integer := C_CHANNEL_BUF_WIDTH-C_DDR_IAWIDTH; --102;
|
385 |
|
|
Constant C_CHBUF_DDA_BIT_TOP : integer := C_CHANNEL_BUF_WIDTH-1; --127;
|
386 |
|
|
|
387 |
|
|
|
388 |
|
|
|
389 |
|
|
------------------------------------------------------------------------
|
390 |
|
|
-- The Relaxed Ordering bit constant in TLP
|
391 |
|
|
Constant C_RELAXED_ORDERING : std_logic
|
392 |
|
|
:= '0';
|
393 |
|
|
|
394 |
|
|
-- The NO SNOOP bit constant in TLP
|
395 |
|
|
Constant C_NO_SNOOP : std_logic
|
396 |
|
|
:= '0'; -- '1';
|
397 |
|
|
|
398 |
|
|
-- AK, 2007-11-07: SNOOP-bit corrupts DMA, if set on INTEL platform. Seems to be don't care on AMD
|
399 |
|
|
|
400 |
|
|
------------------------------------------------------------------------
|
401 |
|
|
-- TLP resolution concerning Format
|
402 |
|
|
Constant C_FMT3_NO_DATA : std_logic_vector(C_TLP_FMT_BIT_TOP downto C_TLP_FMT_BIT_BOT)
|
403 |
|
|
:= "00";
|
404 |
|
|
Constant C_FMT3_WITH_DATA : std_logic_vector(C_TLP_FMT_BIT_TOP downto C_TLP_FMT_BIT_BOT)
|
405 |
|
|
:= "10";
|
406 |
|
|
|
407 |
|
|
Constant C_FMT4_NO_DATA : std_logic_vector(C_TLP_FMT_BIT_TOP downto C_TLP_FMT_BIT_BOT)
|
408 |
|
|
:= "01";
|
409 |
|
|
Constant C_FMT4_WITH_DATA : std_logic_vector(C_TLP_FMT_BIT_TOP downto C_TLP_FMT_BIT_BOT)
|
410 |
|
|
:= "11";
|
411 |
|
|
|
412 |
|
|
-- TLP resolution concerning Type
|
413 |
|
|
Constant C_TYPE_MEM_REQ : std_logic_vector(C_TLP_TYPE_BIT_TOP downto C_TLP_TYPE_BIT_BOT)
|
414 |
|
|
:= "00000";
|
415 |
|
|
Constant C_TYPE_IO_REQ : std_logic_vector(C_TLP_TYPE_BIT_TOP downto C_TLP_TYPE_BIT_BOT)
|
416 |
|
|
:= "00010";
|
417 |
|
|
|
418 |
|
|
Constant C_TYPE_MEM_REQ_LK : std_logic_vector(C_TLP_TYPE_BIT_TOP downto C_TLP_TYPE_BIT_BOT)
|
419 |
|
|
:= "00001";
|
420 |
|
|
Constant C_TYPE_COMPLETION : std_logic_vector(C_TLP_TYPE_BIT_TOP downto C_TLP_TYPE_BIT_BOT)
|
421 |
|
|
:= "01010";
|
422 |
|
|
Constant C_TYPE_COMPLETION_LK : std_logic_vector(C_TLP_TYPE_BIT_TOP downto C_TLP_TYPE_BIT_BOT)
|
423 |
|
|
:= "01011";
|
424 |
|
|
|
425 |
|
|
Constant C_TYPE_MSG_TO_ROOT : std_logic_vector(C_TLP_TYPE_BIT_TOP downto C_TLP_TYPE_BIT_BOT)
|
426 |
|
|
:= "10000";
|
427 |
|
|
Constant C_TYPE_MSG_BY_ADDRESS : std_logic_vector(C_TLP_TYPE_BIT_TOP downto C_TLP_TYPE_BIT_BOT)
|
428 |
|
|
:= "10001";
|
429 |
|
|
Constant C_TYPE_MSG_BY_ID : std_logic_vector(C_TLP_TYPE_BIT_TOP downto C_TLP_TYPE_BIT_BOT)
|
430 |
|
|
:= "10010";
|
431 |
|
|
Constant C_TYPE_MSG_FROM_ROOT : std_logic_vector(C_TLP_TYPE_BIT_TOP downto C_TLP_TYPE_BIT_BOT)
|
432 |
|
|
:= "10011";
|
433 |
|
|
Constant C_TYPE_MSG_LOCAL : std_logic_vector(C_TLP_TYPE_BIT_TOP downto C_TLP_TYPE_BIT_BOT)
|
434 |
|
|
:= "10100";
|
435 |
|
|
Constant C_TYPE_MSG_GATHER_TO_ROOT : std_logic_vector(C_TLP_TYPE_BIT_TOP downto C_TLP_TYPE_BIT_BOT)
|
436 |
|
|
:= "10101";
|
437 |
|
|
|
438 |
|
|
-- Select this constant to test system response
|
439 |
|
|
Constant C_TYPE_OF_MSG : std_logic_vector(C_TLP_TYPE_BIT_TOP downto C_TLP_TYPE_BIT_BOT)
|
440 |
|
|
:= C_TYPE_MSG_LOCAL; -- C_TYPE_MSG_TO_ROOT;
|
441 |
|
|
|
442 |
|
|
------------------------------------------------------------------------
|
443 |
|
|
-- Lowest priority for Tx_Output_Arbitration module
|
444 |
|
|
Constant C_LOWEST_PRIORITY : std_logic_vector (C_ARBITRATE_WIDTH-1 downto 0)
|
445 |
|
|
:= (0=>'1', OTHERS=>'0');
|
446 |
|
|
|
447 |
|
|
------------------------------------------------------------------------
|
448 |
|
|
Constant C_DECODE_BIT_TOP : integer := C_EP_AWIDTH-1; -- 15;
|
449 |
|
|
Constant C_DECODE_BIT_BOT : integer := C_DECODE_BIT_TOP-1; -- 14;
|
450 |
|
|
|
451 |
|
|
|
452 |
|
|
------------------------------------------------------------------------
|
453 |
|
|
-- Current buffer descriptor length is 8 DW.
|
454 |
|
|
Constant C_NEXT_BD_LENGTH : std_logic_vector(C_TLP_FLD_WIDTH_OF_LENG+1 downto 0)
|
455 |
|
|
:= CONV_STD_LOGIC_VECTOR(8*4, C_TLP_FLD_WIDTH_OF_LENG+2);
|
456 |
|
|
|
457 |
|
|
-- Maximum 8 DW for the CplD carrying next BDA
|
458 |
|
|
Constant C_NEXT_BD_LENG_MSB : integer := 3;
|
459 |
|
|
|
460 |
|
|
------------------------------------------------------------------------
|
461 |
|
|
-- To determine the max.size parameters, 6 bits are used.
|
462 |
|
|
Constant C_MAXSIZE_FLD_BIT_TOP : integer := C_TLP_FLD_WIDTH_OF_LENG +2;
|
463 |
|
|
Constant C_MAXSIZE_FLD_BIT_BOT : integer := 7;
|
464 |
|
|
|
465 |
|
|
|
466 |
|
|
-- DDR commands: RASn-CASn-WEn
|
467 |
|
|
Constant CMD_NOP : std_logic_vector(2 downto 0) := "111";
|
468 |
|
|
Constant CMD_LMR : std_logic_vector(2 downto 0) := "000";
|
469 |
|
|
Constant CMD_ACT : std_logic_vector(2 downto 0) := "011";
|
470 |
|
|
Constant CMD_READ : std_logic_vector(2 downto 0) := "101";
|
471 |
|
|
Constant CMD_WRITE : std_logic_vector(2 downto 0) := "100";
|
472 |
|
|
Constant CMD_PRECH : std_logic_vector(2 downto 0) := "010";
|
473 |
|
|
Constant CMD_BTERM : std_logic_vector(2 downto 0) := "110";
|
474 |
|
|
Constant CMD_AREF : std_logic_vector(2 downto 0) := "001";
|
475 |
|
|
|
476 |
|
|
|
477 |
|
|
------------------------------------------------------------------------
|
478 |
|
|
-- Time-out counter width
|
479 |
|
|
Constant C_TOUT_WIDTH : integer := 32;
|
480 |
|
|
|
481 |
|
|
-- Bottom bit for determining time-out
|
482 |
|
|
Constant CBIT_TOUT_BOT : integer := 16;
|
483 |
|
|
|
484 |
|
|
-- Time-out value
|
485 |
|
|
Constant C_TIME_OUT_VALUE : std_logic_vector(C_TOUT_WIDTH-1 downto CBIT_TOUT_BOT)
|
486 |
|
|
-- := (OTHERS=>'1' ); -- Maximum value (-1)
|
487 |
|
|
:= (24=>'1', OTHERS=>'0' );
|
488 |
|
|
|
489 |
|
|
----------------------------------------------------------------------------------
|
490 |
|
|
Constant C_REGS_BASE_ADDR : std_logic_vector(C_EP_AWIDTH-1 downto 0)
|
491 |
|
|
:= (C_DECODE_BIT_TOP => '0'
|
492 |
|
|
, C_DECODE_BIT_BOT => '0'
|
493 |
|
|
, OTHERS => '0' );
|
494 |
|
|
|
495 |
|
|
Constant C_BRAM_BASE_ADDR : std_logic_vector(C_EP_AWIDTH-1 downto 0)
|
496 |
|
|
:= (C_DECODE_BIT_TOP => '1'
|
497 |
|
|
, C_DECODE_BIT_BOT => '0'
|
498 |
|
|
, OTHERS => '0' );
|
499 |
|
|
|
500 |
|
|
Constant C_FIFO_BASE_ADDR : std_logic_vector(C_EP_AWIDTH-1 downto 0)
|
501 |
|
|
:= (C_DECODE_BIT_TOP => '0'
|
502 |
|
|
, C_DECODE_BIT_BOT => '0'
|
503 |
|
|
, OTHERS => '0' );
|
504 |
|
|
|
505 |
|
|
|
506 |
|
|
----------------------------------------------------------------------------------
|
507 |
|
|
-- Constant CINT_ADDR_TXFIFO_DATA : integer := 4;
|
508 |
|
|
-- Constant CINT_ADDR_TXFIFO_CTRL : integer := 6;
|
509 |
|
|
-- Constant CINT_ADDR_TXFIFO_STA : integer := 6;
|
510 |
|
|
--
|
511 |
|
|
-- Constant CINT_ADDR_RXFIFO_DATA : integer := 8;
|
512 |
|
|
-- Constant CINT_ADDR_RXFIFO_CTRL : integer := 10;
|
513 |
|
|
-- Constant CINT_ADDR_RXFIFO_STA : integer := 10;
|
514 |
|
|
|
515 |
|
|
Constant CINT_REGS_SPACE_BAR : integer := 0;
|
516 |
|
|
Constant CINT_FIFO_SPACE_BAR : integer := 2;
|
517 |
|
|
Constant CINT_BRAM_SPACE_BAR : integer := 3;
|
518 |
|
|
Constant CINT_DDR_SPACE_BAR : integer := 1;
|
519 |
|
|
------------------------------------------------------------------------
|
520 |
|
|
|
521 |
|
|
|
522 |
|
|
-- -- Default channel buffer word for CplD
|
523 |
|
|
-- Constant C_DEF_CPLD_WORD : std_logic_vector(C_DBUS_WIDTH-1 downto 0)
|
524 |
|
|
-- :=X"CA000000";
|
525 |
|
|
|
526 |
|
|
----------------------------------------------------------------------------------
|
527 |
|
|
-- 1st word of MRd, for requesting the next descriptor
|
528 |
|
|
-- Constant C_MRD_HEAD0_WORD : std_logic_vector(C_DBUS_WIDTH-1 downto 0)
|
529 |
|
|
-- := X"80000000";
|
530 |
|
|
Constant C_TLP_HAS_DATA : std_logic
|
531 |
|
|
:= '1';
|
532 |
|
|
Constant C_TLP_HAS_NO_DATA : std_logic
|
533 |
|
|
:= '0';
|
534 |
|
|
Constant C_TLP_3DW_HEADER : std_logic
|
535 |
|
|
:= '0';
|
536 |
|
|
Constant C_TLP_4DW_HEADER : std_logic
|
537 |
|
|
:= '1';
|
538 |
|
|
|
539 |
|
|
------------------------------------------------------------------------
|
540 |
|
|
Constant C_TLP_TYPE_IS_MRD_H3 : std_logic_vector(3 downto 0)
|
541 |
|
|
:= "1000";
|
542 |
|
|
Constant C_TLP_TYPE_IS_MRDLK_H3 : std_logic_vector(3 downto 0)
|
543 |
|
|
:= "0100";
|
544 |
|
|
Constant C_TLP_TYPE_IS_MRD_H4 : std_logic_vector(3 downto 0)
|
545 |
|
|
:= "0010";
|
546 |
|
|
Constant C_TLP_TYPE_IS_MRDLK_H4 : std_logic_vector(3 downto 0)
|
547 |
|
|
:= "0001";
|
548 |
|
|
|
549 |
|
|
Constant C_TLP_TYPE_IS_MWR_H3 : std_logic_vector(1 downto 0)
|
550 |
|
|
:= "10";
|
551 |
|
|
Constant C_TLP_TYPE_IS_MWR_H4 : std_logic_vector(1 downto 0)
|
552 |
|
|
:= "01";
|
553 |
|
|
|
554 |
|
|
Constant C_TLP_TYPE_IS_CPLD : std_logic_vector(3 downto 0)
|
555 |
|
|
:= "1000";
|
556 |
|
|
Constant C_TLP_TYPE_IS_CPL : std_logic_vector(3 downto 0)
|
557 |
|
|
:= "0100";
|
558 |
|
|
Constant C_TLP_TYPE_IS_CPLDLK : std_logic_vector(3 downto 0)
|
559 |
|
|
:= "0010";
|
560 |
|
|
Constant C_TLP_TYPE_IS_CPLLK : std_logic_vector(3 downto 0)
|
561 |
|
|
:= "0001";
|
562 |
|
|
|
563 |
|
|
------------------------------------------------------------------------
|
564 |
|
|
-- Maximal number of Interrupts
|
565 |
|
|
Constant C_NUM_OF_INTERRUPTS : integer := 16;
|
566 |
|
|
|
567 |
|
|
|
568 |
|
|
------------------------------------------------------------------------
|
569 |
|
|
-- Minimal register set
|
570 |
|
|
Constant CINT_ADDR_VERSION : integer := 0;
|
571 |
|
|
|
572 |
|
|
Constant CINT_ADDR_IRQ_STAT : integer := 2;
|
573 |
|
|
|
574 |
|
|
-- IRQ Enable. Write '1' turns on the interrupt, '0' masks.
|
575 |
|
|
|
576 |
|
|
Constant CINT_ADDR_IRQ_EN : integer := 4;
|
577 |
|
|
|
578 |
|
|
Constant CINT_ADDR_ERROR : integer := 6; -- unused
|
579 |
|
|
|
580 |
|
|
Constant CINT_ADDR_STATUS : integer := 8;
|
581 |
|
|
|
582 |
|
|
Constant CINT_ADDR_CONTROL : integer := 10;
|
583 |
|
|
|
584 |
|
|
-- Upstream DMA channel Constants
|
585 |
|
|
Constant CINT_ADDR_DMA_US_PAH : integer := 11;
|
586 |
|
|
|
587 |
|
|
Constant CINT_ADDR_DMA_US_PAL : integer := 12;
|
588 |
|
|
|
589 |
|
|
Constant CINT_ADDR_DMA_US_HAH : integer := 13;
|
590 |
|
|
|
591 |
|
|
Constant CINT_ADDR_DMA_US_HAL : integer := 14;
|
592 |
|
|
|
593 |
|
|
Constant CINT_ADDR_DMA_US_BDAH : integer := 15;
|
594 |
|
|
|
595 |
|
|
Constant CINT_ADDR_DMA_US_BDAL : integer := 16;
|
596 |
|
|
|
597 |
|
|
Constant CINT_ADDR_DMA_US_LENG : integer := 17;
|
598 |
|
|
|
599 |
|
|
Constant CINT_ADDR_DMA_US_CTRL : integer := 18;
|
600 |
|
|
|
601 |
|
|
Constant CINT_ADDR_DMA_US_STA : integer := 19;
|
602 |
|
|
|
603 |
|
|
|
604 |
|
|
-- Downstream DMA channel Constants
|
605 |
|
|
Constant CINT_ADDR_DMA_DS_PAH : integer := 20;
|
606 |
|
|
|
607 |
|
|
Constant CINT_ADDR_DMA_DS_PAL : integer := 21;
|
608 |
|
|
|
609 |
|
|
Constant CINT_ADDR_DMA_DS_HAH : integer := 22;
|
610 |
|
|
|
611 |
|
|
Constant CINT_ADDR_DMA_DS_HAL : integer := 23;
|
612 |
|
|
|
613 |
|
|
Constant CINT_ADDR_DMA_DS_BDAH : integer := 24;
|
614 |
|
|
|
615 |
|
|
Constant CINT_ADDR_DMA_DS_BDAL : integer := 25;
|
616 |
|
|
|
617 |
|
|
Constant CINT_ADDR_DMA_DS_LENG : integer := 26;
|
618 |
|
|
|
619 |
|
|
Constant CINT_ADDR_DMA_DS_CTRL : integer := 27;
|
620 |
|
|
|
621 |
|
|
Constant CINT_ADDR_DMA_DS_STA : integer := 28;
|
622 |
|
|
|
623 |
|
|
|
624 |
|
|
-------- Address for MRd channel control
|
625 |
|
|
Constant CINT_ADDR_MRD_CTRL : integer := 29;
|
626 |
|
|
|
627 |
|
|
-------- Address for Tx module control
|
628 |
|
|
Constant CINT_ADDR_TX_CTRL : integer := 30;
|
629 |
|
|
|
630 |
|
|
-------- Address for ICAP access
|
631 |
|
|
Constant CINT_ADDR_ICAP : integer := 31;
|
632 |
|
|
|
633 |
|
|
|
634 |
|
|
|
635 |
|
|
-------- Address of Interrupt Generator Control (W)
|
636 |
|
|
Constant CINT_ADDR_IG_CONTROL : integer := 32;
|
637 |
|
|
|
638 |
|
|
-------- Address of Interrupt Generator Latency (W+R)
|
639 |
|
|
Constant CINT_ADDR_IG_LATENCY : integer := 33;
|
640 |
|
|
|
641 |
|
|
-------- Address of Interrupt Generator Assert Number (R)
|
642 |
|
|
Constant CINT_ADDR_IG_NUM_ASSERT : integer := 34;
|
643 |
|
|
|
644 |
|
|
-------- Address of Interrupt Generator Deassert Number (R)
|
645 |
|
|
Constant CINT_ADDR_IG_NUM_DEASSERT : integer := 35;
|
646 |
|
|
|
647 |
|
|
|
648 |
|
|
-------- Event Buffer FIFO status (R) + control (W)
|
649 |
|
|
Constant CINT_ADDR_EB_STACON : integer := 36;
|
650 |
|
|
|
651 |
|
|
-------- Upstream DMA transferred byte count (R)
|
652 |
|
|
Constant CINT_ADDR_US_TRANSF_BC : integer := 37;
|
653 |
|
|
-------- Downstream DMA transferred byte count (R)
|
654 |
|
|
Constant CINT_ADDR_DS_TRANSF_BC : integer := 38;
|
655 |
|
|
|
656 |
|
|
-------- DCB protocol link status (R) + control (W)
|
657 |
|
|
Constant CINT_ADDR_PROTOCOL_STACON : integer := 39;
|
658 |
|
|
|
659 |
|
|
-------- CTL class register rx(R) + tx (W)
|
660 |
|
|
Constant CINT_ADDR_CTL_CLASS : integer := 40;
|
661 |
|
|
|
662 |
|
|
-------- DLM class register rx(R) + tx (W)
|
663 |
|
|
Constant CINT_ADDR_DLM_CLASS : integer := 41;
|
664 |
|
|
|
665 |
|
|
-------- Data generator control register (W)
|
666 |
|
|
Constant CINT_ADDR_DG_CTRL : integer := 42;
|
667 |
|
|
|
668 |
|
|
-------- Traffice classes status (R)
|
669 |
|
|
Constant CINT_ADDR_TC_STATUS : integer := 43;
|
670 |
|
|
|
671 |
|
|
------------------------------------------------------------------------
|
672 |
|
|
-- Number of registers
|
673 |
|
|
Constant C_NUM_OF_ADDRESSES : integer := 44;
|
674 |
|
|
--
|
675 |
|
|
------------------------------------------------------------------------
|
676 |
|
|
|
677 |
|
|
|
678 |
|
|
-- ----------------------------------------------------------------------
|
679 |
|
|
-- Bit definitions of the Control register for DMA channels
|
680 |
|
|
--
|
681 |
|
|
Constant CINT_BIT_DMA_CTRL_VALID : integer := 25;
|
682 |
|
|
Constant CINT_BIT_DMA_CTRL_LAST : integer := 24;
|
683 |
|
|
Constant CINT_BIT_DMA_CTRL_UPA : integer := 20;
|
684 |
|
|
Constant CINT_BIT_DMA_CTRL_AINC : integer := 15;
|
685 |
|
|
Constant CINT_BIT_DMA_CTRL_END : integer := 08;
|
686 |
|
|
|
687 |
|
|
-- Bit range of BAR field in DMA Control register
|
688 |
|
|
Constant CINT_BIT_DMA_CTRL_BAR_TOP : integer := 18;
|
689 |
|
|
Constant CINT_BIT_DMA_CTRL_BAR_BOT : integer := 16;
|
690 |
|
|
|
691 |
|
|
|
692 |
|
|
-- Default DMA Control register value
|
693 |
|
|
-- Constant C_DEF_DMA_CTRL_WORD : std_logic_vector(C_DBUS_WIDTH-1 downto 0)
|
694 |
|
|
Constant C_DEF_DMA_CTRL_WORD : std_logic_vector(C_DBUS_WIDTH-1 downto 0)
|
695 |
|
|
:= (CINT_BIT_DMA_CTRL_VALID => '1' ,
|
696 |
|
|
CINT_BIT_DMA_CTRL_END => '1' ,
|
697 |
|
|
OTHERS => '0'
|
698 |
|
|
);
|
699 |
|
|
|
700 |
|
|
------------------------------------------------------------------------
|
701 |
|
|
Constant C_CHANNEL_RST_BITS : std_logic_vector(C_FEAT_BITS_WIDTH-1 downto 0)
|
702 |
|
|
:= X"0A";
|
703 |
|
|
|
704 |
|
|
------------------------------------------------------------------------
|
705 |
|
|
Constant C_HOST_ICLR_BITS : std_logic_vector(C_FEAT_BITS_WIDTH-1 downto 0)
|
706 |
|
|
:= X"F0";
|
707 |
|
|
|
708 |
|
|
----------------------------------------------------------------------------------
|
709 |
|
|
-- Initial MWr Tag for upstream DMA
|
710 |
|
|
Constant C_TAG0_DMA_US_MWR : std_logic_vector(C_TAG_WIDTH-1 downto 0)
|
711 |
|
|
:= X"D0";
|
712 |
|
|
|
713 |
|
|
-- Initial MRd Tag for upstream DMA descriptor
|
714 |
|
|
Constant C_TAG0_DMA_USB : std_logic_vector(C_TAG_WIDTH-1 downto 0)
|
715 |
|
|
:= X"E0";
|
716 |
|
|
|
717 |
|
|
-- Initial MRd Tag for downstream DMA descriptor
|
718 |
|
|
Constant C_TAG0_DMA_DSB : std_logic_vector(C_TAG_WIDTH-1 downto 0)
|
719 |
|
|
:= X"C0";
|
720 |
|
|
|
721 |
|
|
-- Initial Msg Tag Hihger 4 bits for interrupt
|
722 |
|
|
Constant C_MSG_TAG_HI : std_logic_vector( 3 downto 0)
|
723 |
|
|
:= X"F";
|
724 |
|
|
-- Msg code for IntA (fixed by PCIe)
|
725 |
|
|
Constant C_MSGCODE_INTA : std_logic_vector( 7 downto 0)
|
726 |
|
|
:= X"20";
|
727 |
|
|
-- Msg code for #IntA (fixed by PCIe)
|
728 |
|
|
Constant C_MSGCODE_INTA_N : std_logic_vector( 7 downto 0)
|
729 |
|
|
:= X"24";
|
730 |
|
|
|
731 |
|
|
----------------------------------------------------------------------------------
|
732 |
|
|
-- DMA status bit definition
|
733 |
|
|
Constant CINT_BIT_DMA_STAT_NALIGN : integer := 7;
|
734 |
|
|
Constant CINT_BIT_DMA_STAT_TIMEOUT : integer := 4;
|
735 |
|
|
Constant CINT_BIT_DMA_STAT_BDANULL : integer := 3;
|
736 |
|
|
Constant CINT_BIT_DMA_STAT_BUSY : integer := 1;
|
737 |
|
|
Constant CINT_BIT_DMA_STAT_DONE : integer := 0;
|
738 |
|
|
|
739 |
|
|
-- Bit definition in interrup status register (ISR)
|
740 |
|
|
Constant CINT_BIT_US_DONE_IN_ISR : integer := 0;
|
741 |
|
|
Constant CINT_BIT_DS_DONE_IN_ISR : integer := 1;
|
742 |
|
|
|
743 |
|
|
Constant CINT_BIT_INTGEN_IN_ISR : integer := 2;
|
744 |
|
|
Constant CINT_BIT_DGEN_IN_ISR : integer := 3;
|
745 |
|
|
|
746 |
|
|
Constant CINT_BIT_USTOUT_IN_ISR : integer := 4;
|
747 |
|
|
Constant CINT_BIT_DSTOUT_IN_ISR : integer := 5;
|
748 |
|
|
|
749 |
|
|
Constant CINT_BIT_DAQ_IN_ISR : integer := 6;
|
750 |
|
|
Constant CINT_BIT_CTL_IN_ISR : integer := 7;
|
751 |
|
|
Constant CINT_BIT_DLM_IN_ISR : integer := 8;
|
752 |
|
|
|
753 |
|
|
-- The Time-out bits in System Error Register (SER)
|
754 |
|
|
Constant CINT_BIT_TX_TOUT_IN_SER : integer := 18;
|
755 |
|
|
Constant CINT_BIT_EB_TOUT_IN_SER : integer := 19;
|
756 |
|
|
Constant CINT_BIT_EB_OVERWRITTEN : integer := 20;
|
757 |
|
|
|
758 |
|
|
-- The separate RST bit in DG_CTRL register
|
759 |
|
|
Constant CINT_BIT_DG_RST : integer := 12;
|
760 |
|
|
|
761 |
|
|
-- The MASK bit in DG_CTRL register
|
762 |
|
|
Constant CINT_BIT_DG_MASK : integer := 8;
|
763 |
|
|
|
764 |
|
|
-- The BUSY bit in DG_CTRL register
|
765 |
|
|
Constant CINT_BIT_DG_BUSY : integer := 1;
|
766 |
|
|
|
767 |
|
|
-- The AVAIL bit in DG_CTRL register
|
768 |
|
|
Constant CINT_BIT_DG_AVAIL : integer := 0;
|
769 |
|
|
|
770 |
|
|
-- Bit definition of msg routing method in General Control Register (GCR)
|
771 |
|
|
Constant C_GCR_MSG_ROUT_BIT_BOT : integer := 0;
|
772 |
|
|
Constant C_GCR_MSG_ROUT_BIT_TOP : integer := 2;
|
773 |
|
|
|
774 |
|
|
-- Bit definition of ICAP Busy in global status register (GSR)
|
775 |
|
|
Constant CINT_BIT_ICAP_BUSY_IN_GSR : integer := 4;
|
776 |
|
|
|
777 |
|
|
-- Bit definition of Data Generator available in global status register (GSR)
|
778 |
|
|
Constant CINT_BIT_DG_AVAIL_IN_GSR : integer := 5;
|
779 |
|
|
|
780 |
|
|
-- Bit definition of DCB link_active in global status register (GSR)
|
781 |
|
|
Constant CINT_BIT_LINK_ACT_IN_GSR : integer := 6;
|
782 |
|
|
|
783 |
|
|
|
784 |
|
|
-- Bit range of link width in GSR
|
785 |
|
|
Constant CINT_BIT_LWIDTH_IN_GSR_BOT : integer := 10; -- 16;
|
786 |
|
|
Constant CINT_BIT_LWIDTH_IN_GSR_TOP : integer := 15; -- 21;
|
787 |
|
|
|
788 |
|
|
|
789 |
|
|
----------------------------------------------------------------------------------
|
790 |
|
|
-- Carry bit, only for better timing, used to divide 32-bit add into 2 stages
|
791 |
|
|
Constant CBIT_CARRY : integer := 16;
|
792 |
|
|
|
793 |
|
|
----------------------------------------------------------------------------------
|
794 |
|
|
-- Zero and -1 constants for different dimensions
|
795 |
|
|
--
|
796 |
|
|
Constant C_ALL_ZEROS : std_logic_vector(255 downto 0)
|
797 |
|
|
:= (OTHERS=>'0');
|
798 |
|
|
Constant C_ALL_ONES : std_logic_vector(255 downto 0)
|
799 |
|
|
:= (OTHERS=>'1');
|
800 |
|
|
|
801 |
|
|
|
802 |
|
|
----------------------------------------------------------------------------------
|
803 |
|
|
-- Implement interrupt generator (IG)
|
804 |
|
|
constant IMP_INT_GENERATOR : boolean := FALSE;
|
805 |
|
|
|
806 |
|
|
-- interrupt type: cfg(aka legacy) or MSI
|
807 |
|
|
constant USE_CFG_INTERRUPT : boolean := FALSE;
|
808 |
|
|
|
809 |
|
|
|
810 |
|
|
------------------------------------------------------------------------------------
|
811 |
|
|
---- ------------ Author ID
|
812 |
|
|
constant AUTHOR_UNKNOWN : std_logic_vector(4-1 downto 0) := X"0";
|
813 |
|
|
constant AUTHOR_AKUGEL : std_logic_vector(4-1 downto 0) := X"1";
|
814 |
|
|
constant AUTHOR_WGAO : std_logic_vector(4-1 downto 0) := X"2";
|
815 |
|
|
----------------------------------------------------------------------------------
|
816 |
|
|
|
817 |
|
|
---- ------------ design ID ---------------------
|
818 |
|
|
---- design id now contains a version: upper 8 bits, a major revision: next 8 bits,
|
819 |
|
|
---- and author code: next 4 bits and a minor revision: lower 12 bits
|
820 |
|
|
---- keep the autor file seperate and don't submit to CVS
|
821 |
|
|
----
|
822 |
|
|
constant DESIGN_VERSION : std_logic_vector( 8-1 downto 0) := X"03";
|
823 |
|
|
constant DESIGN_MAJOR_REVISION : std_logic_vector( 8-1 downto 0) := X"01";
|
824 |
|
|
constant DESIGN_MINOR_REVISION : std_logic_vector(12-1 downto 0) := X"001";
|
825 |
|
|
constant C_DESIGN_ID : std_logic_vector(64-1 downto 0)
|
826 |
|
|
:= X"00000000"
|
827 |
|
|
& DESIGN_VERSION
|
828 |
|
|
& DESIGN_MAJOR_REVISION
|
829 |
|
|
& AUTHOR_WGAO
|
830 |
|
|
& DESIGN_MINOR_REVISION
|
831 |
|
|
;
|
832 |
|
|
|
833 |
|
|
|
834 |
|
|
----------------------------------------------------------------------------------
|
835 |
|
|
-- Function to invert endian for 32-bit data
|
836 |
|
|
--
|
837 |
|
|
function Endian_Invert_32 (Word_in: std_logic_vector) return std_logic_vector;
|
838 |
|
|
function Endian_Invert_64 (Word_in: std_logic_vector(64-1 downto 0)) return std_logic_vector;
|
839 |
|
|
|
840 |
|
|
|
841 |
|
|
----------------------------------------------------------------------------------
|
842 |
|
|
----------------------------------------------------------------------------------
|
843 |
|
|
-- revision log
|
844 |
|
|
-- 2007-05-30: AK - abbPackage added, address map changed
|
845 |
|
|
-- 2007-06-12: WGao - C_DEF_DMA_CTRL_WORD added,
|
846 |
|
|
-- DMA Control word bit definition added,
|
847 |
|
|
-- Function Endian_Invert_32 added.
|
848 |
|
|
-- CINT_ADDR_MRD_CTRL and CINT_ADDR_CPLD_CTRL changed,
|
849 |
|
|
-- CINT_ADDR_US_SAH and CINT_ADDR_DS_SAH removed.
|
850 |
|
|
-- 2007-07-16: AK - dma status bits added
|
851 |
|
|
|
852 |
|
|
|
853 |
|
|
end abb64Package;
|
854 |
|
|
|
855 |
|
|
|
856 |
|
|
package body abb64Package is
|
857 |
|
|
|
858 |
|
|
-- ------------------------------------------------------------------------------------------
|
859 |
|
|
-- Function to invert bytewise endian for 32-bit data
|
860 |
|
|
-- ------------------------------------------------------------------------------------------
|
861 |
|
|
function Endian_Invert_32 (Word_in: std_logic_vector) return std_logic_vector is
|
862 |
|
|
begin
|
863 |
|
|
return Word_in(7 downto 0)&Word_in(15 downto 8)&Word_in(23 downto 16)&Word_in(31 downto 24);
|
864 |
|
|
end Endian_Invert_32;
|
865 |
|
|
|
866 |
|
|
-- ------------------------------------------------------------------------------------------
|
867 |
|
|
-- Function to invert bytewise endian for 64-bit data
|
868 |
|
|
-- ------------------------------------------------------------------------------------------
|
869 |
|
|
function Endian_Invert_64 (Word_in: std_logic_vector(64-1 downto 0)) return std_logic_vector is
|
870 |
|
|
begin
|
871 |
|
|
return Word_in(39 downto 32)&Word_in(47 downto 40)&Word_in(55 downto 48)&Word_in(63 downto 56)
|
872 |
|
|
& Word_in(7 downto 0)&Word_in(15 downto 8)&Word_in(23 downto 16)&Word_in(31 downto 24);
|
873 |
|
|
end Endian_Invert_64;
|
874 |
|
|
|
875 |
|
|
end abb64Package;
|