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weng_ziti |
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-- Company: ziti, Uni. HD
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-- Engineer: wgao
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--
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-- Design Name:
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-- Module Name: rx_CplD_Transact - Behavioral
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-- Project Name:
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-- Target Devices:
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-- Tool versions:
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-- Description:
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--
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-- Dependencies:
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--
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-- Revision 1.00 - first release. 14.12.2006
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--
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-- Additional Comments:
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--
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----------------------------------------------------------------------------------
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library IEEE;
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use IEEE.STD_LOGIC_1164.ALL;
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use IEEE.STD_LOGIC_ARITH.ALL;
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use IEEE.STD_LOGIC_UNSIGNED.ALL;
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library work;
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use work.abb64Package.all;
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-- Uncomment the following library declaration if instantiating
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-- any Xilinx primitives in this code.
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--library UNISIM;
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--use UNISIM.VComponents.all;
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entity rx_CplD_Transact is
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port (
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-- Transaction receive interface
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trn_rsof_n : IN std_logic;
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trn_reof_n : IN std_logic;
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trn_rd : IN std_logic_vector(C_DBUS_WIDTH-1 downto 0);
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trn_rrem_n : IN std_logic_vector(C_DBUS_WIDTH/8-1 downto 0);
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trn_rerrfwd_n : IN std_logic;
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trn_rsrc_rdy_n : IN std_logic;
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trn_rdst_rdy_n : IN std_logic; -- !!
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trn_rsrc_dsc_n : IN std_logic;
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trn_rbar_hit_n : IN std_logic_vector(C_BAR_NUMBER-1 downto 0);
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-- trn_rfc_ph_av : IN std_logic_vector(7 downto 0);
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-- trn_rfc_pd_av : IN std_logic_vector(11 downto 0);
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-- trn_rfc_nph_av : IN std_logic_vector(7 downto 0);
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-- trn_rfc_npd_av : IN std_logic_vector(11 downto 0);
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-- trn_rfc_cplh_av : IN std_logic_vector(7 downto 0);
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-- trn_rfc_cpld_av : IN std_logic_vector(11 downto 0);
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CplD_Type : IN std_logic_vector(3 downto 0);
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Req_ID_Match : IN std_logic;
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usDex_Tag_Matched : IN std_logic;
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dsDex_Tag_Matched : IN std_logic;
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Tlp_has_4KB : IN std_logic;
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Tlp_has_1DW : IN std_logic;
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CplD_on_Pool : IN std_logic;
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CplD_on_EB : IN std_logic;
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CplD_is_the_Last : IN std_logic;
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CplD_Tag : IN std_logic_vector(C_TAG_WIDTH-1 downto 0);
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FC_pop : OUT std_logic;
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-- Downstream DMA transferred bytes count up
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ds_DMA_Bytes_Add : OUT std_logic;
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ds_DMA_Bytes : OUT std_logic_vector(C_TLP_FLD_WIDTH_OF_LENG+2 downto 0);
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-- Tag output to downstream DMA channel
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dsDMA_dex_Tag : OUT std_logic_vector(C_TAG_WIDTH-1 downto 0);
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-- Downstream Handshake Signals with ds Channel for Busy/Done
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Tag_Map_Clear : OUT std_logic_vector(C_TAG_MAP_WIDTH-1 downto 0);
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-- Downstream tRAM port A write request
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tRAM_weB : IN std_logic;
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tRAM_addrB : IN std_logic_vector(C_TAGRAM_AWIDTH-1 downto 0);
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tRAM_dinB : IN std_logic_vector(C_TAGRAM_DWIDTH-1 downto 0);
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-- Tag output to upstream DMA channel
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usDMA_dex_Tag : OUT std_logic_vector(C_TAG_WIDTH-1 downto 0);
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-- Event Buffer write port
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eb_FIFO_we : OUT std_logic;
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eb_FIFO_wsof : OUT std_logic;
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eb_FIFO_weof : OUT std_logic;
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eb_FIFO_din : OUT std_logic_vector(C_DBUS_WIDTH-1 downto 0);
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-- Registers Write Port
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Regs_WrEn : OUT std_logic;
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Regs_WrMask : OUT std_logic_vector(2-1 downto 0);
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Regs_WrAddr : OUT std_logic_vector(C_EP_AWIDTH-1 downto 0);
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Regs_WrDin : OUT std_logic_vector(C_DBUS_WIDTH-1 downto 0);
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-- DDR write port
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DDR_wr_sof : OUT std_logic;
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DDR_wr_eof : OUT std_logic;
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DDR_wr_v : OUT std_logic;
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DDR_wr_FA : OUT std_logic;
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DDR_wr_Shift : OUT std_logic;
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DDR_wr_Mask : OUT std_logic_vector(2-1 downto 0);
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DDR_wr_din : OUT std_logic_vector(C_DBUS_WIDTH-1 downto 0);
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DDR_wr_full : IN std_logic;
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-- Common ports
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trn_clk : IN std_logic;
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trn_reset_n : IN std_logic;
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trn_lnk_up_n : IN std_logic
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);
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end entity rx_CplD_Transact;
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architecture Behavioral of rx_CplD_Transact is
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type RxCplDEBStates is ( ST_EBWR_IDLE
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, ST_EBWR_TAG
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, ST_EBWR_DATA
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);
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signal EB_Write_State : RxCplDEBStates;
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type RxCplDTrnStates is ( ST_CplD_RESET
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, ST_CplD_IDLE
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-- , ST_Cpl_HEAD1 -- Cpl Header #1 (not used)
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-- , ST_CplD_HEAD1 -- CplD Header #1
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, ST_Cpl_HEAD2 -- Cpl Header #2 (not used)
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, ST_CplD_HEAD2 -- CplD Header #2
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, ST_CplD_AFetch_Special --
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, ST_CplD_AFetch_Special_Tail --
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, ST_CplD_AFetch -- Target address fetch from tRAM/registers
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, ST_CplD_AFetch_THROTTLE -- Target address fetch throttled
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, ST_CplD_ONLY_1DW -- Current CplD has only 1 DW
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-- , ST_CplD_ONLY_1DW_THROTTLE -- Current CplD has only 1 DW, throttled
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, ST_CplD_1ST_DATA -- 1st data payload of the CplD
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, ST_CplD_1ST_DATA_THROTTLE -- 1st data payload of the CplD
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, ST_CplD_DATA -- data receiving
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, ST_CplD_DATA_THROTTLE -- data receiving throttled
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, ST_CplD_LAST_DATA -- Last data payload of the CplD
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);
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-- State variables
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signal RxCplDTrn_NextState : RxCplDTrnStates;
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signal RxCplDTrn_State : RxCplDTrnStates;
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-- State delay
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signal RxCplDTrn_State_r1 : RxCplDTrnStates;
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signal RxCplDTrn_State_r2 : RxCplDTrnStates;
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signal CplD_State_is_AFetch : std_logic;
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signal CplD_State_is_AFetch_r1 : std_logic;
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signal CplD_State_is_after_AFetch : std_logic;
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signal CplD_State_is_after_AFetch_r1 : std_logic;
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-- Shifted-glued payload
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signal hybrid_rd : std_logic_vector (C_DBUS_WIDTH-1 downto 0);
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-- trn_rx stubs
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signal trn_rd_i : std_logic_vector (C_DBUS_WIDTH-1 downto 0);
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signal trn_rd_r1 : std_logic_vector (C_DBUS_WIDTH-1 downto 0);
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signal trn_rd_r2 : std_logic_vector (C_DBUS_WIDTH-1 downto 0);
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signal trn_rd_r3 : std_logic_vector (C_DBUS_WIDTH-1 downto 0);
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signal trn_rd_r4 : std_logic_vector (C_DBUS_WIDTH-1 downto 0);
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-- trn_rd_* in little endian
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signal trn_rd_Little : std_logic_vector (C_DBUS_WIDTH-1 downto 0);
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signal trn_rd_Little_r1 : std_logic_vector (C_DBUS_WIDTH-1 downto 0);
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signal trn_rd_Little_r2 : std_logic_vector (C_DBUS_WIDTH-1 downto 0);
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signal trn_rd_Little_r3 : std_logic_vector (C_DBUS_WIDTH-1 downto 0);
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signal trn_rd_Little_r4 : std_logic_vector (C_DBUS_WIDTH-1 downto 0);
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-- signal trn_rbar_hit_n_i : std_logic_vector(C_BAR_NUMBER-1 downto 0);
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signal trn_rerrfwd_n_i : std_logic;
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signal trn_rsrc_dsc_n_i : std_logic;
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signal trn_rsof_n_i : std_logic;
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signal trn_rsof_n_r1 : std_logic;
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signal trn_rsof_n_r2 : std_logic;
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signal trn_rsof_n_r3 : std_logic;
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signal trn_rsof_n_r4 : std_logic;
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signal trn_reof_n_i : std_logic;
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signal trn_reof_n_r1 : std_logic;
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signal trn_reof_n_r2 : std_logic;
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signal trn_reof_n_r3 : std_logic;
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signal trn_reof_n_r4 : std_logic;
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-- signal Tlp_has_4KB_r1 : std_logic;
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signal trn_rrem_n_i : std_logic_vector(C_DBUS_WIDTH/8-1 downto 0);
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signal trn_rrem_n_r1 : std_logic_vector(C_DBUS_WIDTH/8-1 downto 0);
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signal trn_rrem_n_r2 : std_logic_vector(C_DBUS_WIDTH/8-1 downto 0);
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signal trn_rrem_n_r3 : std_logic_vector(C_DBUS_WIDTH/8-1 downto 0);
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signal trn_rrem_n_r4 : std_logic_vector(C_DBUS_WIDTH/8-1 downto 0);
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-- Whether address increases
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signal Addr_Inc : std_logic;
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-- Spaces hit
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-- signal FIFO_Space_Hit : std_logic;
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signal DDR_Space_Hit : std_logic;
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-- DDR write port
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signal DDR_wr_sof_i : std_logic;
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signal DDR_wr_eof_i : std_logic;
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signal DDR_wr_v_i : std_logic;
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signal DDR_wr_FA_i : std_logic;
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signal DDR_wr_void : std_logic;
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signal DDR_wr_Shift_i : std_logic;
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signal DDR_wr_Mask_i : std_logic_vector(2-1 downto 0);
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signal DDR_wr_din_i : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
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signal DDR_wr_full_i : std_logic;
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-- Event Buffer write port
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signal eb_FIFO_we_i : std_logic;
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signal eb_FIFO_wsof_i : std_logic;
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signal eb_FIFO_weof_i : std_logic;
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signal eb_FIFO_sof_marker : std_logic;
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signal eb_FIFO_din_i : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
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-- Register write port
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signal Regs_WrEn_i : std_logic;
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signal Regs_WrMask_i : std_logic_vector(2-1 downto 0);
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signal Regs_WrAddr_i : std_logic_vector(C_EP_AWIDTH-1 downto 0);
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signal Regs_WrDin_i : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
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-- Calculation @ trn_rsof_n=0
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signal Dex_CplD_Illegal : std_logic;
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signal Reg_WrAddr_if_last_us: std_logic_vector(C_EP_AWIDTH-1 downto 0);
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signal Reg_WrAddr_if_last_ds: std_logic_vector(C_EP_AWIDTH-1 downto 0);
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-- Flow control signals
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signal trn_rdst_rdy_n_i : std_logic;
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signal trn_rsrc_rdy_n_i : std_logic;
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signal trn_rsrc_rdy_n_r1 : std_logic;
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signal trn_rsrc_rdy_n_r2 : std_logic;
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signal trn_rsrc_rdy_n_r3 : std_logic;
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signal trn_rsrc_rdy_n_r4 : std_logic;
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signal trn_rx_throttle : std_logic;
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signal trn_rx_throttle_r1 : std_logic;
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signal trn_rx_throttle_r2 : std_logic;
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signal trn_rx_throttle_r3 : std_logic;
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signal trn_rx_throttle_r4 : std_logic;
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-- Downstream DMA transferred bytes count up
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signal ds_DMA_Bytes_Add_i : std_logic;
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signal ds_DMA_Bytes_i : std_logic_vector(C_TLP_FLD_WIDTH_OF_LENG+2 downto 0);
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signal CplD_is_Payloaded : std_logic;
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signal TLP_is_not_CplD : std_logic;
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signal TLP_is_not_CplD_r1 : std_logic;
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signal TLP_is_not_CplD_r2 : std_logic;
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signal TLP_is_not_CplD_r3 : std_logic;
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signal TLP_is_not_CplD_r4 : std_logic;
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signal TLP_is_not_CplD_r5 : std_logic;
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-- Alias for header resolution
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signal CplD_Length : std_logic_vector(C_TLP_FLD_WIDTH_OF_LENG downto 0);
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signal CplD_Leng_in_Bytes : std_logic_vector(C_DBUS_WIDTH/2-1 downto 0);
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signal CplD_Leng_in_Bytes_r1: std_logic_vector(C_DBUS_WIDTH/2-1 downto 0);
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signal CplD_Leng_in_Bytes_r2: std_logic_vector(C_DBUS_WIDTH/2-1 downto 0);
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signal CplD_is_1DW : std_logic;
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-- Small_CplD means CplD with less than 4 DW payload
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signal Small_CplD : std_logic;
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signal Small_CplD_r1 : std_logic;
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signal RegAddr_us_Dex : std_logic_vector(C_EP_AWIDTH-1 downto 0);
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signal RegAddr_ds_Dex : std_logic_vector(C_EP_AWIDTH-1 downto 0);
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signal CplD_Tag_on_Dex : std_logic;
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-- ----------------------------------------------------------------------
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signal Req_ID_Match_i : std_logic;
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signal Dex_Tag_Matched_i : std_logic;
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-- The top bit of the CplD_Tag is for distinguishing data CplD or descriptor CplD
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signal MSB_DSP_Tag : std_logic;
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signal MSB_DSP_Tag_r1 : std_logic;
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signal DSP_Tag_on_RAM : std_logic;
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signal DSP_Tag_on_RAM_r1 : std_logic;
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signal DSP_Tag_on_RAM_r2 : std_logic;
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signal DSP_Tag_on_RAM_r3 : std_logic;
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signal DSP_Tag_on_RAM_r4p : std_logic;
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signal DSP_Tag_on_FIFO : std_logic;
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-- ----------------------------------------------------------------------
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signal FC_pop_i : std_logic;
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302 |
|
|
signal Tag_Map_Clear_i : std_logic_vector(C_TAG_MAP_WIDTH-1 downto 0);
|
303 |
|
|
|
304 |
|
|
signal Local_Reset_i : std_logic;
|
305 |
|
|
|
306 |
|
|
|
307 |
|
|
-- upstream Descriptors' tags
|
308 |
|
|
signal usDMA_dex_Tag_i : std_logic_vector(C_TAG_WIDTH-1 downto 0);
|
309 |
|
|
|
310 |
|
|
-- downstream Descriptors' tags
|
311 |
|
|
signal dsDMA_dex_Tag_i : std_logic_vector(C_TAG_WIDTH-1 downto 0);
|
312 |
|
|
|
313 |
|
|
|
314 |
|
|
-- --- ------------------------------------------
|
315 |
|
|
-- --- Dual port Block Memory, used as tag RAM
|
316 |
|
|
-- component
|
317 |
|
|
-- v5tagram64x36
|
318 |
|
|
-- port (
|
319 |
|
|
-- clka : IN std_logic;
|
320 |
|
|
-- addra : IN std_logic_VECTOR(C_TAGRAM_AWIDTH-1 downto 0);
|
321 |
|
|
-- wea : IN std_logic_vector(0 downto 0);
|
322 |
|
|
-- dina : IN std_logic_VECTOR(C_TAGRAM_DWIDTH-1 downto 0);
|
323 |
|
|
-- douta : OUT std_logic_VECTOR(C_TAGRAM_DWIDTH-1 downto 0);
|
324 |
|
|
-- clkb : IN std_logic;
|
325 |
|
|
-- addrb : IN std_logic_VECTOR(C_TAGRAM_AWIDTH-1 downto 0);
|
326 |
|
|
-- web : IN std_logic_vector(0 downto 0);
|
327 |
|
|
-- dinb : IN std_logic_VECTOR(C_TAGRAM_DWIDTH-1 downto 0);
|
328 |
|
|
-- doutb : OUT std_logic_VECTOR(C_TAGRAM_DWIDTH-1 downto 0)
|
329 |
|
|
-- );
|
330 |
|
|
-- end component;
|
331 |
|
|
|
332 |
|
|
--- ------------------------------------------
|
333 |
|
|
--- Dual port Block Memory, used as tag RAM
|
334 |
|
|
component
|
335 |
|
|
FF_TagRam64x36
|
336 |
|
|
port (
|
337 |
|
|
clk : IN std_logic;
|
338 |
|
|
addra : IN std_logic_VECTOR(C_TAGRAM_AWIDTH-1 downto 0);
|
339 |
|
|
wea : IN std_logic;
|
340 |
|
|
dina : IN std_logic_VECTOR(C_TAGRAM_DWIDTH-1 downto 0);
|
341 |
|
|
douta : OUT std_logic_VECTOR(C_TAGRAM_DWIDTH-1 downto 0);
|
342 |
|
|
addrb : IN std_logic_VECTOR(C_TAGRAM_AWIDTH-1 downto 0);
|
343 |
|
|
web : IN std_logic;
|
344 |
|
|
dinb : IN std_logic_VECTOR(C_TAGRAM_DWIDTH-1 downto 0);
|
345 |
|
|
doutb : OUT std_logic_VECTOR(C_TAGRAM_DWIDTH-1 downto 0)
|
346 |
|
|
);
|
347 |
|
|
end component;
|
348 |
|
|
|
349 |
|
|
signal tRAM_wea : std_logic_vector(0 downto 0);
|
350 |
|
|
signal tRAM_addra : std_logic_vector(C_TAGRAM_AWIDTH-1 downto 0);
|
351 |
|
|
signal tRAM_dina : std_logic_vector(C_TAGRAM_DWIDTH-1 downto 0);
|
352 |
|
|
signal tRAM_doutA : std_logic_vector(C_TAGRAM_DWIDTH-1 downto 0);
|
353 |
|
|
signal tRAM_weB_i : std_logic_vector(0 downto 0);
|
354 |
|
|
|
355 |
|
|
signal tRAM_DoutA_r1 : std_logic_vector(C_TAGRAM_DWIDTH-1 downto 0);
|
356 |
|
|
signal tRAM_DoutA_r2 : std_logic_vector(C_TAGRAM_DWIDTH-1 downto 0);
|
357 |
|
|
signal tRAM_dina_aInc : std_logic_vector(C_TAGRAM_DWIDTH-1 downto 0);
|
358 |
|
|
signal tRAM_DoutA_latch : std_logic_vector(C_TAGRAM_DWIDTH-1 downto 0);
|
359 |
|
|
|
360 |
|
|
-- updates the tag RAM as soon as possible
|
361 |
|
|
signal CplD_Tag_r1 : std_logic_vector(C_TAG_WIDTH-1 downto 0);
|
362 |
|
|
signal CplD_Tag_r2 : std_logic_vector(C_TAG_WIDTH-1 downto 0);
|
363 |
|
|
signal CplD_Tag_r3 : std_logic_vector(C_TAG_WIDTH-1 downto 0);
|
364 |
|
|
signal CplD_Tag_r4 : std_logic_vector(C_TAG_WIDTH-1 downto 0);
|
365 |
|
|
signal CplD_is_the_Last_r1 : std_logic;
|
366 |
|
|
signal CplD_is_the_Last_r2 : std_logic;
|
367 |
|
|
signal Updates_tRAM : std_logic;
|
368 |
|
|
signal Updates_tRAM_r1 : std_logic;
|
369 |
|
|
signal Update_was_too_late : std_logic;
|
370 |
|
|
|
371 |
|
|
signal hazard_update : std_logic;
|
372 |
|
|
signal hazard_update_r1 : std_logic;
|
373 |
|
|
signal hazard_update_r2 : std_logic;
|
374 |
|
|
signal hazard_update_r3 : std_logic;
|
375 |
|
|
-- signal hazard_tag : std_logic_vector(C_TAG_WIDTH-1 downto 0);
|
376 |
|
|
signal curr_tag_latch : std_logic_vector(C_TAG_WIDTH-1 downto 0);
|
377 |
|
|
signal hazard_content : std_logic_vector(C_TAGRAM_DWIDTH-1 downto 0);
|
378 |
|
|
signal tag_matches_hazard : std_logic;
|
379 |
|
|
signal tag_matches_hazard_r1 : std_logic;
|
380 |
|
|
signal tag_matches_hazard_r2 : std_logic;
|
381 |
|
|
|
382 |
|
|
-- aka TLB unit
|
383 |
|
|
signal TLB_Addr : std_logic_vector(C_TAGRAM_AWIDTH-1 downto 0);
|
384 |
|
|
signal TLB_Content : std_logic_vector(C_TAGRAM_DWIDTH-1 downto 0);
|
385 |
|
|
signal TLB_cnt : std_logic_vector(4-1 downto 0);
|
386 |
|
|
signal TLB_Valid : std_logic;
|
387 |
|
|
signal TLB_Hit : std_logic;
|
388 |
|
|
|
389 |
|
|
Constant C_TLB_VALID_CNT : std_logic_vector(4-1 downto 0) := X"6";
|
390 |
|
|
|
391 |
|
|
begin
|
392 |
|
|
|
393 |
|
|
-- Event Buffer write
|
394 |
|
|
eb_FIFO_we <= eb_FIFO_we_i ;
|
395 |
|
|
eb_FIFO_wsof <= eb_FIFO_wsof_i ;
|
396 |
|
|
eb_FIFO_weof <= eb_FIFO_weof_i ;
|
397 |
|
|
eb_FIFO_din <= eb_FIFO_din_i ;
|
398 |
|
|
|
399 |
|
|
-- DDR
|
400 |
|
|
DDR_wr_sof <= DDR_wr_sof_i ;
|
401 |
|
|
DDR_wr_eof <= DDR_wr_eof_i ;
|
402 |
|
|
DDR_wr_v <= DDR_wr_v_i ;
|
403 |
|
|
DDR_wr_FA <= DDR_wr_FA_i ;
|
404 |
|
|
DDR_wr_Shift <= DDR_wr_Shift_i ;
|
405 |
|
|
DDR_wr_Mask <= DDR_wr_Mask_i ;
|
406 |
|
|
DDR_wr_din <= DDR_wr_din_i ;
|
407 |
|
|
DDR_wr_full_i <= DDR_wr_full ;
|
408 |
|
|
|
409 |
|
|
ds_DMA_Bytes_Add <= ds_DMA_Bytes_Add_i ;
|
410 |
|
|
ds_DMA_Bytes <= ds_DMA_Bytes_i ;
|
411 |
|
|
|
412 |
|
|
--
|
413 |
|
|
Tag_Map_Clear <= Tag_Map_Clear_i;
|
414 |
|
|
|
415 |
|
|
--
|
416 |
|
|
FC_pop <= FC_pop_i;
|
417 |
|
|
-- ----------------------------------------------
|
418 |
|
|
--
|
419 |
|
|
Syn_FC_pop:
|
420 |
|
|
process ( trn_clk, Local_Reset_i)
|
421 |
|
|
begin
|
422 |
|
|
if Local_Reset_i = '1' then
|
423 |
|
|
FC_pop_i <= '0';
|
424 |
|
|
elsif trn_clk'event and trn_clk = '1' then
|
425 |
|
|
FC_pop_i <= (CplD_on_Pool or CplD_on_EB)
|
426 |
|
|
and CplD_is_the_Last
|
427 |
|
|
and not MSB_DSP_Tag
|
428 |
|
|
and not trn_reof_n_i
|
429 |
|
|
and trn_reof_n_r1 -- Catch the falling edge of trn_reof_n
|
430 |
|
|
-- and not trn_rx_throttle
|
431 |
|
|
;
|
432 |
|
|
end if;
|
433 |
|
|
|
434 |
|
|
end process;
|
435 |
|
|
|
436 |
|
|
-- ----------------------------------------------
|
437 |
|
|
-- Synchronous: CplD_is_Payloaded
|
438 |
|
|
--
|
439 |
|
|
Syn_CplD_is_Payloaded:
|
440 |
|
|
process ( trn_clk, Local_Reset_i)
|
441 |
|
|
begin
|
442 |
|
|
if Local_Reset_i = '1' then
|
443 |
|
|
CplD_is_Payloaded <= '0';
|
444 |
|
|
elsif trn_clk'event and trn_clk = '1' then
|
445 |
|
|
if trn_rsof_n_i='0' and trn_rx_throttle='0' then
|
446 |
|
|
CplD_is_Payloaded <= CplD_Type(3) or CplD_Type(1);
|
447 |
|
|
else
|
448 |
|
|
CplD_is_Payloaded <= CplD_is_Payloaded;
|
449 |
|
|
end if;
|
450 |
|
|
end if;
|
451 |
|
|
|
452 |
|
|
end process;
|
453 |
|
|
|
454 |
|
|
|
455 |
|
|
-- ----------------------------------------------
|
456 |
|
|
-- Synchronous Accumulation: us_DMA_Bytes
|
457 |
|
|
--
|
458 |
|
|
Syn_ds_DMA_Bytes_Add:
|
459 |
|
|
process ( trn_clk, Local_Reset_i)
|
460 |
|
|
begin
|
461 |
|
|
if Local_Reset_i = '1' then
|
462 |
|
|
ds_DMA_Bytes_Add_i <= '0' ;
|
463 |
|
|
ds_DMA_Bytes_i <= (OTHERS=>'0');
|
464 |
|
|
elsif trn_clk'event and trn_clk = '1' then
|
465 |
|
|
if trn_reof_n_i='0' and trn_rx_throttle='0'
|
466 |
|
|
and CplD_is_Payloaded='1' and MSB_DSP_Tag='0'
|
467 |
|
|
then
|
468 |
|
|
ds_DMA_Bytes_Add_i <= '1' ;
|
469 |
|
|
ds_DMA_Bytes_i <= CplD_Leng_in_Bytes(C_TLP_FLD_WIDTH_OF_LENG+2 downto 0);
|
470 |
|
|
else
|
471 |
|
|
ds_DMA_Bytes_Add_i <= '0' ;
|
472 |
|
|
ds_DMA_Bytes_i <= (OTHERS=>'0');
|
473 |
|
|
end if;
|
474 |
|
|
end if;
|
475 |
|
|
|
476 |
|
|
end process;
|
477 |
|
|
|
478 |
|
|
|
479 |
|
|
-- Registers writing
|
480 |
|
|
Regs_WrEn <= Regs_WrEn_i;
|
481 |
|
|
Regs_WrMask <= Regs_WrMask_i;
|
482 |
|
|
Regs_WrAddr <= Regs_WrAddr_i;
|
483 |
|
|
Regs_WrDin <= Regs_WrDin_i;
|
484 |
|
|
|
485 |
|
|
|
486 |
|
|
--- Dex Tag output to us DMA channel
|
487 |
|
|
usDMA_dex_Tag <= usDMA_dex_Tag_i;
|
488 |
|
|
|
489 |
|
|
--- Dex Tag output to ds DMA channel
|
490 |
|
|
dsDMA_dex_Tag <= dsDMA_dex_Tag_i;
|
491 |
|
|
|
492 |
|
|
|
493 |
|
|
---------------------------------------------------
|
494 |
|
|
Req_ID_Match_i <= Req_ID_Match;
|
495 |
|
|
|
496 |
|
|
Dex_Tag_Matched_i <= usDex_Tag_Matched or dsDex_Tag_Matched;
|
497 |
|
|
|
498 |
|
|
-- positive reset
|
499 |
|
|
Local_Reset_i <= not trn_reset_n;
|
500 |
|
|
|
501 |
|
|
|
502 |
|
|
-- Frame signals
|
503 |
|
|
trn_rsof_n_i <= trn_rsof_n;
|
504 |
|
|
trn_reof_n_i <= trn_reof_n;
|
505 |
|
|
trn_rd_i <= trn_rd;
|
506 |
|
|
trn_rrem_n_i <= trn_rrem_n;
|
507 |
|
|
trn_rsrc_rdy_n_i <= trn_rsrc_rdy_n;
|
508 |
|
|
trn_rdst_rdy_n_i <= trn_rdst_rdy_n;
|
509 |
|
|
|
510 |
|
|
|
511 |
|
|
-- BC of the current TLP payloads
|
512 |
|
|
CplD_Leng_in_Bytes <= C_ALL_ZEROS(C_DBUS_WIDTH/2-1 downto C_TLP_FLD_WIDTH_OF_LENG+3)
|
513 |
|
|
& CplD_Length & "00";
|
514 |
|
|
|
515 |
|
|
|
516 |
|
|
-- Exception signals
|
517 |
|
|
trn_rerrfwd_n_i <= trn_rerrfwd_n;
|
518 |
|
|
trn_rsrc_dsc_n_i <= trn_rsrc_dsc_n;
|
519 |
|
|
|
520 |
|
|
|
521 |
|
|
-- ( trn_rsrc_rdy_n seems never deasserted during packet)
|
522 |
|
|
trn_rx_throttle <= trn_rsrc_rdy_n_i or trn_rdst_rdy_n_i;
|
523 |
|
|
|
524 |
|
|
|
525 |
|
|
Syn_TLP_is_not_CplD:
|
526 |
|
|
process ( trn_clk, Local_Reset_i)
|
527 |
|
|
begin
|
528 |
|
|
if Local_Reset_i = '1' then
|
529 |
|
|
TLP_is_not_CplD <= '1';
|
530 |
|
|
TLP_is_not_CplD_r1 <= '1';
|
531 |
|
|
TLP_is_not_CplD_r2 <= '1';
|
532 |
|
|
TLP_is_not_CplD_r3 <= '1';
|
533 |
|
|
TLP_is_not_CplD_r4 <= '1';
|
534 |
|
|
TLP_is_not_CplD_r5 <= '1';
|
535 |
|
|
elsif trn_clk'event and trn_clk = '1' then
|
536 |
|
|
TLP_is_not_CplD_r1 <= TLP_is_not_CplD;
|
537 |
|
|
TLP_is_not_CplD_r2 <= TLP_is_not_CplD_r1;
|
538 |
|
|
TLP_is_not_CplD_r3 <= TLP_is_not_CplD_r2;
|
539 |
|
|
TLP_is_not_CplD_r4 <= TLP_is_not_CplD_r3;
|
540 |
|
|
TLP_is_not_CplD_r5 <= TLP_is_not_CplD_r4;
|
541 |
|
|
if trn_rsof_n_i='0' and trn_rx_throttle='0' then
|
542 |
|
|
if CplD_Type=C_TLP_TYPE_IS_CPLD then
|
543 |
|
|
TLP_is_not_CplD <= '0';
|
544 |
|
|
else
|
545 |
|
|
TLP_is_not_CplD <= '1';
|
546 |
|
|
end if;
|
547 |
|
|
else
|
548 |
|
|
TLP_is_not_CplD <= TLP_is_not_CplD;
|
549 |
|
|
end if;
|
550 |
|
|
end if;
|
551 |
|
|
|
552 |
|
|
end process;
|
553 |
|
|
|
554 |
|
|
-- ---------------------------------------------
|
555 |
|
|
-- Synchronous bit: CplD_State_is_AFetch
|
556 |
|
|
--
|
557 |
|
|
RxFSM_CplD_State_is_AFetch:
|
558 |
|
|
process ( trn_clk )
|
559 |
|
|
begin
|
560 |
|
|
if trn_clk'event and trn_clk = '1' then
|
561 |
|
|
|
562 |
|
|
CplD_State_is_AFetch_r1 <= CplD_State_is_AFetch;
|
563 |
|
|
|
564 |
|
|
case RxCplDTrn_State is
|
565 |
|
|
when ST_CplD_AFetch =>
|
566 |
|
|
CplD_State_is_AFetch <= '1';
|
567 |
|
|
when ST_CplD_AFetch_Special =>
|
568 |
|
|
CplD_State_is_AFetch <= '1';
|
569 |
|
|
when OTHERS =>
|
570 |
|
|
CplD_State_is_AFetch <= '0';
|
571 |
|
|
end case;
|
572 |
|
|
|
573 |
|
|
end if;
|
574 |
|
|
end process;
|
575 |
|
|
|
576 |
|
|
|
577 |
|
|
-- ---------------------------------------------
|
578 |
|
|
-- Synchronous bit: CplD_State_is_after_AFetch
|
579 |
|
|
--
|
580 |
|
|
RxFSM_CplD_State_is_after_AFetch:
|
581 |
|
|
process ( trn_clk )
|
582 |
|
|
begin
|
583 |
|
|
if trn_clk'event and trn_clk = '1' then
|
584 |
|
|
|
585 |
|
|
CplD_State_is_after_AFetch_r1 <= CplD_State_is_after_AFetch;
|
586 |
|
|
|
587 |
|
|
case RxCplDTrn_State is
|
588 |
|
|
when ST_CplD_AFetch_Special_Tail =>
|
589 |
|
|
CplD_State_is_after_AFetch <= '1';
|
590 |
|
|
when ST_CplD_AFetch_Special =>
|
591 |
|
|
CplD_State_is_after_AFetch <= '0';
|
592 |
|
|
when ST_CplD_ONLY_1DW =>
|
593 |
|
|
CplD_State_is_after_AFetch <= '1';
|
594 |
|
|
when ST_CplD_1ST_DATA =>
|
595 |
|
|
CplD_State_is_after_AFetch <= '1';
|
596 |
|
|
when OTHERS =>
|
597 |
|
|
CplD_State_is_after_AFetch <= CplD_State_is_AFetch and not trn_rx_throttle_r1; --'0';
|
598 |
|
|
end case;
|
599 |
|
|
|
600 |
|
|
end if;
|
601 |
|
|
end process;
|
602 |
|
|
|
603 |
|
|
|
604 |
|
|
-- ---------------------------------------------
|
605 |
|
|
-- Delay Synchronous Delay: trn_r*
|
606 |
|
|
--
|
607 |
|
|
Syn_Delay_trn_r_x:
|
608 |
|
|
process ( trn_clk )
|
609 |
|
|
begin
|
610 |
|
|
if trn_clk'event and trn_clk = '1' then
|
611 |
|
|
trn_rsof_n_r1 <= trn_rsof_n_i;
|
612 |
|
|
trn_rsof_n_r2 <= trn_rsof_n_r1;
|
613 |
|
|
trn_rsof_n_r3 <= trn_rsof_n_r2;
|
614 |
|
|
trn_rsof_n_r4 <= trn_rsof_n_r3;
|
615 |
|
|
|
616 |
|
|
trn_reof_n_r1 <= trn_reof_n_i;
|
617 |
|
|
trn_reof_n_r2 <= trn_reof_n_r1;
|
618 |
|
|
trn_reof_n_r3 <= trn_reof_n_r2;
|
619 |
|
|
trn_reof_n_r4 <= trn_reof_n_r3;
|
620 |
|
|
|
621 |
|
|
trn_rsrc_rdy_n_r1 <= trn_rx_throttle; -- trn_rsrc_rdy_n_i;
|
622 |
|
|
trn_rsrc_rdy_n_r2 <= trn_rsrc_rdy_n_r1;
|
623 |
|
|
trn_rsrc_rdy_n_r3 <= trn_rsrc_rdy_n_r2;
|
624 |
|
|
trn_rsrc_rdy_n_r4 <= trn_rsrc_rdy_n_r3;
|
625 |
|
|
|
626 |
|
|
trn_rx_throttle_r1 <= trn_rx_throttle;
|
627 |
|
|
trn_rx_throttle_r2 <= trn_rx_throttle_r1;
|
628 |
|
|
trn_rx_throttle_r3 <= trn_rx_throttle_r2;
|
629 |
|
|
trn_rx_throttle_r4 <= trn_rx_throttle_r3;
|
630 |
|
|
|
631 |
|
|
trn_rd_r1 <= trn_rd_i;
|
632 |
|
|
trn_rd_r2 <= trn_rd_r1;
|
633 |
|
|
trn_rd_r3 <= trn_rd_r2;
|
634 |
|
|
trn_rd_r4 <= trn_rd_r3;
|
635 |
|
|
|
636 |
|
|
trn_rrem_n_r1 <= trn_rrem_n_i;
|
637 |
|
|
trn_rrem_n_r2 <= trn_rrem_n_r1;
|
638 |
|
|
trn_rrem_n_r3 <= trn_rrem_n_r2;
|
639 |
|
|
trn_rrem_n_r4 <= trn_rrem_n_r3;
|
640 |
|
|
|
641 |
|
|
end if;
|
642 |
|
|
end process;
|
643 |
|
|
|
644 |
|
|
|
645 |
|
|
-- Endian reversed
|
646 |
|
|
trn_rd_Little <= Endian_Invert_64 (trn_rd_i);
|
647 |
|
|
trn_rd_Little_r1 <= Endian_Invert_64 (trn_rd_r1);
|
648 |
|
|
trn_rd_Little_r2 <= Endian_Invert_64 (trn_rd_r2);
|
649 |
|
|
trn_rd_Little_r3 <= Endian_Invert_64 (trn_rd_r3);
|
650 |
|
|
trn_rd_Little_r4 <= Endian_Invert_64 (trn_rd_r4);
|
651 |
|
|
|
652 |
|
|
|
653 |
|
|
-- ---------------------------------------------
|
654 |
|
|
MSB_DSP_Tag <= CplD_Tag(C_TAG_WIDTH-1);
|
655 |
|
|
DSP_Tag_on_RAM <= not CplD_Tag(C_TAG_WIDTH-1) and not CplD_Tag(C_TAG_WIDTH-2);
|
656 |
|
|
DSP_Tag_on_FIFO <= not CplD_Tag(C_TAG_WIDTH-1) and CplD_Tag(C_TAG_WIDTH-2);
|
657 |
|
|
|
658 |
|
|
--
|
659 |
|
|
-- Delay Synchronous: MSB_DSP_Tag_r1
|
660 |
|
|
--
|
661 |
|
|
Syn_Delay_MSB_DSP_Tag_r1:
|
662 |
|
|
process ( trn_clk )
|
663 |
|
|
begin
|
664 |
|
|
if trn_clk'event and trn_clk = '1' then
|
665 |
|
|
CplD_Tag_r1 <= CplD_Tag;
|
666 |
|
|
CplD_Tag_r2 <= CplD_Tag_r1;
|
667 |
|
|
CplD_Tag_r3 <= CplD_Tag_r2;
|
668 |
|
|
CplD_Tag_r4 <= CplD_Tag_r3;
|
669 |
|
|
MSB_DSP_Tag_r1 <= MSB_DSP_Tag;
|
670 |
|
|
DSP_Tag_on_RAM_r1 <= DSP_Tag_on_RAM;
|
671 |
|
|
DSP_Tag_on_RAM_r2 <= DSP_Tag_on_RAM_r1;
|
672 |
|
|
DSP_Tag_on_RAM_r3 <= DSP_Tag_on_RAM_r2;
|
673 |
|
|
DSP_Tag_on_RAM_r4p <= DSP_Tag_on_RAM_r2 or DSP_Tag_on_RAM_r3;
|
674 |
|
|
end if;
|
675 |
|
|
end process;
|
676 |
|
|
|
677 |
|
|
|
678 |
|
|
--
|
679 |
|
|
-- Delay Synchronous: CplD_Leng_in_Bytes
|
680 |
|
|
--
|
681 |
|
|
Syn_Delay_CplD_Leng_in_Bytes:
|
682 |
|
|
process ( trn_clk )
|
683 |
|
|
begin
|
684 |
|
|
if trn_clk'event and trn_clk = '1' then
|
685 |
|
|
CplD_Leng_in_Bytes_r1 <= CplD_Leng_in_Bytes;
|
686 |
|
|
CplD_Leng_in_Bytes_r2 <= CplD_Leng_in_Bytes_r1;
|
687 |
|
|
end if;
|
688 |
|
|
end process;
|
689 |
|
|
|
690 |
|
|
|
691 |
|
|
-- ---------------------------------------------
|
692 |
|
|
-- Delay Synchronous Delay: RxCplDTrn_State
|
693 |
|
|
--
|
694 |
|
|
RxFSM_Delay_RxTrn_State:
|
695 |
|
|
process ( trn_clk )
|
696 |
|
|
begin
|
697 |
|
|
if trn_clk'event and trn_clk = '1' then
|
698 |
|
|
RxCplDTrn_State_r1 <= RxCplDTrn_State;
|
699 |
|
|
RxCplDTrn_State_r2 <= RxCplDTrn_State_r1;
|
700 |
|
|
end if;
|
701 |
|
|
end process;
|
702 |
|
|
|
703 |
|
|
|
704 |
|
|
-- ----------------------------------------------
|
705 |
|
|
-- States synchronous
|
706 |
|
|
--
|
707 |
|
|
Syn_RxTrn_States:
|
708 |
|
|
process ( trn_clk, Local_Reset_i)
|
709 |
|
|
begin
|
710 |
|
|
if Local_Reset_i = '1' then
|
711 |
|
|
RxCplDTrn_State <= ST_CplD_RESET;
|
712 |
|
|
elsif trn_clk'event and trn_clk = '1' then
|
713 |
|
|
RxCplDTrn_State <= RxCplDTrn_NextState;
|
714 |
|
|
end if;
|
715 |
|
|
|
716 |
|
|
end process;
|
717 |
|
|
|
718 |
|
|
|
719 |
|
|
-- Next States
|
720 |
|
|
Comb_RxTrn_NextStates:
|
721 |
|
|
process (
|
722 |
|
|
RxCplDTrn_State
|
723 |
|
|
, CplD_Type
|
724 |
|
|
, MSB_DSP_Tag
|
725 |
|
|
, trn_reof_n_i
|
726 |
|
|
, trn_rx_throttle
|
727 |
|
|
, Req_ID_Match_i
|
728 |
|
|
, Dex_Tag_Matched_i
|
729 |
|
|
)
|
730 |
|
|
begin
|
731 |
|
|
case RxCplDTrn_State is
|
732 |
|
|
|
733 |
|
|
when ST_CplD_RESET =>
|
734 |
|
|
RxCplDTrn_NextState <= ST_CplD_IDLE;
|
735 |
|
|
|
736 |
|
|
when ST_CplD_IDLE =>
|
737 |
|
|
|
738 |
|
|
if trn_rx_throttle='0' then
|
739 |
|
|
case CplD_Type is
|
740 |
|
|
when C_TLP_TYPE_IS_CPLD =>
|
741 |
|
|
RxCplDTrn_NextState <= ST_CplD_HEAD2;
|
742 |
|
|
when C_TLP_TYPE_IS_CPL =>
|
743 |
|
|
RxCplDTrn_NextState <= ST_Cpl_HEAD2;
|
744 |
|
|
when C_TLP_TYPE_IS_CPLDLK =>
|
745 |
|
|
RxCplDTrn_NextState <= ST_CplD_HEAD2;
|
746 |
|
|
when C_TLP_TYPE_IS_CPLLK =>
|
747 |
|
|
RxCplDTrn_NextState <= ST_Cpl_HEAD2;
|
748 |
|
|
when OTHERS =>
|
749 |
|
|
RxCplDTrn_NextState <= ST_CplD_IDLE;
|
750 |
|
|
end case; -- CplD_Type
|
751 |
|
|
else
|
752 |
|
|
RxCplDTrn_NextState <= ST_CplD_IDLE;
|
753 |
|
|
end if;
|
754 |
|
|
|
755 |
|
|
|
756 |
|
|
|
757 |
|
|
when ST_Cpl_HEAD2 => -- further processing to be done ...
|
758 |
|
|
RxCplDTrn_NextState <= ST_CplD_IDLE;
|
759 |
|
|
|
760 |
|
|
|
761 |
|
|
when ST_CplD_HEAD2 =>
|
762 |
|
|
if trn_rx_throttle = '1' then
|
763 |
|
|
RxCplDTrn_NextState <= ST_CplD_HEAD2;
|
764 |
|
|
elsif Req_ID_Match_i='1' and Dex_Tag_Matched_i='1' then
|
765 |
|
|
if trn_reof_n_i='0' then
|
766 |
|
|
RxCplDTrn_NextState <= ST_CplD_AFetch_Special;
|
767 |
|
|
else
|
768 |
|
|
RxCplDTrn_NextState <= ST_CplD_AFetch;
|
769 |
|
|
end if;
|
770 |
|
|
elsif Req_ID_Match_i='1' and MSB_DSP_Tag='0' then
|
771 |
|
|
if trn_reof_n_i='0' then
|
772 |
|
|
RxCplDTrn_NextState <= ST_CplD_AFetch_Special;
|
773 |
|
|
else
|
774 |
|
|
RxCplDTrn_NextState <= ST_CplD_AFetch;
|
775 |
|
|
end if;
|
776 |
|
|
else
|
777 |
|
|
RxCplDTrn_NextState <= ST_CplD_IDLE;
|
778 |
|
|
end if;
|
779 |
|
|
|
780 |
|
|
|
781 |
|
|
when ST_CplD_AFetch =>
|
782 |
|
|
if trn_reof_n_i='0' then
|
783 |
|
|
RxCplDTrn_NextState <= ST_CplD_ONLY_1DW;
|
784 |
|
|
elsif trn_rx_throttle = '1' then
|
785 |
|
|
RxCplDTrn_NextState <= ST_CplD_AFetch_THROTTLE;
|
786 |
|
|
else
|
787 |
|
|
RxCplDTrn_NextState <= ST_CplD_1ST_DATA;
|
788 |
|
|
end if;
|
789 |
|
|
|
790 |
|
|
when ST_CplD_AFetch_Special =>
|
791 |
|
|
if trn_rx_throttle='0' then
|
792 |
|
|
case CplD_Type is
|
793 |
|
|
when C_TLP_TYPE_IS_CPLD =>
|
794 |
|
|
RxCplDTrn_NextState <= ST_CplD_HEAD2;
|
795 |
|
|
when C_TLP_TYPE_IS_CPL =>
|
796 |
|
|
RxCplDTrn_NextState <= ST_Cpl_HEAD2;
|
797 |
|
|
when C_TLP_TYPE_IS_CPLDLK =>
|
798 |
|
|
RxCplDTrn_NextState <= ST_CplD_HEAD2;
|
799 |
|
|
when C_TLP_TYPE_IS_CPLLK =>
|
800 |
|
|
RxCplDTrn_NextState <= ST_Cpl_HEAD2;
|
801 |
|
|
when OTHERS =>
|
802 |
|
|
RxCplDTrn_NextState <= ST_CplD_IDLE;
|
803 |
|
|
end case; -- CplD_Type
|
804 |
|
|
else
|
805 |
|
|
RxCplDTrn_NextState <= ST_CplD_AFetch_Special_Tail;
|
806 |
|
|
end if;
|
807 |
|
|
|
808 |
|
|
|
809 |
|
|
when ST_CplD_AFetch_Special_Tail =>
|
810 |
|
|
if trn_rx_throttle='0' then
|
811 |
|
|
case CplD_Type is
|
812 |
|
|
when C_TLP_TYPE_IS_CPLD =>
|
813 |
|
|
RxCplDTrn_NextState <= ST_CplD_HEAD2;
|
814 |
|
|
when C_TLP_TYPE_IS_CPL =>
|
815 |
|
|
RxCplDTrn_NextState <= ST_Cpl_HEAD2;
|
816 |
|
|
when C_TLP_TYPE_IS_CPLDLK =>
|
817 |
|
|
RxCplDTrn_NextState <= ST_CplD_HEAD2;
|
818 |
|
|
when C_TLP_TYPE_IS_CPLLK =>
|
819 |
|
|
RxCplDTrn_NextState <= ST_Cpl_HEAD2;
|
820 |
|
|
when OTHERS =>
|
821 |
|
|
RxCplDTrn_NextState <= ST_CplD_IDLE;
|
822 |
|
|
end case; -- CplD_Type
|
823 |
|
|
else
|
824 |
|
|
RxCplDTrn_NextState <= ST_CplD_IDLE;
|
825 |
|
|
end if;
|
826 |
|
|
|
827 |
|
|
|
828 |
|
|
when ST_CplD_AFetch_THROTTLE =>
|
829 |
|
|
if trn_reof_n_i='0' then
|
830 |
|
|
RxCplDTrn_NextState <= ST_CplD_ONLY_1DW;
|
831 |
|
|
elsif trn_rx_throttle = '1' then
|
832 |
|
|
RxCplDTrn_NextState <= ST_CplD_AFetch_THROTTLE;
|
833 |
|
|
else
|
834 |
|
|
RxCplDTrn_NextState <= ST_CplD_1ST_DATA;
|
835 |
|
|
end if;
|
836 |
|
|
|
837 |
|
|
|
838 |
|
|
when ST_CplD_ONLY_1DW =>
|
839 |
|
|
if trn_rx_throttle='0' then
|
840 |
|
|
case CplD_Type is
|
841 |
|
|
when C_TLP_TYPE_IS_CPLD =>
|
842 |
|
|
RxCplDTrn_NextState <= ST_CplD_HEAD2;
|
843 |
|
|
when C_TLP_TYPE_IS_CPL =>
|
844 |
|
|
RxCplDTrn_NextState <= ST_Cpl_HEAD2;
|
845 |
|
|
when C_TLP_TYPE_IS_CPLDLK =>
|
846 |
|
|
RxCplDTrn_NextState <= ST_CplD_HEAD2;
|
847 |
|
|
when C_TLP_TYPE_IS_CPLLK =>
|
848 |
|
|
RxCplDTrn_NextState <= ST_Cpl_HEAD2;
|
849 |
|
|
when OTHERS =>
|
850 |
|
|
RxCplDTrn_NextState <= ST_CplD_IDLE;
|
851 |
|
|
end case; -- CplD_Type
|
852 |
|
|
else
|
853 |
|
|
RxCplDTrn_NextState <= ST_CplD_IDLE;
|
854 |
|
|
end if;
|
855 |
|
|
|
856 |
|
|
|
857 |
|
|
when ST_CplD_1ST_DATA =>
|
858 |
|
|
if trn_reof_n_i='0' then
|
859 |
|
|
RxCplDTrn_NextState <= ST_CplD_LAST_DATA;
|
860 |
|
|
elsif trn_rx_throttle = '1' then
|
861 |
|
|
RxCplDTrn_NextState <= ST_CplD_1ST_DATA_THROTTLE;
|
862 |
|
|
else
|
863 |
|
|
RxCplDTrn_NextState <= ST_CplD_DATA;
|
864 |
|
|
end if;
|
865 |
|
|
|
866 |
|
|
when ST_CplD_1ST_DATA_THROTTLE =>
|
867 |
|
|
if trn_reof_n_i='0' then
|
868 |
|
|
RxCplDTrn_NextState <= ST_CplD_LAST_DATA;
|
869 |
|
|
elsif trn_rx_throttle = '1' then
|
870 |
|
|
RxCplDTrn_NextState <= ST_CplD_1ST_DATA_THROTTLE;
|
871 |
|
|
else
|
872 |
|
|
RxCplDTrn_NextState <= ST_CplD_DATA;
|
873 |
|
|
end if;
|
874 |
|
|
|
875 |
|
|
|
876 |
|
|
when ST_CplD_DATA =>
|
877 |
|
|
if trn_reof_n_i='0' then
|
878 |
|
|
RxCplDTrn_NextState <= ST_CplD_LAST_DATA;
|
879 |
|
|
elsif trn_rx_throttle = '1' then
|
880 |
|
|
RxCplDTrn_NextState <= ST_CplD_DATA_THROTTLE;
|
881 |
|
|
else
|
882 |
|
|
RxCplDTrn_NextState <= ST_CplD_DATA;
|
883 |
|
|
end if;
|
884 |
|
|
|
885 |
|
|
|
886 |
|
|
when ST_CplD_DATA_THROTTLE =>
|
887 |
|
|
if trn_reof_n_i='0' then
|
888 |
|
|
RxCplDTrn_NextState <= ST_CplD_LAST_DATA;
|
889 |
|
|
elsif trn_rx_throttle = '1' then
|
890 |
|
|
RxCplDTrn_NextState <= ST_CplD_DATA_THROTTLE;
|
891 |
|
|
else
|
892 |
|
|
RxCplDTrn_NextState <= ST_CplD_DATA;
|
893 |
|
|
end if;
|
894 |
|
|
|
895 |
|
|
|
896 |
|
|
when ST_CplD_LAST_DATA => -- Same as IDLE, to support
|
897 |
|
|
-- back-to-back transactions
|
898 |
|
|
if trn_rx_throttle='0' then
|
899 |
|
|
case CplD_Type is
|
900 |
|
|
when C_TLP_TYPE_IS_CPLD =>
|
901 |
|
|
RxCplDTrn_NextState <= ST_CplD_HEAD2;
|
902 |
|
|
when C_TLP_TYPE_IS_CPL =>
|
903 |
|
|
RxCplDTrn_NextState <= ST_Cpl_HEAD2;
|
904 |
|
|
when C_TLP_TYPE_IS_CPLDLK =>
|
905 |
|
|
RxCplDTrn_NextState <= ST_CplD_HEAD2;
|
906 |
|
|
when C_TLP_TYPE_IS_CPLLK =>
|
907 |
|
|
RxCplDTrn_NextState <= ST_Cpl_HEAD2;
|
908 |
|
|
when OTHERS =>
|
909 |
|
|
RxCplDTrn_NextState <= ST_CplD_IDLE;
|
910 |
|
|
end case; -- CplD_Type
|
911 |
|
|
else
|
912 |
|
|
RxCplDTrn_NextState <= ST_CplD_IDLE;
|
913 |
|
|
end if;
|
914 |
|
|
|
915 |
|
|
|
916 |
|
|
when OTHERS =>
|
917 |
|
|
RxCplDTrn_NextState <= ST_CplD_RESET;
|
918 |
|
|
|
919 |
|
|
end case;
|
920 |
|
|
|
921 |
|
|
end process;
|
922 |
|
|
|
923 |
|
|
|
924 |
|
|
-- -------------------------------------------------
|
925 |
|
|
-- Synchronous Registered: Tag_Map_Clear_i
|
926 |
|
|
--
|
927 |
|
|
RxTrn_Tag_Map_Clear:
|
928 |
|
|
process ( trn_clk, Local_Reset_i)
|
929 |
|
|
begin
|
930 |
|
|
if Local_Reset_i = '1' then
|
931 |
|
|
Tag_Map_Clear_i <= (OTHERS=>'0');
|
932 |
|
|
|
933 |
|
|
elsif trn_clk'event and trn_clk = '1' then
|
934 |
|
|
|
935 |
|
|
FOR j IN 0 TO C_TAG_MAP_WIDTH-1 LOOP
|
936 |
|
|
|
937 |
|
|
-- CplD_Tag(C_TAG_WIDTH-2) used as token of BAR
|
938 |
|
|
if CplD_Tag(C_TAG_WIDTH-1)='0'
|
939 |
|
|
and CplD_Tag(C_TAG_WIDTH-2-1 downto 0)=CONV_STD_LOGIC_VECTOR(j, C_TAG_WIDTH-2)
|
940 |
|
|
and CplD_is_the_Last='1' then
|
941 |
|
|
Tag_Map_Clear_i(j) <= '1';
|
942 |
|
|
else
|
943 |
|
|
Tag_Map_Clear_i(j) <= '0';
|
944 |
|
|
end if;
|
945 |
|
|
|
946 |
|
|
END LOOP;
|
947 |
|
|
|
948 |
|
|
end if;
|
949 |
|
|
end process;
|
950 |
|
|
|
951 |
|
|
|
952 |
|
|
|
953 |
|
|
-- -------------------------------------------------
|
954 |
|
|
-- Synchronous Registered: CplD_Length
|
955 |
|
|
--
|
956 |
|
|
RxTrn_CplD_Length:
|
957 |
|
|
process ( trn_clk, Local_Reset_i)
|
958 |
|
|
begin
|
959 |
|
|
if Local_Reset_i = '1' then
|
960 |
|
|
CplD_Length <= (OTHERS => '0');
|
961 |
|
|
CplD_is_1DW <= '0';
|
962 |
|
|
Small_CplD <= '0';
|
963 |
|
|
Small_CplD_r1 <= '0';
|
964 |
|
|
|
965 |
|
|
elsif trn_clk'event and trn_clk = '1' then
|
966 |
|
|
|
967 |
|
|
Small_CplD_r1 <= Small_CplD;
|
968 |
|
|
|
969 |
|
|
if trn_rsof_n_i='0' then
|
970 |
|
|
CplD_Length <= Tlp_has_4KB & trn_rd_i(C_TLP_LENG_BIT_TOP downto C_TLP_LENG_BIT_BOT);
|
971 |
|
|
CplD_is_1DW <= Tlp_has_1DW;
|
972 |
|
|
if trn_rd_i(C_TLP_LENG_BIT_TOP downto C_TLP_LENG_BIT_BOT+3)=C_ALL_ZEROS(C_TLP_LENG_BIT_TOP downto C_TLP_LENG_BIT_BOT+3)
|
973 |
|
|
and
|
974 |
|
|
(trn_rd_i(C_TLP_LENG_BIT_BOT+2 downto C_TLP_LENG_BIT_BOT)="000"
|
975 |
|
|
or trn_rd_i(C_TLP_LENG_BIT_BOT+2 downto C_TLP_LENG_BIT_BOT)="001"
|
976 |
|
|
or trn_rd_i(C_TLP_LENG_BIT_BOT+2 downto C_TLP_LENG_BIT_BOT)="010"
|
977 |
|
|
or trn_rd_i(C_TLP_LENG_BIT_BOT+2 downto C_TLP_LENG_BIT_BOT)="011"
|
978 |
|
|
or trn_rd_i(C_TLP_LENG_BIT_BOT+2 downto C_TLP_LENG_BIT_BOT)="100"
|
979 |
|
|
or trn_rd_i(C_TLP_LENG_BIT_BOT+2 downto C_TLP_LENG_BIT_BOT)="101"
|
980 |
|
|
)
|
981 |
|
|
and trn_rd_i(C_TLP_TYPE_BIT_TOP downto C_TLP_TYPE_BIT_TOP-1)="01" -- Cpl/D
|
982 |
|
|
then
|
983 |
|
|
Small_CplD <= '1';
|
984 |
|
|
else
|
985 |
|
|
Small_CplD <= '0';
|
986 |
|
|
end if;
|
987 |
|
|
else
|
988 |
|
|
CplD_Length <= CplD_Length;
|
989 |
|
|
CplD_is_1DW <= CplD_is_1DW;
|
990 |
|
|
Small_CplD <= Small_CplD;
|
991 |
|
|
end if;
|
992 |
|
|
|
993 |
|
|
end if;
|
994 |
|
|
end process;
|
995 |
|
|
|
996 |
|
|
|
997 |
|
|
|
998 |
|
|
-- -------------------------------------------------
|
999 |
|
|
-- Synchronous outputs: Addr_Inc
|
1000 |
|
|
--
|
1001 |
|
|
RxFSM_Output_Addr_Inc:
|
1002 |
|
|
process ( trn_clk, Local_Reset_i)
|
1003 |
|
|
begin
|
1004 |
|
|
if Local_Reset_i = '1' then
|
1005 |
|
|
Addr_Inc <= '1';
|
1006 |
|
|
|
1007 |
|
|
elsif trn_clk'event and trn_clk = '1' then
|
1008 |
|
|
|
1009 |
|
|
case RxCplDTrn_State_r1 is
|
1010 |
|
|
|
1011 |
|
|
when ST_CplD_RESET =>
|
1012 |
|
|
Addr_Inc <= '1';
|
1013 |
|
|
|
1014 |
|
|
when ST_CplD_1ST_DATA =>
|
1015 |
|
|
Addr_Inc <= tRAM_DoutA_r1(CBIT_AINC_IN_TAGRAM);
|
1016 |
|
|
|
1017 |
|
|
when ST_CplD_ONLY_1DW =>
|
1018 |
|
|
Addr_Inc <= tRAM_DoutA_r1(CBIT_AINC_IN_TAGRAM);
|
1019 |
|
|
|
1020 |
|
|
when OTHERS =>
|
1021 |
|
|
Addr_Inc <= Addr_Inc;
|
1022 |
|
|
|
1023 |
|
|
end case;
|
1024 |
|
|
end if;
|
1025 |
|
|
end process;
|
1026 |
|
|
|
1027 |
|
|
|
1028 |
|
|
-------------------------------------------------
|
1029 |
|
|
-- Calculation at trn_rsof_n
|
1030 |
|
|
--
|
1031 |
|
|
Syn_Dex_wrAddress:
|
1032 |
|
|
process ( trn_clk, Local_Reset_i)
|
1033 |
|
|
begin
|
1034 |
|
|
if Local_Reset_i = '1' then
|
1035 |
|
|
Dex_CplD_Illegal <= '0';
|
1036 |
|
|
Reg_WrAddr_if_last_us <= (OTHERS=>'0'); -- C_REGS_BASE_ADDR;
|
1037 |
|
|
Reg_WrAddr_if_last_ds <= (OTHERS=>'0'); -- C_REGS_BASE_ADDR;
|
1038 |
|
|
|
1039 |
|
|
elsif trn_clk'event and trn_clk = '1' then
|
1040 |
|
|
|
1041 |
|
|
if trn_rsof_n_i = '0' then
|
1042 |
|
|
Reg_WrAddr_if_last_us(C_EP_AWIDTH-2-1 downto 2) <= CONV_STD_LOGIC_VECTOR(CINT_ADDR_DMA_US_CTRL, C_EP_AWIDTH-2-2) - trn_rd_i(C_NEXT_BD_LENG_MSB+32 downto 32);
|
1043 |
|
|
Reg_WrAddr_if_last_ds(C_EP_AWIDTH-2-1 downto 2) <= CONV_STD_LOGIC_VECTOR(CINT_ADDR_DMA_DS_CTRL, C_EP_AWIDTH-2-2) - trn_rd_i(C_NEXT_BD_LENG_MSB+32 downto 32);
|
1044 |
|
|
-- Reg_WrAddr_if_last_us(C_EP_AWIDTH-2-1 downto 2) <= CONV_STD_LOGIC_VECTOR(CINT_ADDR_DMA_US_STA, C_EP_AWIDTH-2-2) - trn_rd_i(C_NEXT_BD_LENG_MSB+32 downto 32);
|
1045 |
|
|
-- Reg_WrAddr_if_last_ds(C_EP_AWIDTH-2-1 downto 2) <= CONV_STD_LOGIC_VECTOR(CINT_ADDR_DMA_DS_STA, C_EP_AWIDTH-2-2) - trn_rd_i(C_NEXT_BD_LENG_MSB+32 downto 32);
|
1046 |
|
|
else
|
1047 |
|
|
Reg_WrAddr_if_last_us <= Reg_WrAddr_if_last_us;
|
1048 |
|
|
Reg_WrAddr_if_last_ds <= Reg_WrAddr_if_last_ds;
|
1049 |
|
|
end if;
|
1050 |
|
|
|
1051 |
|
|
end if;
|
1052 |
|
|
|
1053 |
|
|
end process;
|
1054 |
|
|
|
1055 |
|
|
|
1056 |
|
|
-- ---------------------------------------------
|
1057 |
|
|
-- Reg Synchronous: RegAddr_?s_Dex
|
1058 |
|
|
--
|
1059 |
|
|
RxFSM_Reg_RegAddr_xs_Dex:
|
1060 |
|
|
process ( trn_clk, Local_Reset_i)
|
1061 |
|
|
begin
|
1062 |
|
|
if Local_Reset_i = '1' then
|
1063 |
|
|
RegAddr_us_Dex <= (Others=>'1');
|
1064 |
|
|
RegAddr_ds_Dex <= (Others=>'1');
|
1065 |
|
|
|
1066 |
|
|
elsif trn_clk'event and trn_clk = '1' then
|
1067 |
|
|
|
1068 |
|
|
if CplD_Tag(C_TAG_WIDTH-1 downto C_TAG_WIDTH-C_TAG_DECODE_BITS)/=C_TAG0_DMA_USB(C_TAG_WIDTH-1 downto C_TAG_WIDTH-C_TAG_DECODE_BITS) then
|
1069 |
|
|
RegAddr_us_Dex <= (Others=>'1');
|
1070 |
|
|
elsif CplD_is_the_Last = '1' then -- us last/2nd dex
|
1071 |
|
|
RegAddr_us_Dex <= Reg_WrAddr_if_last_us;
|
1072 |
|
|
else -- us 1st/unique dex
|
1073 |
|
|
RegAddr_us_Dex <= -- C_REGS_BASE_ADDR(C_DECODE_BIT_TOP downto C_DECODE_BIT_BOT) & ,(C_DECODE_BIT_BOT-2)
|
1074 |
|
|
-- CONV_STD_LOGIC_VECTOR(CINT_ADDR_DMA_US_PAH, C_DECODE_BIT_BOT) & "00";
|
1075 |
|
|
CONV_STD_LOGIC_VECTOR(CINT_ADDR_DMA_US_PAH-1, C_DECODE_BIT_BOT) & "00";
|
1076 |
|
|
end if;
|
1077 |
|
|
|
1078 |
|
|
|
1079 |
|
|
if CplD_Tag(C_TAG_WIDTH-1 downto C_TAG_WIDTH-C_TAG_DECODE_BITS)/=C_TAG0_DMA_DSB(C_TAG_WIDTH-1 downto C_TAG_WIDTH-C_TAG_DECODE_BITS) then
|
1080 |
|
|
RegAddr_ds_Dex <= (Others=>'1');
|
1081 |
|
|
elsif CplD_is_the_Last = '1' then -- ds last/2nd dex
|
1082 |
|
|
RegAddr_ds_Dex <= Reg_WrAddr_if_last_ds;
|
1083 |
|
|
else -- ds 1st/unique dex
|
1084 |
|
|
RegAddr_ds_Dex <= -- C_REGS_BASE_ADDR(C_DECODE_BIT_TOP downto C_DECODE_BIT_BOT) & ,(C_DECODE_BIT_BOT-2)
|
1085 |
|
|
-- CONV_STD_LOGIC_VECTOR(CINT_ADDR_DMA_DS_PAH, C_DECODE_BIT_BOT) & "00";
|
1086 |
|
|
CONV_STD_LOGIC_VECTOR(CINT_ADDR_DMA_DS_PAH-1, C_DECODE_BIT_BOT) & "00";
|
1087 |
|
|
end if;
|
1088 |
|
|
|
1089 |
|
|
|
1090 |
|
|
end if;
|
1091 |
|
|
end process;
|
1092 |
|
|
|
1093 |
|
|
|
1094 |
|
|
|
1095 |
|
|
-- ---------------------------------------------
|
1096 |
|
|
-- Reg Synchronous Delay: CplD_Tag_on_Dex
|
1097 |
|
|
--
|
1098 |
|
|
RxFSM_Delay_CplD_Tag_on_Dex:
|
1099 |
|
|
process ( trn_clk, Local_Reset_i)
|
1100 |
|
|
begin
|
1101 |
|
|
if Local_Reset_i = '1' then
|
1102 |
|
|
CplD_Tag_on_Dex <= '0';
|
1103 |
|
|
|
1104 |
|
|
elsif trn_clk'event and trn_clk = '1' then
|
1105 |
|
|
|
1106 |
|
|
if CplD_Tag(C_TAG_WIDTH-1 downto C_TAG_WIDTH-C_TAG_DECODE_BITS)=C_TAG0_DMA_USB(C_TAG_WIDTH-1 downto C_TAG_WIDTH-C_TAG_DECODE_BITS) then
|
1107 |
|
|
CplD_Tag_on_Dex <= '1';
|
1108 |
|
|
elsif CplD_Tag(C_TAG_WIDTH-1 downto C_TAG_WIDTH-C_TAG_DECODE_BITS)=C_TAG0_DMA_DSB(C_TAG_WIDTH-1 downto C_TAG_WIDTH-C_TAG_DECODE_BITS) then
|
1109 |
|
|
CplD_Tag_on_Dex <= '1';
|
1110 |
|
|
else
|
1111 |
|
|
CplD_Tag_on_Dex <= '0';
|
1112 |
|
|
end if;
|
1113 |
|
|
|
1114 |
|
|
end if;
|
1115 |
|
|
end process;
|
1116 |
|
|
|
1117 |
|
|
|
1118 |
|
|
-------------------------------------------------------
|
1119 |
|
|
-- Synchronous outputs: DMA_Registers
|
1120 |
|
|
--
|
1121 |
|
|
RxFSM_Output_DMA_Registers:
|
1122 |
|
|
process ( trn_clk, Local_Reset_i)
|
1123 |
|
|
begin
|
1124 |
|
|
if Local_Reset_i = '1' then
|
1125 |
|
|
Regs_WrEn_i <= '0';
|
1126 |
|
|
Regs_WrMask_i <= (OTHERS=>'0');
|
1127 |
|
|
Regs_WrDin_i <= (OTHERS => '0');
|
1128 |
|
|
|
1129 |
|
|
elsif trn_clk'event and trn_clk = '1' then
|
1130 |
|
|
|
1131 |
|
|
case RxCplDTrn_State is
|
1132 |
|
|
|
1133 |
|
|
when ST_CplD_AFetch =>
|
1134 |
|
|
if CplD_Tag_on_Dex='1' then
|
1135 |
|
|
Regs_WrEn_i <= '1';
|
1136 |
|
|
Regs_WrMask_i <= "10";
|
1137 |
|
|
Regs_WrDin_i <= trn_rd_Little_r1;
|
1138 |
|
|
else
|
1139 |
|
|
Regs_WrEn_i <= '0';
|
1140 |
|
|
Regs_WrMask_i <= (OTHERS=>'0');
|
1141 |
|
|
Regs_WrDin_i <= (Others=>'0');
|
1142 |
|
|
end if;
|
1143 |
|
|
|
1144 |
|
|
when ST_CplD_AFetch_Special =>
|
1145 |
|
|
if CplD_Tag_on_Dex='1' then
|
1146 |
|
|
Regs_WrEn_i <= '1';
|
1147 |
|
|
Regs_WrMask_i <= "10";
|
1148 |
|
|
Regs_WrDin_i <= trn_rd_Little_r1;
|
1149 |
|
|
else
|
1150 |
|
|
Regs_WrEn_i <= '0';
|
1151 |
|
|
Regs_WrMask_i <= (OTHERS=>'0');
|
1152 |
|
|
Regs_WrDin_i <= (Others=>'0');
|
1153 |
|
|
end if;
|
1154 |
|
|
|
1155 |
|
|
when ST_CplD_1ST_DATA =>
|
1156 |
|
|
if CplD_Tag_on_Dex='1' then
|
1157 |
|
|
Regs_WrEn_i <= '1';
|
1158 |
|
|
Regs_WrMask_i <= (OTHERS=>'0');
|
1159 |
|
|
Regs_WrDin_i <= trn_rd_Little_r1;
|
1160 |
|
|
else
|
1161 |
|
|
Regs_WrEn_i <= '0';
|
1162 |
|
|
Regs_WrMask_i <= (OTHERS=>'0');
|
1163 |
|
|
Regs_WrDin_i <= (Others=>'0');
|
1164 |
|
|
end if;
|
1165 |
|
|
|
1166 |
|
|
when ST_CplD_ONLY_1DW =>
|
1167 |
|
|
if CplD_Tag_on_Dex='1' then
|
1168 |
|
|
Regs_WrEn_i <= '1';
|
1169 |
|
|
Regs_WrMask_i <= (OTHERS=>'0');
|
1170 |
|
|
Regs_WrDin_i <= trn_rd_Little_r1;
|
1171 |
|
|
else
|
1172 |
|
|
Regs_WrEn_i <= '0';
|
1173 |
|
|
Regs_WrMask_i <= (OTHERS=>'0');
|
1174 |
|
|
Regs_WrDin_i <= (Others=>'0');
|
1175 |
|
|
end if;
|
1176 |
|
|
|
1177 |
|
|
when ST_CplD_DATA =>
|
1178 |
|
|
if CplD_Tag_on_Dex='1' then
|
1179 |
|
|
Regs_WrEn_i <= '1';
|
1180 |
|
|
Regs_WrMask_i <= '0' & (trn_rrem_n_r1(3) or trn_rrem_n_r1(0));
|
1181 |
|
|
Regs_WrDin_i <= trn_rd_Little_r1;
|
1182 |
|
|
else
|
1183 |
|
|
Regs_WrEn_i <= '0';
|
1184 |
|
|
Regs_WrMask_i <= (OTHERS=>'0');
|
1185 |
|
|
Regs_WrDin_i <= (Others=>'0');
|
1186 |
|
|
end if;
|
1187 |
|
|
|
1188 |
|
|
when ST_CplD_LAST_DATA =>
|
1189 |
|
|
if CplD_Tag_on_Dex='1' then
|
1190 |
|
|
Regs_WrEn_i <= '1';
|
1191 |
|
|
Regs_WrMask_i <= '0' & (trn_rrem_n_r1(3) or trn_rrem_n_r1(0));
|
1192 |
|
|
Regs_WrDin_i <= trn_rd_Little_r1;
|
1193 |
|
|
else
|
1194 |
|
|
Regs_WrEn_i <= '0';
|
1195 |
|
|
Regs_WrMask_i <= (OTHERS=>'0');
|
1196 |
|
|
Regs_WrDin_i <= (Others=>'0');
|
1197 |
|
|
end if;
|
1198 |
|
|
|
1199 |
|
|
when OTHERS =>
|
1200 |
|
|
Regs_WrEn_i <= '0';
|
1201 |
|
|
Regs_WrMask_i <= (OTHERS=>'0');
|
1202 |
|
|
Regs_WrDin_i <= (Others=>'0');
|
1203 |
|
|
|
1204 |
|
|
end case;
|
1205 |
|
|
|
1206 |
|
|
end if;
|
1207 |
|
|
end process;
|
1208 |
|
|
|
1209 |
|
|
|
1210 |
|
|
-------------------------------------------------------
|
1211 |
|
|
-- Synchronous outputs: DMA_Registers write Address
|
1212 |
|
|
--
|
1213 |
|
|
RxFSM_Output_DMA_Registers_WrAddr:
|
1214 |
|
|
process ( trn_clk, Local_Reset_i)
|
1215 |
|
|
begin
|
1216 |
|
|
if Local_Reset_i = '1' then
|
1217 |
|
|
Regs_WrAddr_i <= (OTHERS => '1');
|
1218 |
|
|
|
1219 |
|
|
elsif trn_clk'event and trn_clk = '1' then
|
1220 |
|
|
|
1221 |
|
|
case RxCplDTrn_State is
|
1222 |
|
|
|
1223 |
|
|
when ST_CplD_IDLE =>
|
1224 |
|
|
Regs_WrAddr_i <= (OTHERS => '1');
|
1225 |
|
|
|
1226 |
|
|
when ST_CplD_AFetch =>
|
1227 |
|
|
Regs_WrAddr_i <= RegAddr_us_Dex and RegAddr_ds_Dex;
|
1228 |
|
|
|
1229 |
|
|
when ST_CplD_AFetch_Special =>
|
1230 |
|
|
Regs_WrAddr_i <= RegAddr_us_Dex and RegAddr_ds_Dex;
|
1231 |
|
|
|
1232 |
|
|
when ST_CplD_1ST_DATA =>
|
1233 |
|
|
Regs_WrAddr_i(C_DECODE_BIT_BOT-1 downto 0)
|
1234 |
|
|
<= Regs_WrAddr_i(C_DECODE_BIT_BOT-1 downto 0) + CONV_STD_LOGIC_VECTOR(8, C_DECODE_BIT_BOT);
|
1235 |
|
|
|
1236 |
|
|
when ST_CplD_ONLY_1DW =>
|
1237 |
|
|
Regs_WrAddr_i(C_DECODE_BIT_BOT-1 downto 0)
|
1238 |
|
|
<= Regs_WrAddr_i(C_DECODE_BIT_BOT-1 downto 0) + CONV_STD_LOGIC_VECTOR(8, C_DECODE_BIT_BOT);
|
1239 |
|
|
|
1240 |
|
|
when ST_CplD_DATA =>
|
1241 |
|
|
Regs_WrAddr_i(C_DECODE_BIT_BOT-1 downto 0)
|
1242 |
|
|
<= Regs_WrAddr_i(C_DECODE_BIT_BOT-1 downto 0) + CONV_STD_LOGIC_VECTOR(8, C_DECODE_BIT_BOT);
|
1243 |
|
|
|
1244 |
|
|
when ST_CplD_LAST_DATA =>
|
1245 |
|
|
Regs_WrAddr_i(C_DECODE_BIT_BOT-1 downto 0)
|
1246 |
|
|
<= Regs_WrAddr_i(C_DECODE_BIT_BOT-1 downto 0) + CONV_STD_LOGIC_VECTOR(8, C_DECODE_BIT_BOT);
|
1247 |
|
|
|
1248 |
|
|
when OTHERS =>
|
1249 |
|
|
Regs_WrAddr_i <= Regs_WrAddr_i;
|
1250 |
|
|
|
1251 |
|
|
end case;
|
1252 |
|
|
|
1253 |
|
|
end if;
|
1254 |
|
|
end process;
|
1255 |
|
|
|
1256 |
|
|
|
1257 |
|
|
|
1258 |
|
|
-----------------------------------------------------
|
1259 |
|
|
-- Synchronous Register:
|
1260 |
|
|
-- dsDMA_dex_Tag_i
|
1261 |
|
|
-- usDMA_dex_Tag_i
|
1262 |
|
|
--
|
1263 |
|
|
FSM_Reg_DMA_dex_Tags:
|
1264 |
|
|
process ( trn_clk, Local_Reset_i)
|
1265 |
|
|
begin
|
1266 |
|
|
if Local_Reset_i = '1' then
|
1267 |
|
|
usDMA_dex_Tag_i <= C_TAG0_DMA_USB;
|
1268 |
|
|
dsDMA_dex_Tag_i <= C_TAG0_DMA_DSB;
|
1269 |
|
|
|
1270 |
|
|
elsif trn_clk'event and trn_clk = '1' then
|
1271 |
|
|
|
1272 |
|
|
case RxCplDTrn_State is
|
1273 |
|
|
|
1274 |
|
|
when ST_CplD_AFetch =>
|
1275 |
|
|
|
1276 |
|
|
if trn_rd_r1(C_CPLD_TAG_BIT_TOP downto C_CPLD_TAG_BIT_BOT)=usDMA_dex_Tag_i and CplD_is_the_Last = '1' then
|
1277 |
|
|
usDMA_dex_Tag_i(C_TAG_WIDTH-C_TAG_DECODE_BITS-1 downto 0) <= usDMA_dex_Tag_i(C_TAG_WIDTH-C_TAG_DECODE_BITS-1 downto 0) + X"1";
|
1278 |
|
|
else
|
1279 |
|
|
usDMA_dex_Tag_i <= usDMA_dex_Tag_i;
|
1280 |
|
|
end if;
|
1281 |
|
|
|
1282 |
|
|
if trn_rd_r1(C_CPLD_TAG_BIT_TOP downto C_CPLD_TAG_BIT_BOT)=dsDMA_dex_Tag_i and CplD_is_the_Last = '1' then
|
1283 |
|
|
dsDMA_dex_Tag_i(C_TAG_WIDTH-C_TAG_DECODE_BITS-1 downto 0) <= dsDMA_dex_Tag_i(C_TAG_WIDTH-C_TAG_DECODE_BITS-1 downto 0) + X"1";
|
1284 |
|
|
else
|
1285 |
|
|
dsDMA_dex_Tag_i <= dsDMA_dex_Tag_i;
|
1286 |
|
|
end if;
|
1287 |
|
|
|
1288 |
|
|
when ST_CplD_AFetch_Special =>
|
1289 |
|
|
|
1290 |
|
|
if trn_rd_r1(C_CPLD_TAG_BIT_TOP downto C_CPLD_TAG_BIT_BOT)=usDMA_dex_Tag_i and CplD_is_the_Last = '1' then
|
1291 |
|
|
usDMA_dex_Tag_i(C_TAG_WIDTH-C_TAG_DECODE_BITS-1 downto 0) <= usDMA_dex_Tag_i(C_TAG_WIDTH-C_TAG_DECODE_BITS-1 downto 0) + X"1";
|
1292 |
|
|
else
|
1293 |
|
|
usDMA_dex_Tag_i <= usDMA_dex_Tag_i;
|
1294 |
|
|
end if;
|
1295 |
|
|
|
1296 |
|
|
if trn_rd_r1(C_CPLD_TAG_BIT_TOP downto C_CPLD_TAG_BIT_BOT)=dsDMA_dex_Tag_i and CplD_is_the_Last = '1' then
|
1297 |
|
|
dsDMA_dex_Tag_i(C_TAG_WIDTH-C_TAG_DECODE_BITS-1 downto 0) <= dsDMA_dex_Tag_i(C_TAG_WIDTH-C_TAG_DECODE_BITS-1 downto 0) + X"1";
|
1298 |
|
|
else
|
1299 |
|
|
dsDMA_dex_Tag_i <= dsDMA_dex_Tag_i;
|
1300 |
|
|
end if;
|
1301 |
|
|
|
1302 |
|
|
when Others =>
|
1303 |
|
|
usDMA_dex_Tag_i <= usDMA_dex_Tag_i;
|
1304 |
|
|
dsDMA_dex_Tag_i <= dsDMA_dex_Tag_i;
|
1305 |
|
|
|
1306 |
|
|
end case;
|
1307 |
|
|
|
1308 |
|
|
end if;
|
1309 |
|
|
end process;
|
1310 |
|
|
|
1311 |
|
|
|
1312 |
|
|
-- -------------------------------------------------------------
|
1313 |
|
|
-- RAM holding downstream Tags of packet MRd requests
|
1314 |
|
|
-- -------------------------------------------------------------
|
1315 |
|
|
|
1316 |
|
|
tRAM_addra <= CplD_Tag(C_TAGRAM_AWIDTH-1 downto 0);
|
1317 |
|
|
tRAM_weB_i(0) <= tRAM_weB;
|
1318 |
|
|
|
1319 |
|
|
dspTag_BRAM:
|
1320 |
|
|
FF_TagRam64x36
|
1321 |
|
|
port map(
|
1322 |
|
|
clk => trn_clk ,
|
1323 |
|
|
|
1324 |
|
|
wea => tRAM_wea(0) ,
|
1325 |
|
|
addra => tRAM_addra ,
|
1326 |
|
|
dina => tRAM_dina ,
|
1327 |
|
|
douta => tRAM_doutA ,
|
1328 |
|
|
|
1329 |
|
|
web => tRAM_weB_i(0) ,
|
1330 |
|
|
addrb => tRAM_addrB ,
|
1331 |
|
|
dinb => tRAM_dinB ,
|
1332 |
|
|
doutb => open
|
1333 |
|
|
);
|
1334 |
|
|
|
1335 |
|
|
|
1336 |
|
|
-- dspTag_BRAM:
|
1337 |
|
|
-- v5tagram64x36
|
1338 |
|
|
-- port map(
|
1339 |
|
|
-- clka => trn_clk ,
|
1340 |
|
|
-- addra => tRAM_addra ,
|
1341 |
|
|
-- wea => tRAM_wea ,
|
1342 |
|
|
-- dina => tRAM_dina ,
|
1343 |
|
|
-- douta => tRAM_doutA ,
|
1344 |
|
|
-- clkb => trn_clk ,
|
1345 |
|
|
-- addrb => tRAM_addrB ,
|
1346 |
|
|
-- web => tRAM_weB_i ,
|
1347 |
|
|
-- dinb => tRAM_dinB ,
|
1348 |
|
|
-- doutb => open
|
1349 |
|
|
-- );
|
1350 |
|
|
|
1351 |
|
|
|
1352 |
|
|
-- -----------------------------------------------------------------------------------
|
1353 |
|
|
-- Synchronous delay: CplD_is_the_Last
|
1354 |
|
|
--
|
1355 |
|
|
Syn_Delay_CplD_is_the_Last:
|
1356 |
|
|
process ( trn_clk )
|
1357 |
|
|
begin
|
1358 |
|
|
if trn_clk'event and trn_clk = '1' then
|
1359 |
|
|
CplD_is_the_Last_r1 <= CplD_is_the_Last;
|
1360 |
|
|
CplD_is_the_Last_r2 <= CplD_is_the_Last_r1;
|
1361 |
|
|
end if;
|
1362 |
|
|
end process;
|
1363 |
|
|
|
1364 |
|
|
-- -----------------------------------------------------------------------------------
|
1365 |
|
|
-- Synchronous output: Updates_tRAM
|
1366 |
|
|
-- Update happens only at data TLP
|
1367 |
|
|
-- The last CplD of one MRd does not trigger tRAM update,
|
1368 |
|
|
-- to enable back-to-back transactions.
|
1369 |
|
|
--
|
1370 |
|
|
RxFSM_Output_Updates_tRAM:
|
1371 |
|
|
process ( trn_clk, Local_Reset_i)
|
1372 |
|
|
begin
|
1373 |
|
|
if Local_Reset_i = '1' then
|
1374 |
|
|
Updates_tRAM <= '0';
|
1375 |
|
|
|
1376 |
|
|
elsif trn_clk'event and trn_clk = '1' then
|
1377 |
|
|
|
1378 |
|
|
Updates_tRAM <= CplD_State_is_AFetch
|
1379 |
|
|
and DSP_Tag_on_RAM_r1
|
1380 |
|
|
and not CplD_is_the_Last_r2
|
1381 |
|
|
;
|
1382 |
|
|
|
1383 |
|
|
end if;
|
1384 |
|
|
end process;
|
1385 |
|
|
|
1386 |
|
|
|
1387 |
|
|
-- -----------------------------------------------------------------------------------
|
1388 |
|
|
-- Synchronous output: Update_was_too_late
|
1389 |
|
|
-- For 1DW CplD the update might be too late for the
|
1390 |
|
|
-- next CplD with the same TAG
|
1391 |
|
|
--
|
1392 |
|
|
RxFSM_Output_Update_was_too_late:
|
1393 |
|
|
process ( trn_clk, Local_Reset_i)
|
1394 |
|
|
begin
|
1395 |
|
|
if Local_Reset_i = '1' then
|
1396 |
|
|
Update_was_too_late <= '0';
|
1397 |
|
|
-- hazard_tag <= (OTHERS=>'1');
|
1398 |
|
|
tag_matches_hazard <= '0';
|
1399 |
|
|
tag_matches_hazard_r1 <= '0';
|
1400 |
|
|
tag_matches_hazard_r2 <= '0';
|
1401 |
|
|
hazard_update <= '0';
|
1402 |
|
|
hazard_update_r1 <= '0';
|
1403 |
|
|
hazard_update_r2 <= '0';
|
1404 |
|
|
hazard_update_r3 <= '0';
|
1405 |
|
|
elsif trn_clk'event and trn_clk = '1' then
|
1406 |
|
|
|
1407 |
|
|
if (Small_CplD='1' or Small_CplD_r1='1')
|
1408 |
|
|
----?? and (CplD_State_is_after_AFetch='1' or CplD_State_is_after_AFetch_r1='1')
|
1409 |
|
|
and (CplD_State_is_AFetch='1')
|
1410 |
|
|
and CplD_Tag_on_Dex='0'
|
1411 |
|
|
then
|
1412 |
|
|
hazard_update <= '1';
|
1413 |
|
|
else
|
1414 |
|
|
hazard_update <= '0';
|
1415 |
|
|
end if;
|
1416 |
|
|
|
1417 |
|
|
hazard_update_r1 <= hazard_update;
|
1418 |
|
|
hazard_update_r2 <= hazard_update_r1;
|
1419 |
|
|
hazard_update_r3 <= hazard_update_r2;
|
1420 |
|
|
|
1421 |
|
|
-- Update_was_too_late <= hazard_update_r1 or hazard_update_r2 or hazard_update_r3;
|
1422 |
|
|
Update_was_too_late <= hazard_update or hazard_update_r1 or hazard_update_r2 or hazard_update_r3;
|
1423 |
|
|
|
1424 |
|
|
|
1425 |
|
|
|
1426 |
|
|
if trn_rsof_n_i='1' and trn_rsof_n_r1='0' then
|
1427 |
|
|
if trn_rd_r1(C_TLP_FMT_BIT_TOP downto C_TLP_FMT_BIT_BOT) ="10"
|
1428 |
|
|
and trn_rd_r1(C_TLP_TYPE_BIT_TOP downto C_TLP_TYPE_BIT_TOP-1) ="01"
|
1429 |
|
|
then
|
1430 |
|
|
curr_tag_latch <= CplD_Tag;
|
1431 |
|
|
if CplD_Tag=curr_tag_latch then
|
1432 |
|
|
tag_matches_hazard <= '1';
|
1433 |
|
|
else
|
1434 |
|
|
tag_matches_hazard <= '0';
|
1435 |
|
|
end if;
|
1436 |
|
|
else
|
1437 |
|
|
curr_tag_latch <= (OTHERS=>'1');
|
1438 |
|
|
end if;
|
1439 |
|
|
else
|
1440 |
|
|
curr_tag_latch <= curr_tag_latch;
|
1441 |
|
|
end if;
|
1442 |
|
|
|
1443 |
|
|
tag_matches_hazard_r1 <= tag_matches_hazard;
|
1444 |
|
|
tag_matches_hazard_r2 <= tag_matches_hazard_r1;
|
1445 |
|
|
|
1446 |
|
|
|
1447 |
|
|
-- if DDR_Space_Hit='0' then
|
1448 |
|
|
-- hazard_tag <= (OTHERS=>'1');
|
1449 |
|
|
-- elsif CplD_State_is_after_AFetch='1' then
|
1450 |
|
|
-- hazard_tag <= curr_tag_latch; -- CplD_Tag_r1;
|
1451 |
|
|
-- else
|
1452 |
|
|
-- hazard_tag <= hazard_tag;
|
1453 |
|
|
-- end if;
|
1454 |
|
|
--
|
1455 |
|
|
-- if trn_rsof_n_i='1' and trn_rsof_n_r1='0' then
|
1456 |
|
|
-- if trn_rd_r1(C_TLP_FMT_BIT_TOP downto C_TLP_FMT_BIT_BOT) ="10"
|
1457 |
|
|
-- and trn_rd_r1(C_TLP_TYPE_BIT_TOP downto C_TLP_TYPE_BIT_TOP-1) ="01"
|
1458 |
|
|
-- then
|
1459 |
|
|
-- curr_tag_latch <= CplD_Tag;
|
1460 |
|
|
-- else
|
1461 |
|
|
-- curr_tag_latch <= (OTHERS=>'1');
|
1462 |
|
|
-- end if;
|
1463 |
|
|
-- else
|
1464 |
|
|
-- curr_tag_latch <= curr_tag_latch;
|
1465 |
|
|
-- end if;
|
1466 |
|
|
--
|
1467 |
|
|
-- if CplD_Tag=hazard_tag then
|
1468 |
|
|
-- tag_matches_hazard <= '1';
|
1469 |
|
|
-- else
|
1470 |
|
|
-- tag_matches_hazard <= '0';
|
1471 |
|
|
-- end if;
|
1472 |
|
|
|
1473 |
|
|
end if;
|
1474 |
|
|
end process;
|
1475 |
|
|
|
1476 |
|
|
|
1477 |
|
|
-- ---------------------------------------------
|
1478 |
|
|
-- Delay Synchronous Delay: Updates_tRAM
|
1479 |
|
|
--
|
1480 |
|
|
RxFSM_Delay_Updates_tRAM:
|
1481 |
|
|
process ( trn_clk )
|
1482 |
|
|
begin
|
1483 |
|
|
if trn_clk'event and trn_clk = '1' then
|
1484 |
|
|
Updates_tRAM_r1 <= Updates_tRAM;
|
1485 |
|
|
end if;
|
1486 |
|
|
end process;
|
1487 |
|
|
|
1488 |
|
|
|
1489 |
|
|
-- ---------------------------------------------
|
1490 |
|
|
-- Synchronous Delay: tRAM_DoutA_r2
|
1491 |
|
|
--
|
1492 |
|
|
Delay_tRAM_DoutA:
|
1493 |
|
|
process ( trn_clk )
|
1494 |
|
|
begin
|
1495 |
|
|
if trn_clk'event and trn_clk = '1' then
|
1496 |
|
|
|
1497 |
|
|
---- if CplD_State_is_AFetch='1' then -- [ avoid confilict in simulation, can be removed ]
|
1498 |
|
|
-- if TLB_Hit='1'
|
1499 |
|
|
-- and TLB_Valid='1' -- [ only for simulation. can be removed for imp.]
|
1500 |
|
|
-- then
|
1501 |
|
|
-- tRAM_DoutA_r1 <= TLB_Content;
|
1502 |
|
|
-- else
|
1503 |
|
|
-- tRAM_DoutA_r1 <= tRAM_doutA;
|
1504 |
|
|
-- end if;
|
1505 |
|
|
---- else
|
1506 |
|
|
---- tRAM_DoutA_r1 <= tRAM_DoutA_r1;
|
1507 |
|
|
---- end if;
|
1508 |
|
|
|
1509 |
|
|
if Update_was_too_late='1' and tag_matches_hazard='1' then
|
1510 |
|
|
tRAM_DoutA_r1 <= hazard_content;
|
1511 |
|
|
else
|
1512 |
|
|
tRAM_DoutA_r1 <= tRAM_doutA;
|
1513 |
|
|
end if;
|
1514 |
|
|
-- tRAM_DoutA_r1 <= tRAM_doutA;
|
1515 |
|
|
tRAM_DoutA_r2 <= tRAM_DoutA_r1;
|
1516 |
|
|
|
1517 |
|
|
end if;
|
1518 |
|
|
end process;
|
1519 |
|
|
|
1520 |
|
|
|
1521 |
|
|
-- ---------------------------------------------
|
1522 |
|
|
-- Synchronous Output: hazard_content
|
1523 |
|
|
--
|
1524 |
|
|
Syn_Reg_hazard_content:
|
1525 |
|
|
process ( trn_clk, Local_Reset_i)
|
1526 |
|
|
begin
|
1527 |
|
|
if Local_Reset_i = '1' then
|
1528 |
|
|
hazard_content <= (OTHERS =>'1');
|
1529 |
|
|
elsif trn_clk'event and trn_clk = '1' then
|
1530 |
|
|
if tRAM_wea(0)='1' then
|
1531 |
|
|
hazard_content <= tRAM_dina;
|
1532 |
|
|
else
|
1533 |
|
|
hazard_content <= hazard_content;
|
1534 |
|
|
end if;
|
1535 |
|
|
end if;
|
1536 |
|
|
end process;
|
1537 |
|
|
|
1538 |
|
|
|
1539 |
|
|
-- ---------------------------------------------
|
1540 |
|
|
-- Synchronous Calculation: tRAM_dina_aInc
|
1541 |
|
|
--
|
1542 |
|
|
Syn_Calc_tRAM_dina_aInc:
|
1543 |
|
|
process ( trn_clk, Local_Reset_i)
|
1544 |
|
|
begin
|
1545 |
|
|
if Local_Reset_i = '1' then
|
1546 |
|
|
tRAM_dina_aInc <= (CBIT_AINC_IN_TAGRAM=>'1',
|
1547 |
|
|
OTHERS =>'0'
|
1548 |
|
|
);
|
1549 |
|
|
elsif trn_clk'event and trn_clk = '1' then
|
1550 |
|
|
tRAM_dina_aInc(C_TAGBAR_BIT_TOP downto C_TAGBAR_BIT_BOT)
|
1551 |
|
|
<= tRAM_DoutA_r1(C_TAGBAR_BIT_TOP downto C_TAGBAR_BIT_BOT);
|
1552 |
|
|
tRAM_dina_aInc(C_TAGBAR_BIT_BOT-1 downto 0) --C_EP_AWIDTH !!!!!
|
1553 |
|
|
<= tRAM_DoutA_r1(C_TAGBAR_BIT_BOT-1 downto 0) --C_EP_AWIDTH !!!!!
|
1554 |
|
|
+ CplD_Leng_in_Bytes_r2(C_TLP_FLD_WIDTH_OF_LENG+2 downto 0) ;
|
1555 |
|
|
end if;
|
1556 |
|
|
end process;
|
1557 |
|
|
|
1558 |
|
|
|
1559 |
|
|
tRAM_wea(0) <= Updates_tRAM_r1;
|
1560 |
|
|
tRAM_dina <= tRAM_dina_aInc;
|
1561 |
|
|
-- tRAM_dina <= ('1' & tRAM_dina_aInc(C_TAGRAM_DWIDTH-1-1 downto 0))
|
1562 |
|
|
-- when Addr_Inc='1'
|
1563 |
|
|
-- else ('0' & tRAM_DoutA_r2(C_TAGRAM_DWIDTH-1-1 downto 0));
|
1564 |
|
|
|
1565 |
|
|
|
1566 |
|
|
-- ---------------------------------------------
|
1567 |
|
|
-- Synchronous Calculation: tRAM_DoutA_latch
|
1568 |
|
|
--
|
1569 |
|
|
Syn_tRAM_DoutA_latch:
|
1570 |
|
|
process ( trn_clk, Local_Reset_i)
|
1571 |
|
|
begin
|
1572 |
|
|
if Local_Reset_i = '1' then
|
1573 |
|
|
tRAM_DoutA_latch <= (CBIT_AINC_IN_TAGRAM=>'1',OTHERS =>'0');
|
1574 |
|
|
elsif trn_clk'event and trn_clk = '1' then
|
1575 |
|
|
if CplD_State_is_AFetch_r1='0' then
|
1576 |
|
|
tRAM_DoutA_latch <= tRAM_DoutA_latch;
|
1577 |
|
|
elsif Update_was_too_late='0' then
|
1578 |
|
|
tRAM_DoutA_latch <= tRAM_DoutA;
|
1579 |
|
|
elsif tag_matches_hazard='1' then
|
1580 |
|
|
tRAM_DoutA_latch <= hazard_content;
|
1581 |
|
|
else
|
1582 |
|
|
tRAM_DoutA_latch <= tRAM_DoutA_r1;
|
1583 |
|
|
end if;
|
1584 |
|
|
end if;
|
1585 |
|
|
end process;
|
1586 |
|
|
|
1587 |
|
|
-- ---------------------------------------------
|
1588 |
|
|
-- Synchronous Output: TLB (not used)
|
1589 |
|
|
--
|
1590 |
|
|
Syn_Reg_TLB_Operation:
|
1591 |
|
|
process ( trn_clk, Local_Reset_i)
|
1592 |
|
|
begin
|
1593 |
|
|
if Local_Reset_i = '1' then
|
1594 |
|
|
TLB_Addr <= (OTHERS =>'1');
|
1595 |
|
|
TLB_Content <= (OTHERS =>'0');
|
1596 |
|
|
TLB_cnt <= (OTHERS =>'0');
|
1597 |
|
|
TLB_Valid <= '0';
|
1598 |
|
|
TLB_Hit <= '0';
|
1599 |
|
|
elsif trn_clk'event and trn_clk = '1' then
|
1600 |
|
|
|
1601 |
|
|
if Updates_tRAM_r1='0' then
|
1602 |
|
|
TLB_Content <= TLB_Content;
|
1603 |
|
|
TLB_Addr <= TLB_Addr;
|
1604 |
|
|
if TLB_cnt=C_ALL_ZEROS(3 downto 0) then
|
1605 |
|
|
TLB_cnt <= TLB_cnt;
|
1606 |
|
|
TLB_Valid <= '0';
|
1607 |
|
|
else
|
1608 |
|
|
TLB_cnt <= TLB_cnt - '1';
|
1609 |
|
|
TLB_Valid <= '1';
|
1610 |
|
|
end if;
|
1611 |
|
|
else
|
1612 |
|
|
TLB_Addr <= tRAM_addra;
|
1613 |
|
|
TLB_cnt <= C_TLB_VALID_CNT;
|
1614 |
|
|
TLB_Valid <= '0';
|
1615 |
|
|
if Addr_Inc='1' then
|
1616 |
|
|
TLB_Content <= '1' & tRAM_dina_aInc(C_TAGRAM_DWIDTH-1-1 downto 0);
|
1617 |
|
|
else
|
1618 |
|
|
TLB_Content <= '0' & tRAM_DoutA_r2(C_TAGRAM_DWIDTH-1-1 downto 0);
|
1619 |
|
|
end if;
|
1620 |
|
|
end if;
|
1621 |
|
|
|
1622 |
|
|
if TLB_Addr=tRAM_addra then
|
1623 |
|
|
TLB_Hit <= '1';
|
1624 |
|
|
else
|
1625 |
|
|
TLB_Hit <= '0';
|
1626 |
|
|
end if;
|
1627 |
|
|
|
1628 |
|
|
end if;
|
1629 |
|
|
end process;
|
1630 |
|
|
|
1631 |
|
|
|
1632 |
|
|
hybrid_rd <= trn_rd_r1(32-1 downto 0) & trn_rd_i(64-1 downto 32);
|
1633 |
|
|
|
1634 |
|
|
-- -------------------------------------------------
|
1635 |
|
|
-- Synchronous outputs: eb_FIFO_Write
|
1636 |
|
|
--
|
1637 |
|
|
RxFSM_Output_FIFO_Space_Hit:
|
1638 |
|
|
process ( trn_clk, Local_Reset_i)
|
1639 |
|
|
begin
|
1640 |
|
|
if Local_Reset_i = '1' then
|
1641 |
|
|
eb_FIFO_we_i <= '0';
|
1642 |
|
|
eb_FIFO_wsof_i <= '0';
|
1643 |
|
|
eb_FIFO_weof_i <= '0';
|
1644 |
|
|
eb_FIFO_sof_marker <= '0';
|
1645 |
|
|
eb_FIFO_din_i <= (OTHERS=>'0');
|
1646 |
|
|
EB_Write_State <= ST_EBWR_IDLE;
|
1647 |
|
|
|
1648 |
|
|
elsif trn_clk'event and trn_clk = '1' then
|
1649 |
|
|
|
1650 |
|
|
case EB_Write_State is
|
1651 |
|
|
|
1652 |
|
|
when ST_EBWR_IDLE =>
|
1653 |
|
|
eb_FIFO_we_i <= '0';
|
1654 |
|
|
eb_FIFO_wsof_i <= '0';
|
1655 |
|
|
eb_FIFO_weof_i <= '0';
|
1656 |
|
|
eb_FIFO_sof_marker <= '0';
|
1657 |
|
|
eb_FIFO_din_i <= (OTHERS=>'0');
|
1658 |
|
|
if trn_rx_throttle='0'
|
1659 |
|
|
and CplD_Type=C_TLP_TYPE_IS_CPLD
|
1660 |
|
|
and trn_rd_i(0)='0' -- Odd-DW CplD is illegal
|
1661 |
|
|
then
|
1662 |
|
|
EB_Write_State <= ST_EBWR_TAG;
|
1663 |
|
|
else
|
1664 |
|
|
EB_Write_State <= ST_EBWR_IDLE;
|
1665 |
|
|
end if;
|
1666 |
|
|
|
1667 |
|
|
when ST_EBWR_TAG =>
|
1668 |
|
|
eb_FIFO_we_i <= '0';
|
1669 |
|
|
eb_FIFO_wsof_i <= '0';
|
1670 |
|
|
eb_FIFO_weof_i <= '0';
|
1671 |
|
|
eb_FIFO_din_i <= (OTHERS=>'0');
|
1672 |
|
|
if trn_rsof_n_i='0' then
|
1673 |
|
|
eb_FIFO_sof_marker <= '0';
|
1674 |
|
|
EB_Write_State <= ST_EBWR_TAG;
|
1675 |
|
|
elsif trn_rx_throttle='0' and DSP_Tag_on_FIFO='1' then
|
1676 |
|
|
eb_FIFO_sof_marker <= '1';
|
1677 |
|
|
EB_Write_State <= ST_EBWR_DATA;
|
1678 |
|
|
else
|
1679 |
|
|
eb_FIFO_sof_marker <= '0';
|
1680 |
|
|
EB_Write_State <= ST_EBWR_IDLE;
|
1681 |
|
|
end if;
|
1682 |
|
|
|
1683 |
|
|
when ST_EBWR_DATA =>
|
1684 |
|
|
eb_FIFO_we_i <= not trn_rx_throttle;
|
1685 |
|
|
eb_FIFO_wsof_i <= eb_FIFO_sof_marker and not trn_rx_throttle;
|
1686 |
|
|
eb_FIFO_sof_marker <= eb_FIFO_sof_marker and trn_rx_throttle;
|
1687 |
|
|
eb_FIFO_din_i <= Endian_Invert_64(hybrid_rd);
|
1688 |
|
|
if trn_rx_throttle='0' and trn_reof_n_i='0' then
|
1689 |
|
|
eb_FIFO_weof_i <= '1';
|
1690 |
|
|
EB_Write_State <= ST_EBWR_IDLE;
|
1691 |
|
|
else
|
1692 |
|
|
eb_FIFO_weof_i <= '0';
|
1693 |
|
|
EB_Write_State <= ST_EBWR_DATA;
|
1694 |
|
|
end if;
|
1695 |
|
|
|
1696 |
|
|
|
1697 |
|
|
when OTHERS =>
|
1698 |
|
|
eb_FIFO_we_i <= '0';
|
1699 |
|
|
eb_FIFO_wsof_i <= '0';
|
1700 |
|
|
eb_FIFO_weof_i <= '0';
|
1701 |
|
|
eb_FIFO_sof_marker <= '0';
|
1702 |
|
|
eb_FIFO_din_i <= (OTHERS=>'0');
|
1703 |
|
|
EB_Write_State <= ST_EBWR_IDLE;
|
1704 |
|
|
|
1705 |
|
|
end case;
|
1706 |
|
|
|
1707 |
|
|
end if;
|
1708 |
|
|
end process;
|
1709 |
|
|
|
1710 |
|
|
|
1711 |
|
|
-- -------------------------------------------------
|
1712 |
|
|
-- Synchronous outputs: DDR_Space_Hit
|
1713 |
|
|
--
|
1714 |
|
|
RxFSM_Output_DDR_Space_Hit:
|
1715 |
|
|
process ( trn_clk, Local_Reset_i)
|
1716 |
|
|
begin
|
1717 |
|
|
if Local_Reset_i = '1' then
|
1718 |
|
|
DDR_Space_Hit <= '0';
|
1719 |
|
|
|
1720 |
|
|
elsif trn_clk'event and trn_clk = '1' then
|
1721 |
|
|
|
1722 |
|
|
if CplD_State_is_AFetch='1' then
|
1723 |
|
|
DDR_Space_Hit <= DSP_Tag_on_RAM and not TLP_is_not_CplD_r1;
|
1724 |
|
|
elsif trn_reof_n_r4='0' then
|
1725 |
|
|
DDR_Space_Hit <= '0';
|
1726 |
|
|
else
|
1727 |
|
|
DDR_Space_Hit <= DDR_Space_Hit;
|
1728 |
|
|
end if;
|
1729 |
|
|
|
1730 |
|
|
end if;
|
1731 |
|
|
end process;
|
1732 |
|
|
|
1733 |
|
|
|
1734 |
|
|
-- -------------------------------------------------
|
1735 |
|
|
-- Synchronous outputs: DDR write
|
1736 |
|
|
--
|
1737 |
|
|
RxFSM_Output_DDR_Write:
|
1738 |
|
|
process ( trn_clk, Local_Reset_i)
|
1739 |
|
|
begin
|
1740 |
|
|
if Local_Reset_i = '1' then
|
1741 |
|
|
DDR_wr_sof_i <= '0';
|
1742 |
|
|
DDR_wr_eof_i <= '0';
|
1743 |
|
|
DDR_wr_v_i <= '0';
|
1744 |
|
|
DDR_wr_FA_i <= '0';
|
1745 |
|
|
DDR_wr_void <= '1';
|
1746 |
|
|
DDR_wr_Shift_i <= '0';
|
1747 |
|
|
DDR_wr_Mask_i <= (OTHERS=>'0');
|
1748 |
|
|
DDR_wr_din_i <= (OTHERS=>'0');
|
1749 |
|
|
|
1750 |
|
|
elsif trn_clk'event and trn_clk = '1' then
|
1751 |
|
|
|
1752 |
|
|
if DDR_wr_eof_i='1' and (CplD_State_is_after_AFetch='1' and DSP_Tag_on_RAM_r1='1') then
|
1753 |
|
|
DDR_wr_void <= '0';
|
1754 |
|
|
elsif DDR_wr_eof_i='1' then
|
1755 |
|
|
DDR_wr_void <= '1';
|
1756 |
|
|
elsif CplD_State_is_after_AFetch='1' and DSP_Tag_on_RAM_r1='1' then
|
1757 |
|
|
DDR_wr_void <= '0';
|
1758 |
|
|
else
|
1759 |
|
|
DDR_wr_void <= DDR_wr_void;
|
1760 |
|
|
end if;
|
1761 |
|
|
|
1762 |
|
|
DDR_wr_sof_i <= DDR_Space_Hit and CplD_State_is_after_AFetch;
|
1763 |
|
|
|
1764 |
|
|
DDR_wr_eof_i <= (DDR_Space_Hit and not trn_reof_n_r4)
|
1765 |
|
|
or (CplD_State_is_AFetch and DSP_Tag_on_RAM_r4p and not TLP_is_not_CplD_r4 and not DSP_Tag_on_RAM_r1)
|
1766 |
|
|
;
|
1767 |
|
|
|
1768 |
|
|
if CplD_State_is_after_AFetch='1' then
|
1769 |
|
|
DDR_wr_v_i <= DDR_Space_Hit;
|
1770 |
|
|
elsif CplD_State_is_AFetch='1' then
|
1771 |
|
|
DDR_wr_v_i <= DSP_Tag_on_RAM_r4p and not TLP_is_not_CplD_r4 and not DDR_wr_eof_i and not DDR_wr_void;
|
1772 |
|
|
elsif DDR_Space_Hit='1' then
|
1773 |
|
|
DDR_wr_v_i <= (CplD_State_is_after_AFetch
|
1774 |
|
|
or not (trn_rx_throttle_r4 and trn_reof_n_r4)
|
1775 |
|
|
or DDR_wr_sof_i) and not DDR_wr_eof_i and not DDR_wr_void
|
1776 |
|
|
;
|
1777 |
|
|
else
|
1778 |
|
|
DDR_wr_v_i <= '0';
|
1779 |
|
|
end if;
|
1780 |
|
|
|
1781 |
|
|
if CplD_State_is_after_AFetch='1' and DDR_Space_Hit='1' then
|
1782 |
|
|
if Update_was_too_late='1' and tag_matches_hazard_r2='1' then
|
1783 |
|
|
DDR_wr_din_i <= CplD_Leng_in_Bytes_r2(C_DBUS_WIDTH/2-1 downto 0) & hazard_content(C_DBUS_WIDTH/2-1 downto 0);
|
1784 |
|
|
elsif CplD_State_is_AFetch_r1 = '0' then
|
1785 |
|
|
DDR_wr_din_i <= CplD_Leng_in_Bytes_r2(C_DBUS_WIDTH/2-1 downto 0) & tRAM_DoutA_latch(C_DBUS_WIDTH/2-1 downto 0);
|
1786 |
|
|
else
|
1787 |
|
|
DDR_wr_din_i <= CplD_Leng_in_Bytes_r2(C_DBUS_WIDTH/2-1 downto 0) & tRAM_DoutA_r1(C_DBUS_WIDTH/2-1 downto 0);
|
1788 |
|
|
end if;
|
1789 |
|
|
elsif DDR_Space_Hit='1' then
|
1790 |
|
|
DDR_wr_din_i <= trn_rd_Little_r4;
|
1791 |
|
|
else
|
1792 |
|
|
DDR_wr_din_i <= (OTHERS=>'0');
|
1793 |
|
|
end if;
|
1794 |
|
|
|
1795 |
|
|
if CplD_State_is_after_AFetch='1' and DDR_Space_Hit='1' then
|
1796 |
|
|
if Update_was_too_late='1' and tag_matches_hazard_r2='1' then
|
1797 |
|
|
DDR_wr_Shift_i <= not hazard_content(2);
|
1798 |
|
|
elsif CplD_State_is_AFetch_r1 = '0' then
|
1799 |
|
|
DDR_wr_Shift_i <= not tRAM_DoutA_latch(2);
|
1800 |
|
|
else
|
1801 |
|
|
DDR_wr_Shift_i <= not tRAM_DoutA_r1(2);
|
1802 |
|
|
end if;
|
1803 |
|
|
else
|
1804 |
|
|
DDR_wr_Shift_i <= '0';
|
1805 |
|
|
end if;
|
1806 |
|
|
|
1807 |
|
|
if DDR_wr_sof_i='1' then
|
1808 |
|
|
DDR_wr_Mask_i <= "10";
|
1809 |
|
|
else
|
1810 |
|
|
DDR_wr_Mask_i <= '0' & (trn_rrem_n_r4(3) or trn_rrem_n_r4(0));
|
1811 |
|
|
end if;
|
1812 |
|
|
|
1813 |
|
|
end if;
|
1814 |
|
|
end process;
|
1815 |
|
|
|
1816 |
|
|
|
1817 |
|
|
end architecture Behavioral;
|