1 |
2 |
weng_ziti |
----------------------------------------------------------------------------------
|
2 |
|
|
-- Company: ziti, Uni. HD
|
3 |
|
|
-- Engineer: wgao
|
4 |
|
|
--
|
5 |
|
|
-- Design Name:
|
6 |
|
|
-- Module Name: rx_MWr_Transact - Behavioral
|
7 |
|
|
-- Project Name:
|
8 |
|
|
-- Target Devices:
|
9 |
|
|
-- Tool versions:
|
10 |
|
|
-- Description:
|
11 |
|
|
--
|
12 |
|
|
-- Dependencies:
|
13 |
|
|
--
|
14 |
|
|
-- Revision 1.00 - first release. 14.12.2006
|
15 |
|
|
--
|
16 |
|
|
-- Additional Comments:
|
17 |
|
|
--
|
18 |
|
|
----------------------------------------------------------------------------------
|
19 |
|
|
|
20 |
|
|
library IEEE;
|
21 |
|
|
use IEEE.STD_LOGIC_1164.ALL;
|
22 |
|
|
use IEEE.STD_LOGIC_ARITH.ALL;
|
23 |
|
|
use IEEE.STD_LOGIC_UNSIGNED.ALL;
|
24 |
|
|
|
25 |
|
|
library work;
|
26 |
|
|
use work.abb64Package.all;
|
27 |
|
|
|
28 |
|
|
-- Uncomment the following library declaration if instantiating
|
29 |
|
|
-- any Xilinx primitives in this code.
|
30 |
|
|
--library UNISIM;
|
31 |
|
|
--use UNISIM.VComponents.all;
|
32 |
|
|
|
33 |
|
|
entity rx_MWr_Transact is
|
34 |
|
|
port (
|
35 |
|
|
-- Transaction receive interface
|
36 |
|
|
trn_rsof_n : IN std_logic;
|
37 |
|
|
trn_reof_n : IN std_logic;
|
38 |
|
|
trn_rd : IN std_logic_vector(C_DBUS_WIDTH-1 downto 0);
|
39 |
|
|
trn_rrem_n : IN std_logic_vector(C_DBUS_WIDTH/8-1 downto 0);
|
40 |
|
|
trn_rerrfwd_n : IN std_logic;
|
41 |
|
|
trn_rsrc_rdy_n : IN std_logic;
|
42 |
|
|
trn_rdst_rdy_n : IN std_logic; -- !!
|
43 |
|
|
trn_rsrc_dsc_n : IN std_logic;
|
44 |
|
|
trn_rbar_hit_n : IN std_logic_vector(C_BAR_NUMBER-1 downto 0);
|
45 |
|
|
-- trn_rfc_ph_av : IN std_logic_vector(7 downto 0);
|
46 |
|
|
-- trn_rfc_pd_av : IN std_logic_vector(11 downto 0);
|
47 |
|
|
-- trn_rfc_nph_av : IN std_logic_vector(7 downto 0);
|
48 |
|
|
-- trn_rfc_npd_av : IN std_logic_vector(11 downto 0);
|
49 |
|
|
-- trn_rfc_cplh_av : IN std_logic_vector(7 downto 0);
|
50 |
|
|
-- trn_rfc_cpld_av : IN std_logic_vector(11 downto 0);
|
51 |
|
|
|
52 |
|
|
-- from pre-process module
|
53 |
|
|
IOWr_Type : IN std_logic;
|
54 |
|
|
MWr_Type : IN std_logic_vector(1 downto 0);
|
55 |
|
|
Tlp_straddles_4KB : IN std_logic;
|
56 |
|
|
-- Last_DW_of_TLP : IN std_logic;
|
57 |
|
|
Tlp_has_4KB : IN std_logic;
|
58 |
|
|
|
59 |
|
|
|
60 |
|
|
-- Event Buffer write port
|
61 |
|
|
eb_FIFO_we : OUT std_logic;
|
62 |
|
|
eb_FIFO_wsof : OUT std_logic;
|
63 |
|
|
eb_FIFO_weof : OUT std_logic;
|
64 |
|
|
eb_FIFO_din : OUT std_logic_vector(C_DBUS_WIDTH-1 downto 0);
|
65 |
|
|
|
66 |
|
|
-- Registers Write Port
|
67 |
|
|
Regs_WrEn : OUT std_logic;
|
68 |
|
|
Regs_WrMask : OUT std_logic_vector(2-1 downto 0);
|
69 |
|
|
Regs_WrAddr : OUT std_logic_vector(C_EP_AWIDTH-1 downto 0);
|
70 |
|
|
Regs_WrDin : OUT std_logic_vector(C_DBUS_WIDTH-1 downto 0);
|
71 |
|
|
|
72 |
|
|
-- DDR write port
|
73 |
|
|
DDR_wr_sof : OUT std_logic;
|
74 |
|
|
DDR_wr_eof : OUT std_logic;
|
75 |
|
|
DDR_wr_v : OUT std_logic;
|
76 |
|
|
DDR_wr_FA : OUT std_logic;
|
77 |
|
|
DDR_wr_Shift : OUT std_logic;
|
78 |
|
|
DDR_wr_Mask : OUT std_logic_vector(2-1 downto 0);
|
79 |
|
|
DDR_wr_din : OUT std_logic_vector(C_DBUS_WIDTH-1 downto 0);
|
80 |
|
|
DDR_wr_full : IN std_logic;
|
81 |
|
|
|
82 |
|
|
-- Data generator table write
|
83 |
|
|
tab_we : OUT std_logic_vector(2-1 downto 0);
|
84 |
|
|
tab_wa : OUT std_logic_vector(12-1 downto 0);
|
85 |
|
|
tab_wd : OUT std_logic_vector(C_DBUS_WIDTH-1 downto 0);
|
86 |
|
|
|
87 |
|
|
-- Common ports
|
88 |
|
|
trn_clk : IN std_logic;
|
89 |
|
|
trn_reset_n : IN std_logic;
|
90 |
|
|
trn_lnk_up_n : IN std_logic
|
91 |
|
|
);
|
92 |
|
|
|
93 |
|
|
end entity rx_MWr_Transact;
|
94 |
|
|
|
95 |
|
|
|
96 |
|
|
|
97 |
|
|
architecture Behavioral of rx_MWr_Transact is
|
98 |
|
|
|
99 |
|
|
|
100 |
|
|
type RxMWrTrnStates is ( ST_MWr_RESET
|
101 |
|
|
, ST_MWr_IDLE
|
102 |
|
|
-- , ST_MWr3_HEAD1
|
103 |
|
|
-- , ST_MWr4_HEAD1
|
104 |
|
|
, ST_MWr3_HEAD2
|
105 |
|
|
, ST_MWr4_HEAD2
|
106 |
|
|
-- , ST_MWr4_HEAD3
|
107 |
|
|
-- , ST_MWr_Last_HEAD
|
108 |
|
|
, ST_MWr4_1ST_DATA
|
109 |
|
|
, ST_MWr_1ST_DATA
|
110 |
|
|
, ST_MWr_1ST_DATA_THROTTLE
|
111 |
|
|
, ST_MWr_DATA
|
112 |
|
|
, ST_MWr_DATA_THROTTLE
|
113 |
|
|
, ST_MWr_LAST_DATA
|
114 |
|
|
);
|
115 |
|
|
|
116 |
|
|
-- State variables
|
117 |
|
|
signal RxMWrTrn_NextState : RxMWrTrnStates;
|
118 |
|
|
signal RxMWrTrn_State : RxMWrTrnStates;
|
119 |
|
|
|
120 |
|
|
-- trn_rx stubs
|
121 |
|
|
signal trn_rd_i : std_logic_vector (C_DBUS_WIDTH-1 downto 0);
|
122 |
|
|
signal trn_rd_r1 : std_logic_vector (C_DBUS_WIDTH-1 downto 0);
|
123 |
|
|
|
124 |
|
|
signal trn_rrem_n_i : std_logic_vector(C_DBUS_WIDTH/8-1 downto 0);
|
125 |
|
|
signal trn_rrem_n_r1 : std_logic_vector(C_DBUS_WIDTH/8-1 downto 0);
|
126 |
|
|
|
127 |
|
|
signal trn_rbar_hit_n_i : std_logic_vector (C_BAR_NUMBER-1 downto 0);
|
128 |
|
|
signal trn_rbar_hit_n_r1 : std_logic_vector (C_BAR_NUMBER-1 downto 0);
|
129 |
|
|
|
130 |
|
|
signal trn_rsrc_rdy_n_i : std_logic;
|
131 |
|
|
signal trn_rerrfwd_n_i : std_logic;
|
132 |
|
|
signal trn_rsof_n_i : std_logic;
|
133 |
|
|
signal trn_reof_n_i : std_logic;
|
134 |
|
|
signal trn_rsrc_rdy_n_r1 : std_logic;
|
135 |
|
|
signal trn_reof_n_r1 : std_logic;
|
136 |
|
|
|
137 |
|
|
|
138 |
|
|
-- packet RAM and packet FIFOs selection signals
|
139 |
|
|
signal FIFO_Space_Sel : std_logic;
|
140 |
|
|
signal DDR_Space_Sel : std_logic;
|
141 |
|
|
signal REGS_Space_Sel : std_logic;
|
142 |
|
|
|
143 |
|
|
-- DDR write port
|
144 |
|
|
signal DDR_wr_sof_i : std_logic;
|
145 |
|
|
signal DDR_wr_eof_i : std_logic;
|
146 |
|
|
signal DDR_wr_v_i : std_logic;
|
147 |
|
|
signal DDR_wr_FA_i : std_logic;
|
148 |
|
|
signal DDR_wr_Shift_i : std_logic;
|
149 |
|
|
signal DDR_wr_Mask_i : std_logic_vector(2-1 downto 0);
|
150 |
|
|
signal ddr_wr_1st_mask_hi : std_logic;
|
151 |
|
|
signal DDR_wr_din_i : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
|
152 |
|
|
signal DDR_wr_full_i : std_logic;
|
153 |
|
|
|
154 |
|
|
-- Data generator sequence table write
|
155 |
|
|
signal dg_table_Sel : std_logic;
|
156 |
|
|
signal tab_wa_odd : std_logic;
|
157 |
|
|
signal tab_we_i : std_logic_vector(2-1 downto 0);
|
158 |
|
|
signal tab_wa_i : std_logic_vector(12-1 downto 0);
|
159 |
|
|
signal tab_wd_i : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
|
160 |
|
|
|
161 |
|
|
-- Event Buffer write port
|
162 |
|
|
signal eb_FIFO_we_i : std_logic;
|
163 |
|
|
signal eb_FIFO_wsof_i : std_logic;
|
164 |
|
|
signal eb_FIFO_weof_i : std_logic;
|
165 |
|
|
signal eb_FIFO_din_i : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
|
166 |
|
|
|
167 |
|
|
--
|
168 |
|
|
signal Regs_WrEn_i : std_logic;
|
169 |
|
|
signal Regs_WrMask_i : std_logic_vector(2-1 downto 0);
|
170 |
|
|
signal Regs_WrAddr_i : std_logic_vector(C_EP_AWIDTH-1 downto 0);
|
171 |
|
|
signal Regs_WrDin_i : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
|
172 |
|
|
|
173 |
|
|
signal trn_rdst_rdy_n_i : std_logic;
|
174 |
|
|
signal trn_rsrc_dsc_n_i : std_logic;
|
175 |
|
|
|
176 |
|
|
signal trn_rx_throttle : std_logic;
|
177 |
|
|
signal trn_rx_throttle_r1 : std_logic;
|
178 |
|
|
|
179 |
|
|
-- 1st DW BE = "0000" means the TLP is of zero-length.
|
180 |
|
|
signal MWr_Has_4DW_Header : std_logic;
|
181 |
|
|
signal Tlp_is_Zero_Length : std_logic;
|
182 |
|
|
signal MWr_Leng_in_Bytes : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
|
183 |
|
|
|
184 |
|
|
|
185 |
|
|
|
186 |
|
|
begin
|
187 |
|
|
|
188 |
|
|
-- Event Buffer write
|
189 |
|
|
eb_FIFO_we <= eb_FIFO_we_i ;
|
190 |
|
|
eb_FIFO_wsof <= eb_FIFO_wsof_i ;
|
191 |
|
|
eb_FIFO_weof <= eb_FIFO_weof_i ;
|
192 |
|
|
eb_FIFO_din <= eb_FIFO_din_i ;
|
193 |
|
|
|
194 |
|
|
-- DDR
|
195 |
|
|
DDR_wr_sof <= DDR_wr_sof_i ;
|
196 |
|
|
DDR_wr_eof <= DDR_wr_eof_i ;
|
197 |
|
|
DDR_wr_v <= DDR_wr_v_i ;
|
198 |
|
|
DDR_wr_FA <= DDR_wr_FA_i ;
|
199 |
|
|
DDR_wr_Shift <= DDR_wr_Shift_i ;
|
200 |
|
|
DDR_wr_Mask <= DDR_wr_Mask_i ;
|
201 |
|
|
DDR_wr_din <= DDR_wr_din_i ;
|
202 |
|
|
DDR_wr_full_i <= DDR_wr_full ;
|
203 |
|
|
|
204 |
|
|
-- Data generator table
|
205 |
|
|
tab_we <= tab_we_i ;
|
206 |
|
|
tab_wa <= tab_wa_i ;
|
207 |
|
|
tab_wd <= tab_wd_i ;
|
208 |
|
|
|
209 |
|
|
-- Registers writing
|
210 |
|
|
Regs_WrEn <= Regs_WrEn_i;
|
211 |
|
|
Regs_WrMask <= Regs_WrMask_i;
|
212 |
|
|
Regs_WrAddr <= Regs_WrAddr_i;
|
213 |
|
|
Regs_WrDin <= Regs_WrDin_i; -- Mem_WrData;
|
214 |
|
|
|
215 |
|
|
|
216 |
|
|
|
217 |
|
|
-- TLP info stubs
|
218 |
|
|
trn_rd_i <= trn_rd;
|
219 |
|
|
trn_rsof_n_i <= trn_rsof_n;
|
220 |
|
|
trn_reof_n_i <= trn_reof_n;
|
221 |
|
|
trn_rrem_n_i <= trn_rrem_n;
|
222 |
|
|
|
223 |
|
|
|
224 |
|
|
-- Output to the core as handshaking
|
225 |
|
|
trn_rerrfwd_n_i <= trn_rerrfwd_n;
|
226 |
|
|
trn_rbar_hit_n_i <= trn_rbar_hit_n;
|
227 |
|
|
trn_rsrc_dsc_n_i <= trn_rsrc_dsc_n;
|
228 |
|
|
|
229 |
|
|
-- Output to the core as handshaking
|
230 |
|
|
trn_rsrc_rdy_n_i <= trn_rsrc_rdy_n;
|
231 |
|
|
trn_rdst_rdy_n_i <= trn_rdst_rdy_n;
|
232 |
|
|
|
233 |
|
|
|
234 |
|
|
-- ( trn_rsrc_rdy_n seems never deasserted during packet)
|
235 |
|
|
trn_rx_throttle <= trn_rsrc_rdy_n_i or trn_rdst_rdy_n_i;
|
236 |
|
|
|
237 |
|
|
|
238 |
|
|
-- -----------------------------------------------------
|
239 |
|
|
-- Delays: trn_rd_i, trn_rbar_hit_n_i, trn_reof_n_i
|
240 |
|
|
-- -----------------------------------------------------
|
241 |
|
|
Sync_Delays_trn_rd_rbar_reof:
|
242 |
|
|
process ( trn_clk )
|
243 |
|
|
begin
|
244 |
|
|
if trn_clk'event and trn_clk = '1' then
|
245 |
|
|
trn_rsrc_rdy_n_r1 <= trn_rsrc_rdy_n_i;
|
246 |
|
|
trn_reof_n_r1 <= trn_reof_n_i;
|
247 |
|
|
trn_rd_r1 <= trn_rd_i;
|
248 |
|
|
trn_rrem_n_r1 <= trn_rrem_n_i;
|
249 |
|
|
trn_rbar_hit_n_r1 <= trn_rbar_hit_n_i;
|
250 |
|
|
trn_rx_throttle_r1 <= trn_rx_throttle;
|
251 |
|
|
end if;
|
252 |
|
|
end process;
|
253 |
|
|
|
254 |
|
|
|
255 |
|
|
-- -----------------------------------------------------------------------
|
256 |
|
|
-- States synchronous
|
257 |
|
|
--
|
258 |
|
|
Syn_RxTrn_States:
|
259 |
|
|
process ( trn_clk, trn_reset_n)
|
260 |
|
|
begin
|
261 |
|
|
if trn_reset_n = '0' then
|
262 |
|
|
RxMWrTrn_State <= ST_MWr_RESET;
|
263 |
|
|
elsif trn_clk'event and trn_clk = '1' then
|
264 |
|
|
RxMWrTrn_State <= RxMWrTrn_NextState;
|
265 |
|
|
end if;
|
266 |
|
|
end process;
|
267 |
|
|
|
268 |
|
|
|
269 |
|
|
-- Next States
|
270 |
|
|
Comb_RxTrn_NextStates:
|
271 |
|
|
process (
|
272 |
|
|
RxMWrTrn_State
|
273 |
|
|
, MWr_Type
|
274 |
|
|
-- , IOWr_Type
|
275 |
|
|
, Tlp_straddles_4KB
|
276 |
|
|
, trn_rx_throttle
|
277 |
|
|
, trn_reof_n_i
|
278 |
|
|
-- , Last_DW_of_TLP
|
279 |
|
|
)
|
280 |
|
|
begin
|
281 |
|
|
case RxMWrTrn_State is
|
282 |
|
|
|
283 |
|
|
when ST_MWr_RESET =>
|
284 |
|
|
RxMWrTrn_NextState <= ST_MWr_IDLE;
|
285 |
|
|
|
286 |
|
|
when ST_MWr_IDLE =>
|
287 |
|
|
if trn_rx_throttle='0' then
|
288 |
|
|
case MWr_Type is
|
289 |
|
|
when C_TLP_TYPE_IS_MWR_H3 =>
|
290 |
|
|
RxMWrTrn_NextState <= ST_MWr3_HEAD2;
|
291 |
|
|
when C_TLP_TYPE_IS_MWR_H4 =>
|
292 |
|
|
RxMWrTrn_NextState <= ST_MWr4_HEAD2;
|
293 |
|
|
when OTHERS =>
|
294 |
|
|
-- if IOWr_Type='1' then -- Temp taking IOWr as MWr3
|
295 |
|
|
-- RxMWrTrn_NextState <= ST_MWr3_HEAD1;
|
296 |
|
|
-- else
|
297 |
|
|
RxMWrTrn_NextState <= ST_MWr_IDLE;
|
298 |
|
|
-- end if;
|
299 |
|
|
end case; -- MWr_Type
|
300 |
|
|
else
|
301 |
|
|
RxMWrTrn_NextState <= ST_MWr_IDLE;
|
302 |
|
|
end if;
|
303 |
|
|
|
304 |
|
|
|
305 |
|
|
-- when ST_MWr3_HEAD1 =>
|
306 |
|
|
-- if trn_rx_throttle = '1' then
|
307 |
|
|
-- RxMWrTrn_NextState <= ST_MWr3_HEAD1;
|
308 |
|
|
-- else
|
309 |
|
|
-- RxMWrTrn_NextState <= ST_MWr3_HEAD2;
|
310 |
|
|
-- end if;
|
311 |
|
|
|
312 |
|
|
-- when ST_MWr4_HEAD1 =>
|
313 |
|
|
-- if trn_rx_throttle = '1' then
|
314 |
|
|
-- RxMWrTrn_NextState <= ST_MWr4_HEAD1;
|
315 |
|
|
-- else
|
316 |
|
|
-- RxMWrTrn_NextState <= ST_MWr4_HEAD2;
|
317 |
|
|
-- end if;
|
318 |
|
|
|
319 |
|
|
|
320 |
|
|
when ST_MWr3_HEAD2 =>
|
321 |
|
|
if trn_rx_throttle = '1' then
|
322 |
|
|
RxMWrTrn_NextState <= ST_MWr3_HEAD2;
|
323 |
|
|
elsif trn_reof_n_i = '0' then
|
324 |
|
|
RxMWrTrn_NextState <= ST_MWr_IDLE; -- ST_MWr_LAST_DATA;
|
325 |
|
|
else
|
326 |
|
|
RxMWrTrn_NextState <= ST_MWr_1ST_DATA; -- ST_MWr_Last_HEAD;
|
327 |
|
|
end if;
|
328 |
|
|
|
329 |
|
|
when ST_MWr4_HEAD2 =>
|
330 |
|
|
if trn_rx_throttle = '1' then
|
331 |
|
|
RxMWrTrn_NextState <= ST_MWr4_HEAD2;
|
332 |
|
|
else
|
333 |
|
|
RxMWrTrn_NextState <= ST_MWr4_1ST_DATA; -- ST_MWr4_HEAD3;
|
334 |
|
|
end if;
|
335 |
|
|
|
336 |
|
|
-- when ST_MWr4_HEAD3 =>
|
337 |
|
|
-- if trn_rx_throttle = '1' then
|
338 |
|
|
-- RxMWrTrn_NextState <= ST_MWr4_HEAD3;
|
339 |
|
|
-- else
|
340 |
|
|
-- RxMWrTrn_NextState <= ST_MWr_Last_HEAD;
|
341 |
|
|
-- end if;
|
342 |
|
|
|
343 |
|
|
|
344 |
|
|
-- when ST_MWr_Last_HEAD =>
|
345 |
|
|
-- if trn_rx_throttle = '1' then
|
346 |
|
|
-- RxMWrTrn_NextState <= ST_MWr_Last_HEAD;
|
347 |
|
|
-- elsif Tlp_straddles_4KB = '1' then -- !!
|
348 |
|
|
-- RxMWrTrn_NextState <= ST_MWr_IDLE;
|
349 |
|
|
---- elsif Last_DW_of_TLP='1' then
|
350 |
|
|
---- RxMWrTrn_NextState <= ST_MWr_LAST_DATA;
|
351 |
|
|
-- elsif trn_reof_n_i = '0' then
|
352 |
|
|
-- RxMWrTrn_NextState <= ST_MWr_LAST_DATA;
|
353 |
|
|
-- else
|
354 |
|
|
-- RxMWrTrn_NextState <= ST_MWr_1ST_DATA;
|
355 |
|
|
-- end if;
|
356 |
|
|
|
357 |
|
|
|
358 |
|
|
when ST_MWr_1ST_DATA =>
|
359 |
|
|
if trn_rx_throttle = '1' then
|
360 |
|
|
RxMWrTrn_NextState <= ST_MWr_1ST_DATA_THROTTLE;
|
361 |
|
|
elsif trn_reof_n_i = '0' then
|
362 |
|
|
RxMWrTrn_NextState <= ST_MWr_IDLE; -- ST_MWr_LAST_DATA;
|
363 |
|
|
else
|
364 |
|
|
RxMWrTrn_NextState <= ST_MWr_DATA;
|
365 |
|
|
end if;
|
366 |
|
|
|
367 |
|
|
when ST_MWr4_1ST_DATA =>
|
368 |
|
|
if trn_rx_throttle = '1' then
|
369 |
|
|
RxMWrTrn_NextState <= ST_MWr_1ST_DATA_THROTTLE;
|
370 |
|
|
elsif trn_reof_n_i = '0' then
|
371 |
|
|
RxMWrTrn_NextState <= ST_MWr_IDLE; -- ST_MWr_LAST_DATA;
|
372 |
|
|
else
|
373 |
|
|
RxMWrTrn_NextState <= ST_MWr_DATA;
|
374 |
|
|
end if;
|
375 |
|
|
|
376 |
|
|
when ST_MWr_1ST_DATA_THROTTLE =>
|
377 |
|
|
if trn_rx_throttle = '1' then
|
378 |
|
|
RxMWrTrn_NextState <= ST_MWr_1ST_DATA_THROTTLE;
|
379 |
|
|
elsif trn_reof_n_i = '0' then
|
380 |
|
|
RxMWrTrn_NextState <= ST_MWr_IDLE; -- ST_MWr_LAST_DATA;
|
381 |
|
|
else
|
382 |
|
|
RxMWrTrn_NextState <= ST_MWr_DATA;
|
383 |
|
|
end if;
|
384 |
|
|
|
385 |
|
|
|
386 |
|
|
when ST_MWr_DATA =>
|
387 |
|
|
if trn_rx_throttle = '1' then
|
388 |
|
|
RxMWrTrn_NextState <= ST_MWr_DATA_THROTTLE;
|
389 |
|
|
elsif trn_reof_n_i = '0' then
|
390 |
|
|
RxMWrTrn_NextState <= ST_MWr_LAST_DATA;
|
391 |
|
|
else
|
392 |
|
|
RxMWrTrn_NextState <= ST_MWr_DATA;
|
393 |
|
|
end if;
|
394 |
|
|
|
395 |
|
|
|
396 |
|
|
when ST_MWr_DATA_THROTTLE =>
|
397 |
|
|
if trn_rx_throttle = '1' then
|
398 |
|
|
RxMWrTrn_NextState <= ST_MWr_DATA_THROTTLE;
|
399 |
|
|
elsif trn_reof_n_i = '0' then
|
400 |
|
|
RxMWrTrn_NextState <= ST_MWr_LAST_DATA;
|
401 |
|
|
else
|
402 |
|
|
RxMWrTrn_NextState <= ST_MWr_DATA;
|
403 |
|
|
end if;
|
404 |
|
|
|
405 |
|
|
|
406 |
|
|
when ST_MWr_LAST_DATA => -- Same as ST_MWr_IDLE, to support
|
407 |
|
|
-- back-to-back transactions
|
408 |
|
|
case MWr_Type is
|
409 |
|
|
when C_TLP_TYPE_IS_MWR_H3 =>
|
410 |
|
|
RxMWrTrn_NextState <= ST_MWr3_HEAD2;
|
411 |
|
|
when C_TLP_TYPE_IS_MWR_H4 =>
|
412 |
|
|
RxMWrTrn_NextState <= ST_MWr4_HEAD2;
|
413 |
|
|
when OTHERS =>
|
414 |
|
|
-- if IOWr_Type='1' then
|
415 |
|
|
-- RxMWrTrn_NextState <= ST_MWr3_HEAD1;
|
416 |
|
|
-- else
|
417 |
|
|
RxMWrTrn_NextState <= ST_MWr_IDLE;
|
418 |
|
|
-- end if;
|
419 |
|
|
end case; -- MWr_Type
|
420 |
|
|
|
421 |
|
|
|
422 |
|
|
when OTHERS =>
|
423 |
|
|
RxMWrTrn_NextState <= ST_MWr_RESET;
|
424 |
|
|
|
425 |
|
|
end case;
|
426 |
|
|
|
427 |
|
|
end process;
|
428 |
|
|
|
429 |
|
|
|
430 |
|
|
|
431 |
|
|
-- ----------------------------------------------
|
432 |
|
|
-- registers Write Enable
|
433 |
|
|
--
|
434 |
|
|
RxFSM_Output_Regs_Write_En:
|
435 |
|
|
process ( trn_clk, trn_reset_n)
|
436 |
|
|
begin
|
437 |
|
|
if trn_reset_n = '0' then
|
438 |
|
|
Regs_WrEn_i <= '0';
|
439 |
|
|
Regs_WrMask_i <= (OTHERS=>'0');
|
440 |
|
|
Regs_WrAddr_i <= (OTHERS=>'1');
|
441 |
|
|
Regs_WrDin_i <= (OTHERS=>'0');
|
442 |
|
|
|
443 |
|
|
elsif trn_clk'event and trn_clk = '1' then
|
444 |
|
|
|
445 |
|
|
case RxMWrTrn_State is
|
446 |
|
|
|
447 |
|
|
when ST_MWr3_HEAD2 =>
|
448 |
|
|
if REGS_Space_Sel='1' then
|
449 |
|
|
Regs_WrEn_i <= not trn_rx_throttle;
|
450 |
|
|
Regs_WrMask_i <= "01";
|
451 |
|
|
Regs_WrAddr_i <= trn_rd_i(C_EP_AWIDTH-1+32 downto 2+32) & "00";
|
452 |
|
|
Regs_WrDin_i <= Endian_Invert_32(trn_rd_i(31 downto 0)) & X"00000000";
|
453 |
|
|
-- Regs_WrDin_i <= Endian_Invert_64((trn_rd_r1(31 downto 0)&trn_rd_r1(63 downto 32)));
|
454 |
|
|
else
|
455 |
|
|
Regs_WrEn_i <= '0';
|
456 |
|
|
Regs_WrMask_i <= (OTHERS=>'0');
|
457 |
|
|
Regs_WrAddr_i <= (OTHERS=>'1');
|
458 |
|
|
Regs_WrDin_i <= (OTHERS=>'0');
|
459 |
|
|
end if;
|
460 |
|
|
|
461 |
|
|
when ST_MWr4_HEAD2 =>
|
462 |
|
|
if REGS_Space_Sel='1' then
|
463 |
|
|
Regs_WrEn_i <= '0';
|
464 |
|
|
Regs_WrMask_i <= (OTHERS=>'0');
|
465 |
|
|
Regs_WrAddr_i <= trn_rd_i(C_EP_AWIDTH-1 downto 2) &"00";
|
466 |
|
|
Regs_WrDin_i <= Endian_Invert_64(trn_rd_i);
|
467 |
|
|
else
|
468 |
|
|
Regs_WrEn_i <= '0';
|
469 |
|
|
Regs_WrMask_i <= (OTHERS=>'0');
|
470 |
|
|
Regs_WrAddr_i <= (OTHERS=>'1');
|
471 |
|
|
Regs_WrDin_i <= (OTHERS=>'0');
|
472 |
|
|
end if;
|
473 |
|
|
|
474 |
|
|
when ST_MWr_1ST_DATA =>
|
475 |
|
|
if REGS_Space_Sel='1' then
|
476 |
|
|
Regs_WrEn_i <= not trn_rx_throttle;
|
477 |
|
|
Regs_WrDin_i <= Endian_Invert_64 (trn_rd_i);
|
478 |
|
|
if trn_reof_n_i='0' then
|
479 |
|
|
Regs_WrMask_i <= '0' & (trn_rrem_n_i(3) or trn_rrem_n_i(0));
|
480 |
|
|
else
|
481 |
|
|
Regs_WrMask_i <= (OTHERS=>'0');
|
482 |
|
|
end if;
|
483 |
|
|
if MWr_Has_4DW_Header='1' then
|
484 |
|
|
Regs_WrAddr_i <= Regs_WrAddr_i;
|
485 |
|
|
else
|
486 |
|
|
Regs_WrAddr_i <= Regs_WrAddr_i + CONV_STD_LOGIC_VECTOR(4, C_EP_AWIDTH);
|
487 |
|
|
end if;
|
488 |
|
|
else
|
489 |
|
|
Regs_WrEn_i <= '0';
|
490 |
|
|
Regs_WrMask_i <= (OTHERS=>'0');
|
491 |
|
|
Regs_WrAddr_i <= (OTHERS=>'1');
|
492 |
|
|
Regs_WrDin_i <= (OTHERS=>'0');
|
493 |
|
|
end if;
|
494 |
|
|
|
495 |
|
|
when ST_MWr4_1ST_DATA =>
|
496 |
|
|
if REGS_Space_Sel='1' then
|
497 |
|
|
Regs_WrEn_i <= not trn_rx_throttle;
|
498 |
|
|
Regs_WrDin_i <= Endian_Invert_64 (trn_rd_i);
|
499 |
|
|
if trn_reof_n_i='0' then
|
500 |
|
|
Regs_WrMask_i <= '0' & (trn_rrem_n_i(3) or trn_rrem_n_i(0));
|
501 |
|
|
else
|
502 |
|
|
Regs_WrMask_i <= (OTHERS=>'0');
|
503 |
|
|
end if;
|
504 |
|
|
-- if MWr_Has_4DW_Header='1' then
|
505 |
|
|
Regs_WrAddr_i <= Regs_WrAddr_i;
|
506 |
|
|
-- else
|
507 |
|
|
-- Regs_WrAddr_i <= Regs_WrAddr_i + CONV_STD_LOGIC_VECTOR(4, C_EP_AWIDTH);
|
508 |
|
|
-- end if;
|
509 |
|
|
else
|
510 |
|
|
Regs_WrEn_i <= '0';
|
511 |
|
|
Regs_WrMask_i <= (OTHERS=>'0');
|
512 |
|
|
Regs_WrAddr_i <= (OTHERS=>'1');
|
513 |
|
|
Regs_WrDin_i <= (OTHERS=>'0');
|
514 |
|
|
end if;
|
515 |
|
|
|
516 |
|
|
when ST_MWr_1ST_DATA_THROTTLE =>
|
517 |
|
|
if REGS_Space_Sel='1' then
|
518 |
|
|
Regs_WrEn_i <= not trn_rx_throttle;
|
519 |
|
|
Regs_WrDin_i <= Endian_Invert_64 (trn_rd_i);
|
520 |
|
|
if trn_reof_n_i='0' then
|
521 |
|
|
Regs_WrMask_i <= '0' & (trn_rrem_n_i(3) or trn_rrem_n_i(0));
|
522 |
|
|
else
|
523 |
|
|
Regs_WrMask_i <= (OTHERS=>'0');
|
524 |
|
|
end if;
|
525 |
|
|
-- if MWr_Has_4DW_Header='1' then
|
526 |
|
|
Regs_WrAddr_i <= Regs_WrAddr_i;
|
527 |
|
|
-- else
|
528 |
|
|
-- Regs_WrAddr_i <= Regs_WrAddr_i + CONV_STD_LOGIC_VECTOR(4, C_EP_AWIDTH);
|
529 |
|
|
-- end if;
|
530 |
|
|
else
|
531 |
|
|
Regs_WrEn_i <= '0';
|
532 |
|
|
Regs_WrMask_i <= (OTHERS=>'0');
|
533 |
|
|
Regs_WrAddr_i <= (OTHERS=>'1');
|
534 |
|
|
Regs_WrDin_i <= (OTHERS=>'0');
|
535 |
|
|
end if;
|
536 |
|
|
|
537 |
|
|
when ST_MWr_DATA =>
|
538 |
|
|
if REGS_Space_Sel='1' then
|
539 |
|
|
Regs_WrEn_i <= not trn_rx_throttle; -- '1';
|
540 |
|
|
if trn_reof_n_i='0' then
|
541 |
|
|
Regs_WrMask_i <= '0' & (trn_rrem_n_i(3) or trn_rrem_n_i(0));
|
542 |
|
|
else
|
543 |
|
|
Regs_WrMask_i <= (OTHERS=>'0');
|
544 |
|
|
end if;
|
545 |
|
|
Regs_WrAddr_i <= Regs_WrAddr_i + CONV_STD_LOGIC_VECTOR(8, C_EP_AWIDTH);
|
546 |
|
|
Regs_WrDin_i <= Endian_Invert_64 (trn_rd_i);
|
547 |
|
|
else
|
548 |
|
|
Regs_WrEn_i <= '0';
|
549 |
|
|
Regs_WrMask_i <= (OTHERS=>'0');
|
550 |
|
|
Regs_WrAddr_i <= (OTHERS=>'1');
|
551 |
|
|
Regs_WrDin_i <= (OTHERS=>'0');
|
552 |
|
|
end if;
|
553 |
|
|
|
554 |
|
|
|
555 |
|
|
when ST_MWr_DATA_THROTTLE =>
|
556 |
|
|
if REGS_Space_Sel='1' then
|
557 |
|
|
Regs_WrEn_i <= not trn_rx_throttle; -- '1';
|
558 |
|
|
if trn_reof_n_i='0' then
|
559 |
|
|
Regs_WrMask_i <= '0' & (trn_rrem_n_i(3) or trn_rrem_n_i(0));
|
560 |
|
|
else
|
561 |
|
|
Regs_WrMask_i <= (OTHERS=>'0');
|
562 |
|
|
end if;
|
563 |
|
|
Regs_WrAddr_i <= Regs_WrAddr_i; -- + CONV_STD_LOGIC_VECTOR(8, C_EP_AWIDTH);
|
564 |
|
|
Regs_WrDin_i <= Endian_Invert_64 (trn_rd_i);
|
565 |
|
|
else
|
566 |
|
|
Regs_WrEn_i <= '0';
|
567 |
|
|
Regs_WrMask_i <= (OTHERS=>'0');
|
568 |
|
|
Regs_WrAddr_i <= (OTHERS=>'1');
|
569 |
|
|
Regs_WrDin_i <= (OTHERS=>'0');
|
570 |
|
|
end if;
|
571 |
|
|
|
572 |
|
|
|
573 |
|
|
when OTHERS =>
|
574 |
|
|
Regs_WrEn_i <= '0';
|
575 |
|
|
Regs_WrMask_i <= (OTHERS=>'0');
|
576 |
|
|
Regs_WrAddr_i <= (OTHERS=>'1');
|
577 |
|
|
Regs_WrDin_i <= (OTHERS=>'0');
|
578 |
|
|
|
579 |
|
|
end case;
|
580 |
|
|
|
581 |
|
|
end if;
|
582 |
|
|
|
583 |
|
|
end process;
|
584 |
|
|
|
585 |
|
|
|
586 |
|
|
|
587 |
|
|
-- -----------------------------------------------------------------------
|
588 |
|
|
-- Capture: REGS_Space_Sel
|
589 |
|
|
--
|
590 |
|
|
Syn_Capture_REGS_Space_Sel:
|
591 |
|
|
process ( trn_clk, trn_reset_n)
|
592 |
|
|
begin
|
593 |
|
|
if trn_reset_n = '0' then
|
594 |
|
|
REGS_Space_Sel <= '0';
|
595 |
|
|
elsif trn_clk'event and trn_clk = '1' then
|
596 |
|
|
if trn_rsof_n_i='0' then
|
597 |
|
|
REGS_Space_Sel <= (trn_rd_i(3) or trn_rd_i(2) or trn_rd_i(1) or trn_rd_i(0))
|
598 |
|
|
and not trn_rbar_hit_n_i(CINT_REGS_SPACE_BAR);
|
599 |
|
|
else
|
600 |
|
|
REGS_Space_Sel <= REGS_Space_Sel;
|
601 |
|
|
end if;
|
602 |
|
|
end if;
|
603 |
|
|
end process;
|
604 |
|
|
|
605 |
|
|
|
606 |
|
|
-- -----------------------------------------------------------------------
|
607 |
|
|
-- Capture: MWr_Has_4DW_Header
|
608 |
|
|
-- : Tlp_is_Zero_Length
|
609 |
|
|
--
|
610 |
|
|
Syn_Capture_MWr_Has_4DW_Header:
|
611 |
|
|
process ( trn_clk, trn_reset_n)
|
612 |
|
|
begin
|
613 |
|
|
if trn_reset_n = '0' then
|
614 |
|
|
MWr_Has_4DW_Header <= '0';
|
615 |
|
|
Tlp_is_Zero_Length <= '0';
|
616 |
|
|
elsif trn_clk'event and trn_clk = '1' then
|
617 |
|
|
if trn_rsof_n_i='0' then
|
618 |
|
|
MWr_Has_4DW_Header <= trn_rd_i(C_TLP_FMT_BIT_BOT);
|
619 |
|
|
Tlp_is_Zero_Length <= not (trn_rd_i(3) or trn_rd_i(2) or trn_rd_i(1) or trn_rd_i(0));
|
620 |
|
|
else
|
621 |
|
|
MWr_Has_4DW_Header <= MWr_Has_4DW_Header;
|
622 |
|
|
Tlp_is_Zero_Length <= Tlp_is_Zero_Length;
|
623 |
|
|
end if;
|
624 |
|
|
end if;
|
625 |
|
|
end process;
|
626 |
|
|
|
627 |
|
|
-- -----------------------------------------------------------------------
|
628 |
|
|
-- Capture: MWr_Leng_in_Bytes
|
629 |
|
|
--
|
630 |
|
|
Syn_Capture_MWr_Length_in_Bytes:
|
631 |
|
|
process ( trn_clk, trn_reset_n)
|
632 |
|
|
begin
|
633 |
|
|
if trn_reset_n = '0' then
|
634 |
|
|
MWr_Leng_in_Bytes <= (OTHERS=>'0');
|
635 |
|
|
elsif trn_clk'event and trn_clk = '1' then
|
636 |
|
|
if trn_rsof_n_i='0' then
|
637 |
|
|
-- Assume no 4KB length for MWr
|
638 |
|
|
MWr_Leng_in_Bytes(C_TLP_FLD_WIDTH_OF_LENG+2 downto 2)
|
639 |
|
|
<= Tlp_has_4KB & trn_rd_i(C_TLP_LENG_BIT_TOP downto C_TLP_LENG_BIT_BOT);
|
640 |
|
|
else
|
641 |
|
|
MWr_Leng_in_Bytes <= MWr_Leng_in_Bytes;
|
642 |
|
|
end if;
|
643 |
|
|
end if;
|
644 |
|
|
end process;
|
645 |
|
|
|
646 |
|
|
|
647 |
|
|
-- ----------------------------------------------
|
648 |
|
|
-- Synchronous outputs: DDR Space Select --
|
649 |
|
|
-- ----------------------------------------------
|
650 |
|
|
RxFSM_Output_DDR_Space_Selected:
|
651 |
|
|
process ( trn_clk, trn_reset_n)
|
652 |
|
|
begin
|
653 |
|
|
if trn_reset_n = '0' then
|
654 |
|
|
DDR_Space_Sel <= '0';
|
655 |
|
|
DDR_wr_sof_i <= '0';
|
656 |
|
|
DDR_wr_eof_i <= '0';
|
657 |
|
|
DDR_wr_v_i <= '0';
|
658 |
|
|
DDR_wr_FA_i <= '0';
|
659 |
|
|
DDR_wr_Shift_i <= '0';
|
660 |
|
|
DDR_wr_Mask_i <= (OTHERS=>'0');
|
661 |
|
|
DDR_wr_din_i <= (OTHERS=>'0');
|
662 |
|
|
ddr_wr_1st_mask_hi <= '0';
|
663 |
|
|
|
664 |
|
|
elsif trn_clk'event and trn_clk = '1' then
|
665 |
|
|
|
666 |
|
|
case RxMWrTrn_State is
|
667 |
|
|
|
668 |
|
|
when ST_MWr3_HEAD2 =>
|
669 |
|
|
if trn_rbar_hit_n_r1(CINT_DDR_SPACE_BAR)='0'
|
670 |
|
|
and Tlp_is_Zero_Length='0'
|
671 |
|
|
then
|
672 |
|
|
DDR_Space_Sel <= not trn_rd_i(32+19) and not trn_rd_i(32+18); -- '1';
|
673 |
|
|
DDR_wr_sof_i <= not trn_rd_i(32+19) and not trn_rd_i(32+18); -- '1';
|
674 |
|
|
DDR_wr_eof_i <= '0';
|
675 |
|
|
DDR_wr_v_i <= not trn_rsrc_rdy_n_i and not trn_rd_i(32+19) and not trn_rd_i(32+18);
|
676 |
|
|
DDR_wr_FA_i <= '0';
|
677 |
|
|
DDR_wr_Shift_i <= not trn_rd_i(2+32);
|
678 |
|
|
DDR_wr_Mask_i <= (OTHERS=>'0');
|
679 |
|
|
ddr_wr_1st_mask_hi <= '1';
|
680 |
|
|
DDR_wr_din_i <= MWr_Leng_in_Bytes(31 downto 0) & trn_rd_i(64-1 downto 32);
|
681 |
|
|
else
|
682 |
|
|
DDR_Space_Sel <= '0';
|
683 |
|
|
DDR_wr_sof_i <= '0';
|
684 |
|
|
DDR_wr_eof_i <= '0';
|
685 |
|
|
DDR_wr_v_i <= '0';
|
686 |
|
|
DDR_wr_FA_i <= '0';
|
687 |
|
|
DDR_wr_Shift_i <= '0';
|
688 |
|
|
DDR_wr_Mask_i <= (OTHERS=>'0');
|
689 |
|
|
ddr_wr_1st_mask_hi <= '0';
|
690 |
|
|
DDR_wr_din_i <= MWr_Leng_in_Bytes(31 downto 0) & trn_rd_i(64-1 downto 32);
|
691 |
|
|
end if;
|
692 |
|
|
|
693 |
|
|
when ST_MWr4_HEAD2 =>
|
694 |
|
|
if trn_rbar_hit_n_r1(CINT_DDR_SPACE_BAR)='0'
|
695 |
|
|
and Tlp_is_Zero_Length='0'
|
696 |
|
|
then
|
697 |
|
|
DDR_Space_Sel <= not trn_rd_i(19) and not trn_rd_i(18); -- '1';
|
698 |
|
|
DDR_wr_sof_i <= not trn_rd_i(19) and not trn_rd_i(18); -- '1';
|
699 |
|
|
DDR_wr_eof_i <= '0';
|
700 |
|
|
DDR_wr_v_i <= not trn_rsrc_rdy_n_i and not trn_rd_i(19) and not trn_rd_i(18);
|
701 |
|
|
DDR_wr_FA_i <= '0';
|
702 |
|
|
DDR_wr_Shift_i <= trn_rd_i(2);
|
703 |
|
|
DDR_wr_Mask_i <= (OTHERS=>'0');
|
704 |
|
|
ddr_wr_1st_mask_hi <= '0';
|
705 |
|
|
DDR_wr_din_i <= MWr_Leng_in_Bytes(31 downto 0) & trn_rd_i(32-1 downto 0);
|
706 |
|
|
else
|
707 |
|
|
DDR_Space_Sel <= '0';
|
708 |
|
|
DDR_wr_sof_i <= '0';
|
709 |
|
|
DDR_wr_eof_i <= '0';
|
710 |
|
|
DDR_wr_v_i <= '0';
|
711 |
|
|
DDR_wr_FA_i <= '0';
|
712 |
|
|
DDR_wr_Shift_i <= '0';
|
713 |
|
|
DDR_wr_Mask_i <= (OTHERS=>'0');
|
714 |
|
|
ddr_wr_1st_mask_hi <= '0';
|
715 |
|
|
DDR_wr_din_i <= MWr_Leng_in_Bytes(31 downto 0) & trn_rd_i(32-1 downto 0);
|
716 |
|
|
end if;
|
717 |
|
|
|
718 |
|
|
when ST_MWr4_1ST_DATA =>
|
719 |
|
|
DDR_Space_Sel <= DDR_Space_Sel;
|
720 |
|
|
DDR_wr_sof_i <= '0';
|
721 |
|
|
DDR_wr_eof_i <= '0';
|
722 |
|
|
DDR_wr_v_i <= '0';
|
723 |
|
|
DDR_wr_FA_i <= '0';
|
724 |
|
|
DDR_wr_Shift_i <= '0';
|
725 |
|
|
DDR_wr_Mask_i <= (OTHERS=>'0');
|
726 |
|
|
ddr_wr_1st_mask_hi <= '0';
|
727 |
|
|
DDR_wr_din_i <= (OTHERS=>'0');
|
728 |
|
|
|
729 |
|
|
|
730 |
|
|
when OTHERS =>
|
731 |
|
|
if trn_reof_n_r1='0' then
|
732 |
|
|
DDR_Space_Sel <= '0';
|
733 |
|
|
else
|
734 |
|
|
DDR_Space_Sel <= DDR_Space_Sel;
|
735 |
|
|
end if;
|
736 |
|
|
|
737 |
|
|
if DDR_Space_Sel='1' then
|
738 |
|
|
DDR_wr_sof_i <= '0';
|
739 |
|
|
DDR_wr_eof_i <= not trn_reof_n_r1;
|
740 |
|
|
DDR_wr_v_i <= not trn_rx_throttle_r1; -- not trn_rsrc_rdy_n_r1;
|
741 |
|
|
DDR_wr_FA_i <= '0';
|
742 |
|
|
DDR_wr_Shift_i <= '0';
|
743 |
|
|
DDR_wr_Mask_i <= ddr_wr_1st_mask_hi & (trn_rrem_n_r1(3) or trn_rrem_n_r1(0));
|
744 |
|
|
DDR_wr_din_i <= Endian_Invert_64 (trn_rd_r1);
|
745 |
|
|
else
|
746 |
|
|
DDR_wr_sof_i <= '0';
|
747 |
|
|
DDR_wr_eof_i <= '0';
|
748 |
|
|
DDR_wr_v_i <= '0';
|
749 |
|
|
DDR_wr_FA_i <= '0';
|
750 |
|
|
DDR_wr_Shift_i <= '0';
|
751 |
|
|
DDR_wr_Mask_i <= (OTHERS=>'0');
|
752 |
|
|
DDR_wr_din_i <= Endian_Invert_64 (trn_rd_r1);
|
753 |
|
|
end if;
|
754 |
|
|
if DDR_wr_v_i='1' then
|
755 |
|
|
ddr_wr_1st_mask_hi <= '0';
|
756 |
|
|
else
|
757 |
|
|
ddr_wr_1st_mask_hi <= ddr_wr_1st_mask_hi;
|
758 |
|
|
end if;
|
759 |
|
|
|
760 |
|
|
end case;
|
761 |
|
|
|
762 |
|
|
end if;
|
763 |
|
|
|
764 |
|
|
end process;
|
765 |
|
|
|
766 |
|
|
|
767 |
|
|
-- ----------------------------------------------
|
768 |
|
|
-- Synchronous outputs: DGen Table write --
|
769 |
|
|
-- ----------------------------------------------
|
770 |
|
|
RxFSM_Output_DGen_Table_write:
|
771 |
|
|
process ( trn_clk, trn_reset_n)
|
772 |
|
|
begin
|
773 |
|
|
if trn_reset_n = '0' then
|
774 |
|
|
-- Assume every PIO MWr contains only 1 DW(32 bits) payload
|
775 |
|
|
dg_table_Sel <= '0';
|
776 |
|
|
tab_we_i <= (OTHERS=>'0');
|
777 |
|
|
tab_wa_i <= (OTHERS=>'0');
|
778 |
|
|
tab_wd_i <= (OTHERS=>'0');
|
779 |
|
|
tab_wa_odd <= '0';
|
780 |
|
|
|
781 |
|
|
elsif trn_clk'event and trn_clk = '1' then
|
782 |
|
|
|
783 |
|
|
case RxMWrTrn_State is
|
784 |
|
|
|
785 |
|
|
when ST_MWr3_HEAD2 =>
|
786 |
|
|
if trn_rbar_hit_n_r1(CINT_DDR_SPACE_BAR)='0'
|
787 |
|
|
and Tlp_is_Zero_Length='0'
|
788 |
|
|
then
|
789 |
|
|
dg_table_Sel <= trn_rd_i(19) and trn_rd_i(18) and not trn_rd_i(17) and not trn_rd_i(16); -- any expression
|
790 |
|
|
tab_we_i <= (trn_rd_i(32+19) and trn_rd_i(32+18) and not trn_rd_i(32+17) and not trn_rd_i(32+16) and not trn_rd_i(34))
|
791 |
|
|
& (trn_rd_i(32+19) and trn_rd_i(32+18) and not trn_rd_i(32+17) and not trn_rd_i(32+16) and trn_rd_i(34));
|
792 |
|
|
tab_wa_i <= trn_rd_i(32+3+11 downto 32+3);
|
793 |
|
|
tab_wa_odd <= trn_rd_i(32+2);
|
794 |
|
|
tab_wd_i <= Endian_Invert_64 ( (trn_rd_i(32-1 downto 0) & trn_rd_i(32-1 downto 0)) );
|
795 |
|
|
else
|
796 |
|
|
dg_table_Sel <= '0';
|
797 |
|
|
tab_we_i <= (OTHERS=>'0');
|
798 |
|
|
tab_wa_i <= trn_rd_i(32+3+11 downto 32+3);
|
799 |
|
|
tab_wa_odd <= trn_rd_i(32+2);
|
800 |
|
|
tab_wd_i <= Endian_Invert_64 ( (trn_rd_i(32-1 downto 0) & trn_rd_i(32-1 downto 0)));
|
801 |
|
|
end if;
|
802 |
|
|
|
803 |
|
|
when ST_MWr4_HEAD2 =>
|
804 |
|
|
if trn_rbar_hit_n_r1(CINT_DDR_SPACE_BAR)='0'
|
805 |
|
|
and Tlp_is_Zero_Length='0'
|
806 |
|
|
then
|
807 |
|
|
dg_table_Sel <= trn_rd_i(19) and trn_rd_i(18) and not trn_rd_i(17) and not trn_rd_i(16);
|
808 |
|
|
tab_we_i <= (OTHERS=>'0');
|
809 |
|
|
tab_wa_i <= trn_rd_i(3+11 downto 3);
|
810 |
|
|
tab_wa_odd <= trn_rd_i(2);
|
811 |
|
|
tab_wd_i <= Endian_Invert_64 ( (trn_rd_i(64-1 downto 32) & trn_rd_i(64-1 downto 32)));
|
812 |
|
|
else
|
813 |
|
|
dg_table_Sel <= '0';
|
814 |
|
|
tab_we_i <= (OTHERS=>'0');
|
815 |
|
|
tab_wa_i <= trn_rd_i(3+11 downto 3);
|
816 |
|
|
tab_wa_odd <= trn_rd_i(2);
|
817 |
|
|
tab_wd_i <= Endian_Invert_64 ((trn_rd_i(64-1 downto 32) & trn_rd_i(64-1 downto 32)));
|
818 |
|
|
end if;
|
819 |
|
|
|
820 |
|
|
|
821 |
|
|
when ST_MWr4_1ST_DATA =>
|
822 |
|
|
dg_table_Sel <= dg_table_Sel;
|
823 |
|
|
tab_we_i <= (dg_table_Sel and not trn_rx_throttle and not tab_wa_odd)
|
824 |
|
|
& (dg_table_Sel and not trn_rx_throttle and tab_wa_odd);
|
825 |
|
|
tab_wa_i <= tab_wa_i;
|
826 |
|
|
tab_wa_odd <= tab_wa_odd;
|
827 |
|
|
tab_wd_i <= Endian_Invert_64 ((trn_rd_i(64-1 downto 32) & trn_rd_i(64-1 downto 32)));
|
828 |
|
|
|
829 |
|
|
|
830 |
|
|
when ST_MWr_1ST_DATA_THROTTLE =>
|
831 |
|
|
dg_table_Sel <= dg_table_Sel;
|
832 |
|
|
tab_we_i <= (dg_table_Sel and not trn_rx_throttle and not tab_wa_odd)
|
833 |
|
|
& (dg_table_Sel and not trn_rx_throttle and tab_wa_odd);
|
834 |
|
|
tab_wa_i <= tab_wa_i;
|
835 |
|
|
tab_wa_odd <= tab_wa_odd;
|
836 |
|
|
tab_wd_i <= Endian_Invert_64 ((trn_rd_i(64-1 downto 32) & trn_rd_i(64-1 downto 32)));
|
837 |
|
|
|
838 |
|
|
|
839 |
|
|
when OTHERS =>
|
840 |
|
|
dg_table_Sel <= '0';
|
841 |
|
|
tab_we_i <= (OTHERS=>'0');
|
842 |
|
|
tab_wa_i <= tab_wa_i;
|
843 |
|
|
tab_wa_odd <= tab_wa_odd;
|
844 |
|
|
tab_wd_i <= Endian_Invert_64 ((trn_rd_i(64-1 downto 32) & trn_rd_i(64-1 downto 32)));
|
845 |
|
|
|
846 |
|
|
end case;
|
847 |
|
|
|
848 |
|
|
end if;
|
849 |
|
|
|
850 |
|
|
end process;
|
851 |
|
|
|
852 |
|
|
|
853 |
|
|
|
854 |
|
|
-- ----------------------------------------------
|
855 |
|
|
-- Synchronous outputs: EB FIFO Select --
|
856 |
|
|
-- ----------------------------------------------
|
857 |
|
|
RxFSM_Output_FIFO_Space_Selected:
|
858 |
|
|
process ( trn_clk, trn_reset_n)
|
859 |
|
|
begin
|
860 |
|
|
if trn_reset_n = '0' then
|
861 |
|
|
FIFO_Space_Sel <= '0';
|
862 |
|
|
eb_FIFO_we_i <= '0';
|
863 |
|
|
eb_FIFO_wsof_i <= '0';
|
864 |
|
|
eb_FIFO_weof_i <= '0';
|
865 |
|
|
eb_FIFO_din_i <= (OTHERS=>'0');
|
866 |
|
|
|
867 |
|
|
elsif trn_clk'event and trn_clk = '1' then
|
868 |
|
|
|
869 |
|
|
case RxMWrTrn_State is
|
870 |
|
|
|
871 |
|
|
when ST_MWr3_HEAD2 =>
|
872 |
|
|
if trn_rbar_hit_n_r1(CINT_FIFO_SPACE_BAR)='0'
|
873 |
|
|
and Tlp_is_Zero_Length='0'
|
874 |
|
|
then
|
875 |
|
|
FIFO_Space_Sel <= '1';
|
876 |
|
|
eb_FIFO_we_i <= not trn_reof_n_i; -- '1';
|
877 |
|
|
eb_FIFO_wsof_i <= not trn_reof_n_i; -- '1';
|
878 |
|
|
eb_FIFO_weof_i <= not trn_reof_n_i; -- '1';
|
879 |
|
|
eb_FIFO_din_i <= Endian_Invert_64 ((trn_rd_i(32-1 downto 0) & trn_rd_i(32-1 downto 0)));
|
880 |
|
|
else
|
881 |
|
|
FIFO_Space_Sel <= '0';
|
882 |
|
|
eb_FIFO_we_i <= '0';
|
883 |
|
|
eb_FIFO_wsof_i <= '0';
|
884 |
|
|
eb_FIFO_weof_i <= '0';
|
885 |
|
|
eb_FIFO_din_i <= Endian_Invert_64 ((trn_rd_i(32-1 downto 0) & trn_rd_i(32-1 downto 0)));
|
886 |
|
|
end if;
|
887 |
|
|
|
888 |
|
|
when ST_MWr_1ST_DATA =>
|
889 |
|
|
FIFO_Space_Sel <= FIFO_Space_Sel;
|
890 |
|
|
eb_FIFO_we_i <= FIFO_Space_Sel and not trn_reof_n_i; -- '1';
|
891 |
|
|
eb_FIFO_wsof_i <= FIFO_Space_Sel and not trn_reof_n_i; -- '1';
|
892 |
|
|
eb_FIFO_weof_i <= FIFO_Space_Sel and not trn_reof_n_i; -- '1';
|
893 |
|
|
eb_FIFO_din_i <= Endian_Invert_64 (( trn_rd_r1(32-1 downto 0) & trn_rd_i(64-1 downto 32) ));
|
894 |
|
|
|
895 |
|
|
|
896 |
|
|
when ST_MWr4_HEAD2 =>
|
897 |
|
|
if trn_rbar_hit_n_r1(CINT_FIFO_SPACE_BAR)='0'
|
898 |
|
|
and Tlp_is_Zero_Length='0'
|
899 |
|
|
then
|
900 |
|
|
FIFO_Space_Sel <= '1';
|
901 |
|
|
eb_FIFO_we_i <= '0';
|
902 |
|
|
eb_FIFO_wsof_i <= '0';
|
903 |
|
|
eb_FIFO_weof_i <= '0';
|
904 |
|
|
eb_FIFO_din_i <= (OTHERS=>'0');
|
905 |
|
|
else
|
906 |
|
|
FIFO_Space_Sel <= '0';
|
907 |
|
|
eb_FIFO_we_i <= '0';
|
908 |
|
|
eb_FIFO_wsof_i <= '0';
|
909 |
|
|
eb_FIFO_weof_i <= '0';
|
910 |
|
|
eb_FIFO_din_i <= (OTHERS=>'0');
|
911 |
|
|
end if;
|
912 |
|
|
|
913 |
|
|
when ST_MWr4_1ST_DATA =>
|
914 |
|
|
FIFO_Space_Sel <= FIFO_Space_Sel;
|
915 |
|
|
eb_FIFO_we_i <= FIFO_Space_Sel and not trn_reof_n_i; -- trn_rx_throttle;
|
916 |
|
|
eb_FIFO_wsof_i <= FIFO_Space_Sel and not trn_reof_n_i; -- trn_rx_throttle;
|
917 |
|
|
eb_FIFO_weof_i <= FIFO_Space_Sel and not trn_reof_n_i; -- trn_rx_throttle;
|
918 |
|
|
if trn_rrem_n_i(3)='1' or trn_rrem_n_i(0)='1' then
|
919 |
|
|
eb_FIFO_din_i <= Endian_Invert_64 ((trn_rd_i(64-1 downto 32) & trn_rd_i(64-1 downto 32)));
|
920 |
|
|
else
|
921 |
|
|
eb_FIFO_din_i <= Endian_Invert_64 (trn_rd_i);
|
922 |
|
|
end if;
|
923 |
|
|
|
924 |
|
|
when ST_MWr_1ST_DATA_THROTTLE =>
|
925 |
|
|
if MWr_Has_4DW_Header='1' then
|
926 |
|
|
FIFO_Space_Sel <= FIFO_Space_Sel;
|
927 |
|
|
eb_FIFO_we_i <= FIFO_Space_Sel and not trn_reof_n_i; -- trn_rx_throttle;
|
928 |
|
|
eb_FIFO_wsof_i <= FIFO_Space_Sel and not trn_reof_n_i; -- trn_rx_throttle;
|
929 |
|
|
eb_FIFO_weof_i <= FIFO_Space_Sel and not trn_reof_n_i; -- trn_rx_throttle;
|
930 |
|
|
if trn_rrem_n_i(3)='1' or trn_rrem_n_i(0)='1' then
|
931 |
|
|
eb_FIFO_din_i <= Endian_Invert_64 ((trn_rd_i(64-1 downto 32) & trn_rd_i(64-1 downto 32)));
|
932 |
|
|
else
|
933 |
|
|
eb_FIFO_din_i <= Endian_Invert_64 (trn_rd_i);
|
934 |
|
|
end if;
|
935 |
|
|
else
|
936 |
|
|
FIFO_Space_Sel <= FIFO_Space_Sel;
|
937 |
|
|
eb_FIFO_we_i <= FIFO_Space_Sel and not trn_reof_n_i; -- '1';
|
938 |
|
|
eb_FIFO_wsof_i <= FIFO_Space_Sel and not trn_reof_n_i; -- '1';
|
939 |
|
|
eb_FIFO_weof_i <= FIFO_Space_Sel and not trn_reof_n_i; -- '1';
|
940 |
|
|
eb_FIFO_din_i <= Endian_Invert_64 (( trn_rd_r1(32-1 downto 0) & trn_rd_i(64-1 downto 32) ));
|
941 |
|
|
end if;
|
942 |
|
|
|
943 |
|
|
when OTHERS =>
|
944 |
|
|
FIFO_Space_Sel <= '0';
|
945 |
|
|
eb_FIFO_we_i <= '0';
|
946 |
|
|
eb_FIFO_wsof_i <= '0';
|
947 |
|
|
eb_FIFO_weof_i <= '0';
|
948 |
|
|
eb_FIFO_din_i <= (OTHERS=>'0');
|
949 |
|
|
|
950 |
|
|
end case;
|
951 |
|
|
|
952 |
|
|
end if;
|
953 |
|
|
|
954 |
|
|
end process;
|
955 |
|
|
|
956 |
|
|
|
957 |
|
|
end architecture Behavioral;
|