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[/] [pcie_sg_dma/] [trunk/] [rtl/] [rx_Transact.vhd] - Blame information for rev 2

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Line No. Rev Author Line
1 2 weng_ziti 
----------------------------------------------------------------------------------
2 
-- Company:  ziti, Uni. HD
3 
-- Engineer:  wgao
4 
--
5 
-- Design Name:
6 
-- Module Name:    rx_Transact - Behavioral
7 
-- Project Name:
8 
-- Target Devices:
9 
-- Tool versions:
10 
-- Description:
11 
--
12 
-- Dependencies:
13 
--
14 
-- Revision 1.00 - first release.  14.12.2006
15 
--
16 
-- Additional Comments:
17 
--
18 
----------------------------------------------------------------------------------
19 
 
20 
library IEEE;
21 
use IEEE.STD_LOGIC_1164.ALL;
22 
use IEEE.STD_LOGIC_ARITH.ALL;
23 
use IEEE.STD_LOGIC_UNSIGNED.ALL;
24 
 
25 
library work;
26 
use work.abb64Package.all;
27 
 
28 
 
29 
-- Uncomment the following library declaration if instantiating
30 
-- any Xilinx primitives in this code.
31 
--library UNISIM;
32 
--use UNISIM.VComponents.all;
33 
 
34 
entity rx_Transact is
35 
    port (
36 
      -- Common ports
37 
      trn_clk                   : IN  std_logic;
38 
      trn_reset_n               : IN  std_logic;
39 
      trn_lnk_up_n              : IN  std_logic;
40 
 
41 
      -- Transaction receive interface
42 
      trn_rsof_n                : IN  std_logic;
43 
      trn_reof_n                : IN  std_logic;
44 
      trn_rd                    : IN  std_logic_vector(C_DBUS_WIDTH-1 downto 0);
45 
      trn_rrem_n                : IN  std_logic_vector(C_DBUS_WIDTH/8-1 downto 0);
46 
      trn_rerrfwd_n             : IN  std_logic;
47 
      trn_rsrc_rdy_n            : IN  std_logic;
48 
      trn_rdst_rdy_n            : OUT std_logic;
49 
      trn_rnp_ok_n              : OUT std_logic;
50 
      trn_rsrc_dsc_n            : IN  std_logic;
51 
      trn_rbar_hit_n            : IN  std_logic_vector(C_BAR_NUMBER-1 downto 0);
52 
--      trn_rfc_ph_av             : IN  std_logic_vector(7 downto 0);
53 
--      trn_rfc_pd_av             : IN  std_logic_vector(11 downto 0);
54 
--      trn_rfc_nph_av            : IN  std_logic_vector(7 downto 0);
55 
--      trn_rfc_npd_av            : IN  std_logic_vector(11 downto 0);
56 
--      trn_rfc_cplh_av           : IN  std_logic_vector(7 downto 0);
57 
--      trn_rfc_cpld_av           : IN  std_logic_vector(11 downto 0);
58 
 
59 
      -- PIO MRd Channel
60 
      pioCplD_Req               : OUT std_logic;
61 
      pioCplD_RE                : IN  std_logic;
62 
      pioCplD_Qout              : OUT std_logic_vector(C_CHANNEL_BUF_WIDTH-1 downto 0);
63 
      pio_FC_stop               : IN  std_logic;
64 
 
65 
      -- downstream MRd Channel
66 
      dsMRd_Req                 : OUT std_logic;
67 
      dsMRd_RE                  : IN  std_logic;
68 
      dsMRd_Qout                : OUT std_logic_vector(C_CHANNEL_BUF_WIDTH-1 downto 0);
69 
 
70 
      -- upstream MWr/MRd Channel
71 
      usTlp_Req                 : OUT std_logic;
72 
      usTlp_RE                  : IN  std_logic;
73 
      usTlp_Qout                : OUT std_logic_vector(C_CHANNEL_BUF_WIDTH-1 downto 0);
74 
      us_FC_stop                : IN  std_logic;
75 
      us_Last_sof               : IN  std_logic;
76 
      us_Last_eof               : IN  std_logic;
77 
 
78 
      -- Irpt Channel
79 
      Irpt_Req                  : OUT std_logic;
80 
      Irpt_RE                   : IN  std_logic;
81 
      Irpt_Qout                 : OUT std_logic_vector(C_CHANNEL_BUF_WIDTH-1 downto 0);
82 
 
83 
      -- Interrupt Interface
84 
                cfg_interrupt_n           : OUT std_logic;
85 
                cfg_interrupt_rdy_n       : IN  std_logic;
86 
                cfg_interrupt_mmenable    : IN  std_logic_VECTOR(2 downto 0);
87 
                cfg_interrupt_msienable   : IN  std_logic;
88 
                cfg_interrupt_di          : OUT std_logic_VECTOR(7 downto 0);
89 
                cfg_interrupt_do          : IN  std_logic_VECTOR(7 downto 0);
90 
                cfg_interrupt_assert_n    : OUT std_logic;
91 
 
92 
      -- Downstream DMA transferred bytes count up
93 
      ds_DMA_Bytes_Add          : OUT std_logic;
94 
      ds_DMA_Bytes              : OUT std_logic_vector(C_TLP_FLD_WIDTH_OF_LENG+2 downto 0);
95 
 
96 
      -- --------------------------
97 
      -- Registers
98 
      DMA_ds_PA                 : IN  std_logic_vector(C_DBUS_WIDTH-1 downto 0);
99 
      DMA_ds_HA                 : IN  std_logic_vector(C_DBUS_WIDTH-1 downto 0);
100 
      DMA_ds_BDA                : IN  std_logic_vector(C_DBUS_WIDTH-1 downto 0);
101 
      DMA_ds_Length             : IN  std_logic_vector(C_DBUS_WIDTH-1 downto 0);
102 
      DMA_ds_Control            : IN  std_logic_vector(C_DBUS_WIDTH-1 downto 0);
103 
      dsDMA_BDA_eq_Null         : IN  std_logic;
104 
      DMA_ds_Status             : OUT std_logic_vector(C_DBUS_WIDTH-1 downto 0);
105 
      DMA_ds_Done               : OUT std_logic;
106 
      DMA_ds_Busy               : OUT std_logic;
107 
      DMA_ds_Tout               : OUT std_logic;
108 
 
109 
      -- Calculation in advance, for better timing
110 
      dsHA_is_64b               : IN  std_logic;
111 
      dsBDA_is_64b              : IN  std_logic;
112 
 
113 
      -- Calculation in advance, for better timing
114 
      dsLeng_Hi19b_True         : IN  std_logic;
115 
      dsLeng_Lo7b_True          : IN  std_logic;
116 
 
117 
      --
118 
      dsDMA_Start               : IN  std_logic;
119 
      dsDMA_Stop                : IN  std_logic;
120 
      dsDMA_Start2              : IN  std_logic;
121 
      dsDMA_Stop2               : IN  std_logic;
122 
      dsDMA_Channel_Rst         : IN  std_logic;
123 
      dsDMA_Cmd_Ack             : OUT std_logic;
124 
 
125 
      --
126 
      DMA_us_PA                 : IN  std_logic_vector(C_DBUS_WIDTH-1 downto 0);
127 
      DMA_us_HA                 : IN  std_logic_vector(C_DBUS_WIDTH-1 downto 0);
128 
      DMA_us_BDA                : IN  std_logic_vector(C_DBUS_WIDTH-1 downto 0);
129 
      DMA_us_Length             : IN  std_logic_vector(C_DBUS_WIDTH-1 downto 0);
130 
      DMA_us_Control            : IN  std_logic_vector(C_DBUS_WIDTH-1 downto 0);
131 
      usDMA_BDA_eq_Null         : IN  std_logic;
132 
      us_MWr_Param_Vec          : IN  std_logic_vector(6-1   downto 0);
133 
      DMA_us_Status             : OUT std_logic_vector(C_DBUS_WIDTH-1 downto 0);
134 
      DMA_us_Done               : OUT std_logic;
135 
      DMA_us_Busy               : OUT std_logic;
136 
      DMA_us_Tout               : OUT std_logic;
137 
 
138 
      -- Calculation in advance, for better timing
139 
      usHA_is_64b               : IN  std_logic;
140 
      usBDA_is_64b              : IN  std_logic;
141 
 
142 
      -- Calculation in advance, for better timing
143 
      usLeng_Hi19b_True         : IN  std_logic;
144 
      usLeng_Lo7b_True          : IN  std_logic;
145 
 
146 
      --
147 
      usDMA_Start               : IN  std_logic;
148 
      usDMA_Stop                : IN  std_logic;
149 
      usDMA_Start2              : IN  std_logic;
150 
      usDMA_Stop2               : IN  std_logic;
151 
      usDMA_Channel_Rst         : IN  std_logic;
152 
      usDMA_Cmd_Ack             : OUT std_logic;
153 
 
154 
      MRd_Channel_Rst           : IN  std_logic;
155 
 
156 
      -- to Interrupt module
157 
      Sys_IRQ                   : IN  std_logic_vector(C_DBUS_WIDTH-1 downto 0);
158 
 
159 
 
160 
      -- Event Buffer write port
161 
      eb_FIFO_we                : OUT std_logic;
162 
      eb_FIFO_wsof              : OUT std_logic;
163 
      eb_FIFO_weof              : OUT std_logic;
164 
      eb_FIFO_din               : OUT std_logic_vector(C_DBUS_WIDTH-1 downto 0);
165 
 
166 
      eb_FIFO_data_count        : IN  std_logic_vector(C_FIFO_DC_WIDTH downto 0);
167 
      eb_FIFO_Empty             : IN  std_logic;
168 
      eb_FIFO_Reading           : IN  std_logic;
169 
      pio_reading_status        : OUT std_logic;
170 
 
171 
      Link_Buf_full             : IN  std_logic;
172 
 
173 
      -- Registers Write Port
174 
      Regs_WrEn0                : OUT std_logic;
175 
      Regs_WrMask0              : OUT std_logic_vector(2-1 downto 0);
176 
      Regs_WrAddr0              : OUT std_logic_vector(C_EP_AWIDTH-1 downto 0);
177 
      Regs_WrDin0               : OUT std_logic_vector(C_DBUS_WIDTH-1 downto 0);
178 
 
179 
      Regs_WrEn1                : OUT std_logic;
180 
      Regs_WrMask1              : OUT std_logic_vector(2-1 downto 0);
181 
      Regs_WrAddr1              : OUT std_logic_vector(C_EP_AWIDTH-1 downto 0);
182 
      Regs_WrDin1               : OUT std_logic_vector(C_DBUS_WIDTH-1 downto 0);
183 
 
184 
      -- DDR write port
185 
      DDR_wr_sof_A              : OUT std_logic;
186 
      DDR_wr_eof_A              : OUT std_logic;
187 
      DDR_wr_v_A                : OUT std_logic;
188 
      DDR_wr_FA_A               : OUT std_logic;
189 
      DDR_wr_Shift_A            : OUT std_logic;
190 
      DDR_wr_Mask_A             : OUT std_logic_vector(2-1 downto 0);
191 
      DDR_wr_din_A              : OUT std_logic_vector(C_DBUS_WIDTH-1 downto 0);
192 
 
193 
      DDR_wr_sof_B              : OUT std_logic;
194 
      DDR_wr_eof_B              : OUT std_logic;
195 
      DDR_wr_v_B                : OUT std_logic;
196 
      DDR_wr_FA_B               : OUT std_logic;
197 
      DDR_wr_Shift_B            : OUT std_logic;
198 
      DDR_wr_Mask_B             : OUT std_logic_vector(2-1 downto 0);
199 
      DDR_wr_din_B              : OUT std_logic_vector(C_DBUS_WIDTH-1 downto 0);
200 
 
201 
      DDR_wr_full               : IN  std_logic;
202 
 
203 
      -- Data generator table write
204 
      tab_we                    : OUT std_logic_vector(2-1 downto 0);
205 
      tab_wa                    : OUT std_logic_vector(12-1 downto 0);
206 
      tab_wd                    : OUT std_logic_vector(C_DBUS_WIDTH-1 downto 0);
207 
 
208 
      -- Interrupt generator signals
209 
      IG_Reset                  : IN  std_logic;
210 
      IG_Host_Clear             : IN  std_logic;
211 
      IG_Latency                : IN  std_logic_vector(C_DBUS_WIDTH-1   downto 0);
212 
      IG_Num_Assert             : OUT std_logic_vector(C_DBUS_WIDTH-1   downto 0);
213 
      IG_Num_Deassert           : OUT std_logic_vector(C_DBUS_WIDTH-1   downto 0);
214 
      IG_Asserting              : OUT std_logic;
215 
 
216 
      -- Additional
217 
      cfg_dcommand              : IN  std_logic_vector(C_CFG_COMMAND_DWIDTH-1 downto 0);
218 
      localID                   : IN  std_logic_vector(C_ID_WIDTH-1 downto 0)
219 
    );
220 
 
221 
end entity rx_Transact;
222 
 
223 
 
224 
architecture Behavioral of rx_Transact is
225 
 
226 
   signal  eb_FIFO_we_i         : std_logic;
227 
   signal  eb_FIFO_wsof_i       : std_logic;
228 
   signal  eb_FIFO_weof_i       : std_logic;
229 
   signal  eb_FIFO_din_i        : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
230 
 
231 
    ------------------------------------------------------------------
232 
    --  Rx input delay
233 
    --  some calculation in advance, to achieve better timing
234 
    --
235 
    COMPONENT
236 
    RxIn_Delay
237 
    PORT (
238 
      -- Common ports
239 
      trn_clk                   : IN  std_logic;
240 
      trn_reset_n               : IN  std_logic;
241 
      trn_lnk_up_n              : IN  std_logic;
242 
 
243 
      -- Transaction receive interface
244 
      trn_rsof_n                : IN  std_logic;
245 
      trn_reof_n                : IN  std_logic;
246 
      trn_rd                    : IN  std_logic_vector(C_DBUS_WIDTH-1 downto 0);
247 
      trn_rrem_n                : IN  std_logic_vector(C_DBUS_WIDTH/8-1 downto 0);
248 
      trn_rerrfwd_n             : IN  std_logic;
249 
      trn_rsrc_rdy_n            : IN  std_logic;
250 
      trn_rsrc_dsc_n            : IN  std_logic;
251 
      trn_rbar_hit_n            : IN  std_logic_vector(C_BAR_NUMBER-1 downto 0);
252 
      trn_rdst_rdy_n            : OUT std_logic;
253 
      Pool_wrBuf_full           : IN  std_logic;
254 
      Link_Buf_full             : IN  std_logic;
255 
 
256 
      -- Delayed
257 
      trn_rsof_n_dly            : OUT std_logic;
258 
      trn_reof_n_dly            : OUT std_logic;
259 
      trn_rd_dly                : OUT std_logic_vector(C_DBUS_WIDTH-1 downto 0);
260 
      trn_rrem_n_dly            : OUT std_logic_vector(C_DBUS_WIDTH/8-1 downto 0);
261 
      trn_rerrfwd_n_dly         : OUT std_logic;
262 
      trn_rsrc_rdy_n_dly        : OUT std_logic;
263 
      trn_rdst_rdy_n_dly        : OUT std_logic;
264 
      trn_rsrc_dsc_n_dly        : OUT std_logic;
265 
      trn_rbar_hit_n_dly        : OUT std_logic_vector(C_BAR_NUMBER-1 downto 0);
266 
 
267 
      -- TLP resolution
268 
      IORd_Type                 : OUT std_logic;
269 
      IOWr_Type                 : OUT std_logic;
270 
      MRd_Type                  : OUT std_logic_vector(3 downto 0);
271 
      MWr_Type                  : OUT std_logic_vector(1 downto 0);
272 
      CplD_Type                 : OUT std_logic_vector(3 downto 0);
273 
 
274 
      -- From Cpl/D channel
275 
      usDMA_dex_Tag             : IN  std_logic_vector(C_TAG_WIDTH-1 downto 0);
276 
      dsDMA_dex_Tag             : IN  std_logic_vector(C_TAG_WIDTH-1 downto 0);
277 
 
278 
      -- To Memory request process modules
279 
      Tlp_straddles_4KB         : OUT std_logic;
280 
 
281 
      -- To Cpl/D channel
282 
      Tlp_has_4KB               : OUT std_logic;
283 
      Tlp_has_1DW               : OUT std_logic;
284 
      CplD_is_the_Last          : OUT std_logic;
285 
      CplD_on_Pool              : OUT std_logic;
286 
      CplD_on_EB                : OUT std_logic;
287 
      Req_ID_Match              : OUT std_logic;
288 
      usDex_Tag_Matched         : OUT std_logic;
289 
      dsDex_Tag_Matched         : OUT std_logic;
290 
      CplD_Tag                  : OUT std_logic_vector(C_TAG_WIDTH-1 downto  0);
291 
 
292 
      -- Additional
293 
      cfg_dcommand              : IN  std_logic_vector(C_CFG_COMMAND_DWIDTH-1 downto 0);
294 
      localID                   : IN  std_logic_vector(C_ID_WIDTH-1 downto 0)
295 
    );
296 
    END COMPONENT;
297 
 
298 
   -- One clock delayed
299 
   signal   trn_rsof_n_dly      :  std_logic;
300 
   signal   trn_reof_n_dly      :  std_logic;
301 
   signal   trn_rd_dly          :  std_logic_vector(C_DBUS_WIDTH-1 downto 0);
302 
   signal   trn_rrem_n_dly      :  std_logic_vector(C_DBUS_WIDTH/8-1 downto 0);
303 
   signal   trn_rerrfwd_n_dly   :  std_logic;
304 
   signal   trn_rsrc_rdy_n_dly  :  std_logic;
305 
   signal   trn_rdst_rdy_n_dly  :  std_logic;
306 
   signal   trn_rsrc_dsc_n_dly  :  std_logic;
307 
   signal   trn_rbar_hit_n_dly  :  std_logic_vector(C_BAR_NUMBER-1 downto 0);
308 
 
309 
   -- TLP types
310 
   signal   IORd_Type           :  std_logic;
311 
   signal   IOWr_Type           :  std_logic;
312 
   signal   MRd_Type            :  std_logic_vector(3 downto 0);
313 
   signal   MWr_Type            :  std_logic_vector(1 downto 0);
314 
   signal   CplD_Type           :  std_logic_vector(3 downto 0);
315 
 
316 
   signal   Tlp_straddles_4KB   :  std_logic;
317 
 
318 
   -- To Cpl/D channel
319 
   signal   Tlp_has_4KB         :  std_logic;
320 
   signal   Tlp_has_1DW         :  std_logic;
321 
   signal   CplD_is_the_Last    :  std_logic;
322 
   signal   CplD_on_Pool        :  std_logic;
323 
   signal   CplD_on_EB          :  std_logic;
324 
   signal   Req_ID_Match        :  std_logic;
325 
   signal   usDex_Tag_Matched   :  std_logic;
326 
   signal   dsDex_Tag_Matched   :  std_logic;
327 
   signal   CplD_Tag            :  std_logic_vector(C_TAG_WIDTH-1 downto  0);
328 
 
329 
 
330 
   ------------------------------------------------------------------
331 
   --  MRd TLP processing
332 
   --   contains channel buffer for PIO Completions
333 
   --
334 
        COMPONENT
335 
   rx_MRd_Transact
336 
        PORT(
337 
                trn_rsof_n                : IN  std_logic;
338 
                trn_reof_n                : IN  std_logic;
339 
                trn_rd                    : IN  std_logic_vector(C_DBUS_WIDTH-1 downto 0);
340 
      trn_rrem_n                : IN  std_logic_vector(C_DBUS_WIDTH/8-1 downto 0);
341 
--              trn_rdst_rdy_n            : OUT std_logic;
342 
                trn_rnp_ok_n              : OUT std_logic;  -----------------
343 
                trn_rerrfwd_n             : IN  std_logic;
344 
                trn_rsrc_rdy_n            : IN  std_logic;
345 
                trn_rsrc_dsc_n            : IN  std_logic;
346 
                trn_rbar_hit_n            : IN  std_logic_vector(C_BAR_NUMBER-1 downto 0);
347 
 
348 
      IORd_Type                 : IN  std_logic;
349 
      MRd_Type                  : IN  std_logic_vector(3 downto 0);
350 
      Tlp_straddles_4KB         : IN  std_logic;
351 
 
352 
                pioCplD_RE                : IN  std_logic;
353 
                pioCplD_Req               : OUT std_logic;
354 
                pioCplD_Qout              : OUT std_logic_vector(C_CHANNEL_BUF_WIDTH-1 downto 0);
355 
      FIFO_Empty                : IN  std_logic;
356 
      FIFO_Reading              : IN  std_logic;
357 
      pio_FC_stop               : IN  std_logic;
358 
      pio_reading_status        : OUT std_logic;
359 
 
360 
      Channel_Rst               : IN  std_logic;
361 
 
362 
                trn_clk                   : IN  std_logic;
363 
                trn_reset_n               : IN  std_logic;
364 
                trn_lnk_up_n              : IN  std_logic
365 
                );
366 
        END COMPONENT;
367 
 
368 
 
369 
   ------------------------------------------------------------------
370 
   --  MWr TLP processing
371 
   --
372 
        COMPONENT
373 
   rx_MWr_Transact
374 
        PORT(
375 
      --
376 
                trn_rsof_n                : IN  std_logic;
377 
                trn_reof_n                : IN  std_logic;
378 
                trn_rd                    : IN  std_logic_vector(C_DBUS_WIDTH-1 downto 0);
379 
      trn_rrem_n                : IN  std_logic_vector(C_DBUS_WIDTH/8-1 downto 0);
380 
                trn_rdst_rdy_n            : IN  std_logic;  -- !!
381 
                trn_rerrfwd_n             : IN  std_logic;
382 
                trn_rsrc_rdy_n            : IN  std_logic;
383 
                trn_rsrc_dsc_n            : IN  std_logic;
384 
                trn_rbar_hit_n            : IN  std_logic_vector(C_BAR_NUMBER-1 downto 0);
385 
 
386 
      IOWr_Type                 : IN  std_logic;
387 
      MWr_Type                  : IN  std_logic_vector(1 downto 0);
388 
      Tlp_straddles_4KB         : IN  std_logic;
389 
      Tlp_has_4KB               : IN  std_logic;
390 
 
391 
 
392 
      -- Event Buffer write port
393 
      eb_FIFO_we                : OUT std_logic;
394 
      eb_FIFO_wsof              : OUT std_logic;
395 
      eb_FIFO_weof              : OUT std_logic;
396 
      eb_FIFO_din               : OUT std_logic_vector(C_DBUS_WIDTH-1 downto 0);
397 
 
398 
      -- Registers Write Port
399 
      Regs_WrEn                 : OUT std_logic;
400 
      Regs_WrMask               : OUT std_logic_vector(2-1 downto 0);
401 
      Regs_WrAddr               : OUT std_logic_vector(C_EP_AWIDTH-1 downto 0);
402 
      Regs_WrDin                : OUT std_logic_vector(C_DBUS_WIDTH-1 downto 0);
403 
 
404 
      -- DDR write port
405 
      DDR_wr_sof                : OUT std_logic;
406 
      DDR_wr_eof                : OUT std_logic;
407 
      DDR_wr_v                  : OUT std_logic;
408 
      DDR_wr_FA                 : OUT std_logic;
409 
      DDR_wr_Shift              : OUT std_logic;
410 
      DDR_wr_Mask               : OUT std_logic_vector(2-1 downto 0);
411 
      DDR_wr_din                : OUT std_logic_vector(C_DBUS_WIDTH-1 downto 0);
412 
      DDR_wr_full               : IN  std_logic;
413 
 
414 
      -- Data generator table write
415 
      tab_we             : OUT std_logic_vector(2-1 downto 0);
416 
      tab_wa             : OUT std_logic_vector(12-1 downto 0);
417 
      tab_wd             : OUT std_logic_vector(C_DBUS_WIDTH-1 downto 0);
418 
 
419 
      -- Common
420 
                trn_clk                   : IN  std_logic;
421 
                trn_reset_n               : IN  std_logic;
422 
                trn_lnk_up_n              : IN  std_logic
423 
 
424 
                );
425 
        END COMPONENT;
426 
 
427 
   signal  eb_FIFO_we_MWr       : std_logic;
428 
   signal  eb_FIFO_wsof_MWr     : std_logic;
429 
   signal  eb_FIFO_weof_MWr     : std_logic;
430 
   signal  eb_FIFO_din_MWr      : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
431 
 
432 
 
433 
   ------------------------------------------------------------------
434 
   --  Cpl/D TLP processing
435 
   --
436 
        COMPONENT
437 
   rx_CplD_Transact
438 
        PORT(
439 
                trn_rsof_n                : IN  std_logic;
440 
                trn_reof_n                : IN  std_logic;
441 
                trn_rd                    : IN  std_logic_vector(C_DBUS_WIDTH-1 downto 0);
442 
      trn_rrem_n                : IN  std_logic_vector(C_DBUS_WIDTH/8-1 downto 0);
443 
                trn_rdst_rdy_n            : IN  std_logic;
444 
                trn_rerrfwd_n             : IN  std_logic;
445 
                trn_rsrc_rdy_n            : IN  std_logic;
446 
                trn_rsrc_dsc_n            : IN  std_logic;
447 
                trn_rbar_hit_n            : IN  std_logic_vector(C_BAR_NUMBER-1 downto 0);
448 
 
449 
      CplD_Type                 : IN  std_logic_vector(3 downto 0);
450 
 
451 
      Req_ID_Match              : IN  std_logic;
452 
      usDex_Tag_Matched         : IN  std_logic;
453 
      dsDex_Tag_Matched         : IN  std_logic;
454 
 
455 
      Tlp_has_4KB               : IN  std_logic;
456 
      Tlp_has_1DW               : IN  std_logic;
457 
      CplD_is_the_Last          : IN  std_logic;
458 
      CplD_on_Pool              : IN  std_logic;
459 
      CplD_on_EB                : IN  std_logic;
460 
      CplD_Tag                  : IN  std_logic_vector(C_TAG_WIDTH-1 downto  0);
461 
      FC_pop                    : OUT std_logic;
462 
 
463 
      -- Downstream DMA transferred bytes count up
464 
      ds_DMA_Bytes_Add          : OUT std_logic;
465 
      ds_DMA_Bytes              : OUT std_logic_vector(C_TLP_FLD_WIDTH_OF_LENG+2 downto 0);
466 
 
467 
      -- for descriptor of the downstream DMA
468 
      dsDMA_Dex_Tag             : OUT std_logic_vector(C_TAG_WIDTH-1 downto 0);
469 
 
470 
      -- Downstream Handshake Signals with ds Channel for Busy/Done
471 
      Tag_Map_Clear             : OUT std_logic_vector(C_TAG_MAP_WIDTH-1 downto 0);
472 
 
473 
      -- Downstream tRAM port A write request
474 
      tRAM_weB                  : IN  std_logic;
475 
      tRAM_addrB                : IN  std_logic_vector(C_TAGRAM_AWIDTH-1 downto 0);
476 
      tRAM_dinB                 : IN  std_logic_vector(C_TAGRAM_DWIDTH-1 downto 0);
477 
 
478 
      -- for descriptor of the upstream DMA
479 
      usDMA_dex_Tag             : OUT std_logic_vector(C_TAG_WIDTH-1 downto 0);
480 
 
481 
 
482 
      -- Event Buffer write port
483 
      eb_FIFO_we                : OUT std_logic;
484 
      eb_FIFO_wsof              : OUT std_logic;
485 
      eb_FIFO_weof              : OUT std_logic;
486 
      eb_FIFO_din               : OUT std_logic_vector(C_DBUS_WIDTH-1 downto 0);
487 
 
488 
      -- Registers Write Port
489 
      Regs_WrEn                 : OUT std_logic;
490 
      Regs_WrMask               : OUT std_logic_vector(2-1 downto 0);
491 
      Regs_WrAddr               : OUT std_logic_vector(C_EP_AWIDTH-1 downto 0);
492 
      Regs_WrDin                : OUT std_logic_vector(C_DBUS_WIDTH-1 downto 0);
493 
 
494 
      -- DDR write port
495 
      DDR_wr_sof                : OUT std_logic;
496 
      DDR_wr_eof                : OUT std_logic;
497 
      DDR_wr_v                  : OUT std_logic;
498 
      DDR_wr_FA                 : OUT std_logic;
499 
      DDR_wr_Shift              : OUT std_logic;
500 
      DDR_wr_Mask               : OUT std_logic_vector(2-1 downto 0);
501 
      DDR_wr_din                : OUT std_logic_vector(C_DBUS_WIDTH-1 downto 0);
502 
      DDR_wr_full               : IN  std_logic;
503 
 
504 
      -- Common signals
505 
                trn_clk                   : IN  std_logic;
506 
                trn_reset_n               : IN  std_logic;
507 
                trn_lnk_up_n              : IN  std_logic
508 
                );
509 
        END COMPONENT;
510 
 
511 
   signal  eb_FIFO_we_CplD      : std_logic;
512 
   signal  eb_FIFO_wsof_CplD    : std_logic;
513 
   signal  eb_FIFO_weof_CplD    : std_logic;
514 
   signal  eb_FIFO_din_CplD     : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
515 
 
516 
   signal  usDMA_dex_Tag        : std_logic_vector(C_TAG_WIDTH-1 downto 0);
517 
   signal  dsDMA_dex_Tag        : std_logic_vector(C_TAG_WIDTH-1 downto 0);
518 
 
519 
   signal  Tag_Map_Clear        : std_logic_vector(C_TAG_MAP_WIDTH-1 downto 0);
520 
   signal  FC_pop               : std_logic;
521 
 
522 
 
523 
   ------------------------------------------------------------------
524 
   --  Interrupts generation
525 
   --
526 
   COMPONENT
527 
   Interrupts
528 
   PORT(
529 
      Sys_IRQ                   : IN  std_logic_vector(C_DBUS_WIDTH-1 downto 0);
530 
 
531 
      -- Interrupt generator signals
532 
      IG_Reset                  : IN  std_logic;
533 
      IG_Host_Clear             : IN  std_logic;
534 
      IG_Latency                : IN  std_logic_vector(C_DBUS_WIDTH-1   downto 0);
535 
      IG_Num_Assert             : OUT std_logic_vector(C_DBUS_WIDTH-1   downto 0);
536 
      IG_Num_Deassert           : OUT std_logic_vector(C_DBUS_WIDTH-1   downto 0);
537 
      IG_Asserting              : OUT std_logic;
538 
 
539 
      -- cfg interface
540 
      cfg_interrupt_n           : OUT std_logic;
541 
      cfg_interrupt_rdy_n       : IN  std_logic;
542 
      cfg_interrupt_mmenable    : IN  std_logic_vector(2 downto 0);
543 
      cfg_interrupt_msienable   : IN  std_logic;
544 
      cfg_interrupt_di          : OUT std_logic_vector(7 downto 0);
545 
      cfg_interrupt_do          : IN  std_logic_vector(7 downto 0);
546 
      cfg_interrupt_assert_n    : OUT std_logic;
547 
 
548 
      -- Irpt Channel
549 
      Irpt_Req                  : OUT std_logic;
550 
      Irpt_RE                   : IN  std_logic;
551 
      Irpt_Qout                 : OUT std_logic_vector(C_CHANNEL_BUF_WIDTH-1 downto 0);
552 
 
553 
      trn_clk                   : IN  std_logic;
554 
      trn_reset_n               : IN  std_logic
555 
      );
556 
   END COMPONENT;
557 
 
558 
 
559 
   ------------------------------------------------------------------
560 
   --  Upstream DMA Channel
561 
   --   contains channel buffer for upstream DMA
562 
   --
563 
        COMPONENT
564 
   usDMA_Transact
565 
        PORT(
566 
 
567 
      -- command buffer
568 
      usTlp_Req                 : OUT std_logic;
569 
      usTlp_RE                  : IN  std_logic;
570 
      usTlp_Qout                : OUT std_logic_vector(C_CHANNEL_BUF_WIDTH-1 downto 0);
571 
 
572 
      FIFO_Data_Count           : IN  std_logic_vector(C_FIFO_DC_WIDTH downto 0);
573 
      FIFO_Empty                : IN  std_logic;
574 
      FIFO_Reading              : IN  std_logic;
575 
 
576 
      -- Upstream DMA Control Signals from MWr Channel
577 
      usDMA_Start               : IN  std_logic;
578 
      usDMA_Stop                : IN  std_logic;
579 
      usDMA_Channel_Rst         : IN  std_logic;
580 
      us_FC_stop                : IN  std_logic;
581 
      us_Last_sof               : IN  std_logic;
582 
      us_Last_eof               : IN  std_logic;
583 
 
584 
      --- Upstream registers from CplD channel
585 
      DMA_us_PA                 : IN  std_logic_vector(C_DBUS_WIDTH-1 downto 0);
586 
      DMA_us_HA                 : IN  std_logic_vector(C_DBUS_WIDTH-1 downto 0);
587 
      DMA_us_BDA                : IN  std_logic_vector(C_DBUS_WIDTH-1 downto 0);
588 
      DMA_us_Length             : IN  std_logic_vector(C_DBUS_WIDTH-1 downto 0);
589 
      DMA_us_Control            : IN  std_logic_vector(C_DBUS_WIDTH-1 downto 0);
590 
      usDMA_BDA_eq_Null         : IN  std_logic;
591 
      us_MWr_Param_Vec          : IN  std_logic_vector(6-1   downto 0);
592 
 
593 
      -- Calculation in advance, for better timing
594 
      usHA_is_64b               : IN  std_logic;
595 
      usBDA_is_64b              : IN  std_logic;
596 
 
597 
      -- Calculation in advance, for better timing
598 
      usLeng_Hi19b_True         : IN  std_logic;
599 
      usLeng_Lo7b_True          : IN  std_logic;
600 
 
601 
      --- Upstream commands from CplD channel
602 
      usDMA_Start2              : IN  std_logic;
603 
      usDMA_Stop2               : IN  std_logic;
604 
 
605 
      -- DMA Acknowledge to the start command
606 
      DMA_Cmd_Ack               : OUT std_logic;
607 
 
608 
      --- Tag for descriptor
609 
      usDMA_dex_Tag             : IN  std_logic_vector(C_TAG_WIDTH-1 downto 0);
610 
 
611 
      -- To Interrupt module
612 
      DMA_Done                  : OUT std_logic;
613 
      DMA_TimeOut               : OUT std_logic;
614 
      DMA_Busy                  : OUT std_logic;
615 
 
616 
      -- To Tx channel
617 
      DMA_us_Status             : OUT std_logic_vector(C_DBUS_WIDTH-1 downto 0);
618 
 
619 
      -- Additional
620 
      cfg_dcommand              : IN  std_logic_vector(C_CFG_COMMAND_DWIDTH-1 downto 0);
621 
 
622 
      -- common
623 
                trn_clk                   : IN  std_logic;
624 
                trn_reset_n               : IN  std_logic
625 
                );
626 
        END COMPONENT;
627 
 
628 
 
629 
   ------------------------------------------------------------------
630 
   --  Downstream DMA Channel
631 
   --   contains channel buffer for downstream DMA
632 
   --
633 
        COMPONENT
634 
   dsDMA_Transact
635 
        PORT(
636 
      -- command buffer
637 
                MRd_dsp_RE                : IN std_logic;
638 
                MRd_dsp_Req               : OUT std_logic;
639 
                MRd_dsp_Qout              : OUT std_logic_vector(C_CHANNEL_BUF_WIDTH-1 downto 0);
640 
 
641 
      -- Downstream tRAM port A write request, to CplD channel
642 
      tRAM_weB                  : OUT std_logic;
643 
      tRAM_addrB                : OUT std_logic_vector(C_TAGRAM_AWIDTH-1 downto 0);
644 
      tRAM_dinB                 : OUT std_logic_vector(C_TAGRAM_DWIDTH-1 downto 0);
645 
 
646 
      -- Downstream Registers from MWr Channel
647 
      DMA_ds_PA                 : IN  std_logic_vector(C_DBUS_WIDTH-1 downto 0);
648 
      DMA_ds_HA                 : IN  std_logic_vector(C_DBUS_WIDTH-1 downto 0);
649 
      DMA_ds_BDA                : IN  std_logic_vector(C_DBUS_WIDTH-1 downto 0);
650 
      DMA_ds_Length             : IN  std_logic_vector(C_DBUS_WIDTH-1 downto 0);
651 
      DMA_ds_Control            : IN  std_logic_vector(C_DBUS_WIDTH-1 downto 0);
652 
      dsDMA_BDA_eq_Null         : IN  std_logic;
653 
 
654 
      -- Calculation in advance, for better timing
655 
      dsHA_is_64b               : IN  std_logic;
656 
      dsBDA_is_64b              : IN  std_logic;
657 
 
658 
      -- Calculation in advance, for better timing
659 
      dsLeng_Hi19b_True         : IN  std_logic;
660 
      dsLeng_Lo7b_True          : IN  std_logic;
661 
 
662 
      -- Downstream Control Signals from MWr Channel
663 
      dsDMA_Start               : IN  std_logic;
664 
      dsDMA_Stop                : IN  std_logic;
665 
 
666 
      -- DMA Acknowledge to the start command
667 
      DMA_Cmd_Ack               : OUT std_logic;
668 
 
669 
      dsDMA_Channel_Rst         : IN  std_logic;
670 
 
671 
      -- Downstream Control Signals from CplD Channel, out of consecutive dex
672 
      dsDMA_Start2              : IN  std_logic;
673 
      dsDMA_Stop2               : IN  std_logic;
674 
 
675 
      -- Downstream Handshake Signals with CplD Channel for Busy/Done
676 
      Tag_Map_Clear             : IN  std_logic_vector(C_TAG_MAP_WIDTH-1 downto 0);
677 
      FC_pop                    : IN  std_logic;
678 
 
679 
 
680 
      -- Tag for descriptor
681 
      dsDMA_dex_Tag             : IN  std_logic_vector(C_TAG_WIDTH-1 downto 0);
682 
 
683 
      -- To Interrupt module
684 
      DMA_Done                  : OUT std_logic;
685 
      DMA_TimeOut               : OUT std_logic;
686 
      DMA_Busy                  : OUT std_logic;
687 
 
688 
      -- To Cpl/D channel
689 
      DMA_ds_Status             : OUT std_logic_vector(C_DBUS_WIDTH-1 downto 0);
690 
 
691 
      -- Additional
692 
      cfg_dcommand              : IN  std_logic_vector(C_CFG_COMMAND_DWIDTH-1 downto 0);
693 
 
694 
      -- common
695 
                trn_clk                   : IN  std_logic;
696 
                trn_reset_n               : IN  std_logic
697 
                );
698 
        END COMPONENT;
699 
 
700 
   -- tag RAM port A write request
701 
   signal  tRAM_weB             : std_logic;
702 
   signal  tRAM_addrB           : std_logic_vector(C_TAGRAM_AWIDTH-1 downto 0);
703 
   signal  tRAM_dinB            : std_logic_vector(C_TAGRAM_DWIDTH-1 downto 0);
704 
 
705 
 
706 
begin
707 
 
708 
   eb_FIFO_we       <= eb_FIFO_we_i     ;
709 
   eb_FIFO_wsof     <= eb_FIFO_wsof_i   ;
710 
   eb_FIFO_weof     <= eb_FIFO_weof_i   ;
711 
   eb_FIFO_din      <= eb_FIFO_din_i    ;
712 
 
713 
 
714 
   eb_FIFO_we_i     <= eb_FIFO_we_MWr or eb_FIFO_we_CplD;
715 
   eb_FIFO_wsof_i   <= eb_FIFO_wsof_CplD when eb_FIFO_we_CplD='1' else eb_FIFO_wsof_MWr;
716 
   eb_FIFO_weof_i   <= eb_FIFO_weof_CplD when eb_FIFO_we_CplD='1' else eb_FIFO_weof_MWr;
717 
   eb_FIFO_din_i    <= eb_FIFO_din_CplD  when eb_FIFO_we_CplD='1' else eb_FIFO_din_MWr;
718 
 
719 
   -- ------------------------------------------------
720 
   -- Delay of Rx inputs
721 
   -- ------------------------------------------------
722 
    Rx_Input_Delays:
723 
    RxIn_Delay
724 
    PORT MAP(
725 
      -- Common ports
726 
      trn_clk             =>  trn_clk           ,        -- IN  std_logic;
727 
      trn_reset_n         =>  trn_reset_n       ,        -- IN  std_logic;
728 
      trn_lnk_up_n        =>  trn_lnk_up_n      ,        -- IN  std_logic;
729 
 
730 
      -- Transaction receive interface
731 
      trn_rsof_n          =>  trn_rsof_n        ,        -- IN  std_logic;
732 
      trn_reof_n          =>  trn_reof_n        ,        -- IN  std_logic;
733 
      trn_rd              =>  trn_rd            ,        -- IN  std_logic_vector(C_DBUS_WIDTH-1 downto 0);
734 
      trn_rrem_n          =>  trn_rrem_n        ,        -- IN  std_logic_vector(C_DBUS_WIDTH/8-1 downto 0);
735 
      trn_rerrfwd_n       =>  trn_rerrfwd_n     ,        -- IN  std_logic;
736 
      trn_rsrc_rdy_n      =>  trn_rsrc_rdy_n    ,        -- IN  std_logic;
737 
      trn_rsrc_dsc_n      =>  trn_rsrc_dsc_n    ,        -- IN  std_logic;
738 
      trn_rbar_hit_n      =>  trn_rbar_hit_n    ,        -- IN  std_logic_vector(C_BAR_NUMBER-1 downto 0);
739 
      trn_rdst_rdy_n      =>  trn_rdst_rdy_n    ,        -- OUT std_logic;
740 
      Pool_wrBuf_full     =>  DDR_wr_full       ,        -- IN  std_logic;
741 
      Link_Buf_full       =>  Link_Buf_full     ,        -- IN  std_logic;
742 
 
743 
      -- Delayed
744 
      trn_rsof_n_dly      =>  trn_rsof_n_dly    ,        -- OUT std_logic;
745 
      trn_reof_n_dly      =>  trn_reof_n_dly    ,        -- OUT std_logic;
746 
      trn_rd_dly          =>  trn_rd_dly        ,        -- OUT std_logic_vector(C_DBUS_WIDTH-1 downto 0);
747 
      trn_rrem_n_dly      =>  trn_rrem_n_dly    ,        -- OUT std_logic_vector(C_DBUS_WIDTH/8-1 downto 0);
748 
      trn_rerrfwd_n_dly   =>  trn_rerrfwd_n_dly ,        -- OUT std_logic;
749 
      trn_rsrc_rdy_n_dly  =>  trn_rsrc_rdy_n_dly,        -- OUT std_logic;
750 
      trn_rdst_rdy_n_dly  =>  trn_rdst_rdy_n_dly,        -- OUT std_logic;
751 
      trn_rsrc_dsc_n_dly  =>  trn_rsrc_dsc_n_dly,        -- OUT std_logic;
752 
      trn_rbar_hit_n_dly  =>  trn_rbar_hit_n_dly,        -- OUT std_logic_vector(C_BAR_NUMBER-1 downto 0);
753 
 
754 
      -- TLP resolution
755 
      IORd_Type           =>  IORd_Type         ,        -- OUT std_logic;
756 
      IOWr_Type           =>  IOWr_Type         ,        -- OUT std_logic;
757 
      MRd_Type            =>  MRd_Type          ,        -- OUT std_logic_vector(3 downto 0);
758 
      MWr_Type            =>  MWr_Type          ,        -- OUT std_logic_vector(1 downto 0);
759 
      CplD_Type           =>  CplD_Type         ,        -- OUT std_logic_vector(3 downto 0);
760 
 
761 
      -- From Cpl/D channel
762 
      usDMA_dex_Tag       =>  usDMA_dex_Tag     ,        -- IN  std_logic_vector(7 downto 0);
763 
      dsDMA_dex_Tag       =>  dsDMA_dex_Tag     ,        -- IN  std_logic_vector(7 downto 0);
764 
 
765 
      -- To Memory request process modules
766 
      Tlp_straddles_4KB   =>  Tlp_straddles_4KB ,        -- OUT std_logic;
767 
 
768 
      -- To Cpl/D channel
769 
      Tlp_has_4KB         =>  Tlp_has_4KB       ,        -- OUT std_logic;
770 
      Tlp_has_1DW         =>  Tlp_has_1DW       ,        -- OUT std_logic;
771 
      CplD_is_the_Last    =>  CplD_is_the_Last  ,        -- OUT std_logic;
772 
      CplD_on_Pool        =>  CplD_on_Pool      ,        -- OUT std_logic;
773 
      CplD_on_EB          =>  CplD_on_EB        ,        -- OUT std_logic;
774 
      Req_ID_Match        =>  Req_ID_Match      ,        -- OUT std_logic;
775 
      usDex_Tag_Matched   =>  usDex_Tag_Matched ,        -- OUT std_logic;
776 
      dsDex_Tag_Matched   =>  dsDex_Tag_Matched ,        -- OUT std_logic;
777 
      CplD_Tag            =>  CplD_Tag          ,        -- OUT std_logic_vector(7 downto  0);
778 
 
779 
      -- Additional
780 
      cfg_dcommand        =>  cfg_dcommand      ,        -- IN  std_logic_vector(16-1 downto 0)
781 
      localID             =>  localID                    -- IN  std_logic_vector(15 downto 0)
782 
    );
783 
 
784 
 
785 
  -- ------------------------------------------------
786 
  -- Processing MRd Requests
787 
  -- ------------------------------------------------
788 
   MRd_Channel:
789 
   rx_MRd_Transact
790 
   PORT MAP(
791 
      --
792 
      trn_rsof_n          =>  trn_rsof_n_dly,            -- IN  std_logic;
793 
      trn_reof_n          =>  trn_reof_n_dly,            -- IN  std_logic;
794 
      trn_rd              =>  trn_rd_dly,                -- IN  std_logic_vector(31 downto 0);
795 
      trn_rrem_n          =>  trn_rrem_n_dly,            -- IN  std_logic_vector(C_DBUS_WIDTH/8-1 downto 0);
796 
      trn_rerrfwd_n       =>  trn_rerrfwd_n_dly,         -- IN  std_logic;
797 
      trn_rsrc_rdy_n      =>  trn_rsrc_rdy_n_dly,        -- IN  std_logic;
798 
      trn_rsrc_dsc_n      =>  trn_rsrc_dsc_n_dly,        -- IN  std_logic;
799 
      trn_rbar_hit_n      =>  trn_rbar_hit_n_dly,        -- IN  std_logic_vector(6 downto 0);
800 
--      trn_rdst_rdy_n      =>  open,  -- trn_rdst_rdy_n_MRd,            -- OUT std_logic;
801 
                trn_rnp_ok_n        =>  trn_rnp_ok_n,              -- OUT std_logic;
802 
 
803 
      IORd_Type           =>  IORd_Type         ,        -- IN  std_logic;
804 
      MRd_Type            =>  MRd_Type          ,        -- IN  std_logic_vector(3 downto 0);
805 
      Tlp_straddles_4KB   =>  Tlp_straddles_4KB ,        -- IN  std_logic;
806 
 
807 
      pioCplD_RE          =>  pioCplD_RE,                -- IN  std_logic;
808 
      pioCplD_Req         =>  pioCplD_Req,               -- OUT std_logic;
809 
      pioCplD_Qout        =>  pioCplD_Qout,              -- OUT std_logic_vector(127 downto 0);
810 
      pio_FC_stop         =>  pio_FC_stop,               -- IN  std_logic;
811 
 
812 
      FIFO_Empty          =>  eb_FIFO_Empty,                -- IN  std_logic;
813 
      FIFO_Reading        =>  eb_FIFO_Reading,              -- IN  std_logic;
814 
      pio_reading_status  =>  pio_reading_status,           -- OUT std_logic;
815 
 
816 
      Channel_Rst         =>  MRd_Channel_Rst,           -- IN  std_logic;
817 
 
818 
      trn_clk             =>  trn_clk,                   -- IN  std_logic;
819 
      trn_reset_n         =>  trn_reset_n,               -- IN  std_logic;
820 
      trn_lnk_up_n        =>  trn_lnk_up_n               -- IN  std_logic;
821 
        );
822 
 
823 
 
824 
  -- ------------------------------------------------
825 
  -- Processing MWr Requests
826 
  -- ------------------------------------------------
827 
   MWr_Channel:
828 
   rx_MWr_Transact
829 
   PORT MAP(
830 
      --
831 
      trn_rsof_n          =>  trn_rsof_n_dly,            -- IN  std_logic;
832 
      trn_reof_n          =>  trn_reof_n_dly,            -- IN  std_logic;
833 
      trn_rd              =>  trn_rd_dly,                -- IN  std_logic_vector(31 downto 0);
834 
      trn_rrem_n          =>  trn_rrem_n_dly,            -- IN  std_logic_vector(C_DBUS_WIDTH/8-1 downto 0);
835 
      trn_rerrfwd_n       =>  trn_rerrfwd_n_dly ,        -- IN  std_logic;
836 
      trn_rsrc_rdy_n      =>  trn_rsrc_rdy_n_dly,        -- IN  std_logic;
837 
      trn_rdst_rdy_n      =>  trn_rdst_rdy_n_dly,        -- IN  std_logic;
838 
      trn_rsrc_dsc_n      =>  trn_rsrc_dsc_n_dly,        -- IN  std_logic;
839 
      trn_rbar_hit_n      =>  trn_rbar_hit_n_dly,        -- IN  std_logic_vector(6 downto 0);
840 
 
841 
      IOWr_Type           =>  IOWr_Type         ,        -- OUT std_logic;
842 
      MWr_Type            =>  MWr_Type          ,        -- IN  std_logic_vector(1 downto 0);
843 
      Tlp_straddles_4KB   =>  Tlp_straddles_4KB ,        -- IN  std_logic;
844 
      Tlp_has_4KB         =>  Tlp_has_4KB       ,        -- IN  std_logic;
845 
 
846 
 
847 
      -- Event Buffer write port
848 
      eb_FIFO_we          =>  eb_FIFO_we_MWr    ,        -- OUT std_logic;
849 
      eb_FIFO_wsof        =>  eb_FIFO_wsof_MWr  ,        -- OUT std_logic;
850 
      eb_FIFO_weof        =>  eb_FIFO_weof_MWr  ,        -- OUT std_logic;
851 
      eb_FIFO_din         =>  eb_FIFO_din_MWr   ,        -- OUT std_logic_vector(C_DBUS_WIDTH-1 downto 0);
852 
 
853 
      -- To registers module
854 
      Regs_WrEn           =>  Regs_WrEn0     ,           -- OUT std_logic;
855 
      Regs_WrMask         =>  Regs_WrMask0   ,           -- OUT std_logic_vector(2-1 downto 0);
856 
      Regs_WrAddr         =>  Regs_WrAddr0   ,           -- OUT std_logic_vector(16-1 downto 0);
857 
      Regs_WrDin          =>  Regs_WrDin0    ,           -- OUT std_logic_vector(32-1 downto 0);
858 
 
859 
      -- DDR write port
860 
      DDR_wr_sof          =>  DDR_wr_sof_A   ,  --        OUT   std_logic;
861 
      DDR_wr_eof          =>  DDR_wr_eof_A   ,  --        OUT   std_logic;
862 
      DDR_wr_v            =>  DDR_wr_v_A     ,  --        OUT   std_logic;
863 
      DDR_wr_FA           =>  DDR_wr_FA_A    ,  --        OUT   std_logic;
864 
      DDR_wr_Shift        =>  DDR_wr_Shift_A ,  --        OUT   std_logic;
865 
      DDR_wr_din          =>  DDR_wr_din_A   ,  --        OUT   std_logic_vector(C_DBUS_WIDTH-1 downto 0);
866 
      DDR_wr_Mask         =>  DDR_wr_Mask_A  ,  --        OUT   std_logic_vector(2-1 downto 0);
867 
      DDR_wr_full         =>  DDR_wr_full    ,  --        IN    std_logic;
868 
 
869 
      -- Data generator table write
870 
      tab_we              =>  tab_we ,  -- OUT std_logic_vector(2-1 downto 0);
871 
      tab_wa              =>  tab_wa ,  -- OUT std_logic_vector(12-1 downto 0);
872 
      tab_wd              =>  tab_wd ,  -- OUT std_logic_vector(C_DBUS_WIDTH-1 downto 0);
873 
 
874 
      -- Common
875 
      trn_clk             =>  trn_clk        ,  --        IN  std_logic;
876 
      trn_reset_n         =>  trn_reset_n    ,  --        IN  std_logic;
877 
      trn_lnk_up_n        =>  trn_lnk_up_n      --        IN  std_logic;
878 
        );
879 
 
880 
 
881 
  -- ---------------------------------------------------
882 
  -- Processing Completions
883 
  -- ---------------------------------------------------
884 
   CplD_Channel:
885 
   rx_CplD_Transact
886 
   PORT MAP(
887 
      --
888 
      trn_rsof_n          =>  trn_rsof_n_dly,            -- IN  std_logic;
889 
      trn_reof_n          =>  trn_reof_n_dly,            -- IN  std_logic;
890 
      trn_rd              =>  trn_rd_dly,                -- IN  std_logic_vector(31 downto 0);
891 
      trn_rrem_n          =>  trn_rrem_n_dly,            -- IN  std_logic_vector(C_DBUS_WIDTH/8-1 downto 0);
892 
      trn_rerrfwd_n       =>  trn_rerrfwd_n_dly,         -- IN  std_logic;
893 
      trn_rsrc_rdy_n      =>  trn_rsrc_rdy_n_dly,        -- IN  std_logic;
894 
      trn_rdst_rdy_n      =>  trn_rdst_rdy_n_dly,        -- IN  std_logic;
895 
      trn_rsrc_dsc_n      =>  trn_rsrc_dsc_n_dly,        -- IN  std_logic;
896 
      trn_rbar_hit_n      =>  trn_rbar_hit_n_dly,        -- IN  std_logic_vector(6 downto 0);
897 
 
898 
      CplD_Type           =>  CplD_Type,                 -- IN  std_logic_vector(3 downto 0);
899 
 
900 
      Req_ID_Match        =>  Req_ID_Match,              -- IN  std_logic;
901 
      usDex_Tag_Matched   =>  usDex_Tag_Matched,         -- IN  std_logic;
902 
      dsDex_Tag_Matched   =>  dsDex_Tag_Matched,         -- IN  std_logic;
903 
 
904 
      Tlp_has_4KB         =>  Tlp_has_4KB     ,          -- IN  std_logic;
905 
      Tlp_has_1DW         =>  Tlp_has_1DW     ,          -- IN  std_logic;
906 
      CplD_is_the_Last    =>  CplD_is_the_Last,          -- IN  std_logic;
907 
      CplD_on_Pool        =>  CplD_on_Pool    ,          -- IN  std_logic;
908 
      CplD_on_EB          =>  CplD_on_EB      ,          -- IN  std_logic;
909 
      CplD_Tag            =>  CplD_Tag,                  -- IN  std_logic_vector( 7 downto  0);
910 
      FC_pop              =>  FC_pop,                    -- OUT std_logic;
911 
 
912 
 
913 
      -- Downstream DMA transferred bytes count up
914 
      ds_DMA_Bytes_Add    =>  ds_DMA_Bytes_Add,          -- OUT std_logic;
915 
      ds_DMA_Bytes        =>  ds_DMA_Bytes    ,          -- OUT std_logic_vector(C_TLP_FLD_WIDTH_OF_LENG+2 downto 0);
916 
 
917 
      -- Downstream tRAM port A write request
918 
      tRAM_weB            =>  tRAM_weB,                  -- IN  std_logic;
919 
      tRAM_addrB          =>  tRAM_addrB,                -- IN  std_logic_vector( 6 downto 0);
920 
      tRAM_dinB           =>  tRAM_dinB,                 -- IN  std_logic_vector(47 downto 0);
921 
 
922 
      -- Downstream channel descriptor tag
923 
      dsDMA_dex_Tag       =>  dsDMA_dex_Tag,             -- OUT std_logic_vector( 7 downto 0);
924 
 
925 
      -- Downstream Tag Map Signal for Busy/Done
926 
      Tag_Map_Clear       =>  Tag_Map_Clear,             -- OUT std_logic_vector(127 downto 0);
927 
 
928 
      -- Upstream channel descriptor tag
929 
      usDMA_dex_Tag       =>  usDMA_dex_Tag,             -- OUT std_logic_vector( 7 downto 0);
930 
 
931 
 
932 
      -- Event Buffer write port
933 
      eb_FIFO_we          =>  eb_FIFO_we_CplD   ,        -- OUT std_logic;
934 
      eb_FIFO_wsof        =>  eb_FIFO_wsof_CplD ,        -- OUT std_logic;
935 
      eb_FIFO_weof        =>  eb_FIFO_weof_CplD ,        -- OUT std_logic;
936 
      eb_FIFO_din         =>  eb_FIFO_din_CplD  ,        -- OUT std_logic_vector(C_DBUS_WIDTH-1 downto 0);
937 
 
938 
      -- To registers module
939 
      Regs_WrEn           =>  Regs_WrEn1,                -- OUT std_logic;
940 
      Regs_WrMask         =>  Regs_WrMask1,              -- OUT std_logic_vector(2-1 downto 0);
941 
      Regs_WrAddr         =>  Regs_WrAddr1,              -- OUT std_logic_vector(16-1 downto 0);
942 
      Regs_WrDin          =>  Regs_WrDin1,               -- OUT std_logic_vector(32-1 downto 0);
943 
 
944 
      -- DDR write port
945 
      DDR_wr_sof          =>  DDR_wr_sof_B   ,  --        OUT   std_logic;
946 
      DDR_wr_eof          =>  DDR_wr_eof_B   ,  --        OUT   std_logic;
947 
      DDR_wr_v            =>  DDR_wr_v_B     ,  --        OUT   std_logic;
948 
      DDR_wr_FA           =>  DDR_wr_FA_B    ,  --        OUT   std_logic;
949 
      DDR_wr_Shift        =>  DDR_wr_Shift_B ,  --        OUT   std_logic;
950 
      DDR_wr_Mask         =>  DDR_wr_Mask_B  ,  --        OUT   std_logic_vector(2-1 downto 0);
951 
      DDR_wr_din          =>  DDR_wr_din_B   ,  --        OUT   std_logic_vector(C_DBUS_WIDTH-1 downto 0);
952 
      DDR_wr_full         =>  DDR_wr_full    ,  --        IN    std_logic;
953 
 
954 
 
955 
      -- Common
956 
      trn_clk             =>  trn_clk,                   -- IN std_logic;
957 
      trn_reset_n         =>  trn_reset_n,               -- IN std_logic;
958 
      trn_lnk_up_n        =>  trn_lnk_up_n               -- IN std_logic;
959 
        );
960 
 
961 
 
962 
  -- ------------------------------------------------
963 
  -- Processing upstream DMA Requests
964 
  -- ------------------------------------------------
965 
   Upstream_DMA_Engine:
966 
   usDMA_Transact
967 
   PORT MAP(
968 
      -- TLP buffer
969 
      usTlp_RE            =>  usTlp_RE,                 -- IN std_logic;
970 
      usTlp_Req           =>  usTlp_Req,                -- OUT std_logic;
971 
      usTlp_Qout          =>  usTlp_Qout,               -- OUT std_logic_vector(127 downto 0)
972 
 
973 
      FIFO_Data_Count     =>  eb_FIFO_data_count,          -- IN  std_logic_vector(C_FIFO_DC_WIDTH downto 0);
974 
      FIFO_Empty          =>  eb_FIFO_Empty,               -- IN  std_logic;
975 
      FIFO_Reading        =>  eb_FIFO_Reading,             -- IN  std_logic;
976 
 
977 
      -- upstream Control Signals from MWr Channel
978 
      usDMA_Start         =>  usDMA_Start,              -- IN  std_logic;
979 
      usDMA_Stop          =>  usDMA_Stop,               -- IN  std_logic;
980 
 
981 
      -- Upstream Control Signals from CplD Channel
982 
      usDMA_Start2        =>  usDMA_Start2,             -- IN  std_logic;
983 
      usDMA_Stop2         =>  usDMA_Stop2,              -- IN  std_logic;
984 
 
985 
      DMA_Cmd_Ack         =>  usDMA_Cmd_Ack,            -- OUT std_logic;
986 
      usDMA_Channel_Rst   =>  usDMA_Channel_Rst,        -- IN  std_logic;
987 
      us_FC_stop          =>  us_FC_stop,               -- IN  std_logic;
988 
      us_Last_sof         =>  us_Last_sof,              -- IN  std_logic;
989 
      us_Last_eof         =>  us_Last_eof,              -- IN  std_logic;
990 
 
991 
      -- To Interrupt module
992 
      DMA_Done            =>  DMA_us_Done,              -- OUT std_logic;
993 
      DMA_TimeOut         =>  DMA_us_Tout,              -- OUT std_logic;
994 
      DMA_Busy            =>  DMA_us_Busy,              -- OUT std_logic;
995 
 
996 
      -- To Tx channel
997 
      DMA_us_Status       =>  DMA_us_Status,            -- OUT std_logic_vector(31 downto 0);
998 
 
999 
      -- upstream Registers
1000 
      DMA_us_PA           =>  DMA_us_PA,                -- IN  std_logic_vector(63 downto 0);
1001 
      DMA_us_HA           =>  DMA_us_HA,                -- IN  std_logic_vector(63 downto 0);
1002 
      DMA_us_BDA          =>  DMA_us_BDA,               -- IN  std_logic_vector(63 downto 0);
1003 
      DMA_us_Length       =>  DMA_us_Length,            -- IN  std_logic_vector(31 downto 0);
1004 
      DMA_us_Control      =>  DMA_us_Control,           -- IN  std_logic_vector(31 downto 0);
1005 
      usDMA_BDA_eq_Null   =>  usDMA_BDA_eq_Null,        -- IN  std_logic;
1006 
      us_MWr_Param_Vec    =>  us_MWr_Param_Vec,         -- IN  std_logic_vector(5 downto 0);
1007 
 
1008 
      -- Calculation in advance, for better timing
1009 
      usHA_is_64b         =>  usHA_is_64b          ,    -- IN  std_logic;
1010 
      usBDA_is_64b        =>  usBDA_is_64b         ,    -- IN  std_logic;
1011 
 
1012 
      usLeng_Hi19b_True   =>  usLeng_Hi19b_True    ,    --  IN  std_logic;
1013 
      usLeng_Lo7b_True    =>  usLeng_Lo7b_True     ,    --  IN  std_logic;
1014 
 
1015 
      usDMA_dex_Tag       =>  usDMA_dex_Tag        ,    -- OUT std_logic_vector( 7 downto 0);
1016 
 
1017 
      cfg_dcommand        =>  cfg_dcommand         ,    -- IN  std_logic_vector(16-1 downto 0)
1018 
 
1019 
      trn_clk             =>  trn_clk              ,    -- IN std_logic;
1020 
      trn_reset_n         =>  trn_reset_n               -- IN std_logic;
1021 
        );
1022 
 
1023 
 
1024 
  -- ------------------------------------------------
1025 
  -- Processing downstream DMA Requests
1026 
  -- ------------------------------------------------
1027 
   Downstream_DMA_Engine:
1028 
   dsDMA_Transact
1029 
   PORT MAP(
1030 
      -- Downstream tRAM port A write request
1031 
      tRAM_weB            =>  tRAM_weB,                 -- OUT std_logic;
1032 
      tRAM_addrB          =>  tRAM_addrB,               -- OUT std_logic_vector( 6 downto 0);
1033 
      tRAM_dinB           =>  tRAM_dinB,                -- OUT std_logic_vector(47 downto 0);
1034 
 
1035 
      -- TLP buffer
1036 
      MRd_dsp_RE          =>  dsMRd_RE,                 -- IN std_logic;
1037 
      MRd_dsp_Req         =>  dsMRd_Req,                -- OUT std_logic;
1038 
      MRd_dsp_Qout        =>  dsMRd_Qout,               -- OUT std_logic_vector(127 downto 0);
1039 
 
1040 
      -- Downstream Registers
1041 
      DMA_ds_PA           =>  DMA_ds_PA,                -- IN  std_logic_vector(63 downto 0);
1042 
      DMA_ds_HA           =>  DMA_ds_HA,                -- IN  std_logic_vector(63 downto 0);
1043 
      DMA_ds_BDA          =>  DMA_ds_BDA,               -- IN  std_logic_vector(63 downto 0);
1044 
      DMA_ds_Length       =>  DMA_ds_Length,            -- IN  std_logic_vector(31 downto 0);
1045 
      DMA_ds_Control      =>  DMA_ds_Control,           -- IN  std_logic_vector(31 downto 0);
1046 
      dsDMA_BDA_eq_Null   =>  dsDMA_BDA_eq_Null,        -- IN  std_logic;
1047 
 
1048 
      -- Calculation in advance, for better timing
1049 
      dsHA_is_64b         =>  dsHA_is_64b          ,    -- IN  std_logic;
1050 
      dsBDA_is_64b        =>  dsBDA_is_64b         ,    -- IN  std_logic;
1051 
 
1052 
      dsLeng_Hi19b_True   =>  dsLeng_Hi19b_True    ,    -- IN  std_logic;
1053 
      dsLeng_Lo7b_True    =>  dsLeng_Lo7b_True     ,    -- IN  std_logic;
1054 
 
1055 
      -- Downstream Control Signals from MWr Channel
1056 
      dsDMA_Start         =>  dsDMA_Start,              -- IN  std_logic;
1057 
      dsDMA_Stop          =>  dsDMA_Stop,               -- IN  std_logic;
1058 
 
1059 
      -- Downstream Control Signals from CplD Channel
1060 
      dsDMA_Start2        =>  dsDMA_Start2,             -- IN  std_logic;
1061 
      dsDMA_Stop2         =>  dsDMA_Stop2,              -- IN  std_logic;
1062 
 
1063 
      DMA_Cmd_Ack         =>  dsDMA_Cmd_Ack,            -- OUT std_logic;
1064 
      dsDMA_Channel_Rst   =>  dsDMA_Channel_Rst,        -- IN  std_logic;
1065 
 
1066 
      -- Downstream Handshake Signals with CplD Channel for Busy/Done
1067 
      Tag_Map_Clear       =>  Tag_Map_Clear,            -- IN  std_logic_vector(127 downto 0);
1068 
 
1069 
      FC_pop              =>  FC_pop,                   -- IN  std_logic;
1070 
 
1071 
      -- To Interrupt module
1072 
      DMA_Done            =>  DMA_ds_Done,              -- OUT std_logic;
1073 
      DMA_TimeOut         =>  DMA_ds_Tout,              -- OUT std_logic;
1074 
      DMA_Busy            =>  DMA_ds_Busy,              -- OUT std_logic;
1075 
 
1076 
      -- To Tx channel
1077 
      DMA_ds_Status       =>  DMA_ds_Status,            -- OUT std_logic_vector(31 downto 0);
1078 
 
1079 
      -- tag for descriptor
1080 
      dsDMA_dex_Tag       =>  dsDMA_dex_Tag,            -- IN  std_logic_vector( 7 downto 0);
1081 
 
1082 
      -- Additional
1083 
      cfg_dcommand        =>  cfg_dcommand ,            -- IN  std_logic_vector(16-1 downto 0)
1084 
 
1085 
      -- common
1086 
      trn_clk             =>  trn_clk      ,            -- IN std_logic;
1087 
      trn_reset_n         =>  trn_reset_n               -- IN std_logic;
1088 
        );
1089 
 
1090 
 
1091 
  -- ------------------------------------------------
1092 
  --   Interrupts generation
1093 
  -- ------------------------------------------------
1094 
   Intrpt_Handle:
1095 
   Interrupts
1096 
   PORT MAP(
1097 
      Sys_IRQ                 => Sys_IRQ                 ,  -- IN  std_logic_vector(31 downto 0);
1098 
 
1099 
      -- Interrupt generator signals
1100 
      IG_Reset                => IG_Reset                ,  -- IN  std_logic;
1101 
      IG_Host_Clear           => IG_Host_Clear           ,  -- IN  std_logic;
1102 
      IG_Latency              => IG_Latency              ,  -- IN  std_logic_vector(C_DBUS_WIDTH-1   downto 0);
1103 
      IG_Num_Assert           => IG_Num_Assert           ,  -- OUT std_logic_vector(C_DBUS_WIDTH-1   downto 0);
1104 
      IG_Num_Deassert         => IG_Num_Deassert         ,  -- OUT std_logic_vector(C_DBUS_WIDTH-1   downto 0);
1105 
      IG_Asserting            => IG_Asserting            ,  -- OUT std_logic;
1106 
 
1107 
      -- cfg interface
1108 
      cfg_interrupt_n         => cfg_interrupt_n         ,  -- OUT std_logic;
1109 
      cfg_interrupt_rdy_n     => cfg_interrupt_rdy_n     ,  -- IN  std_logic;
1110 
      cfg_interrupt_mmenable  => cfg_interrupt_mmenable  ,  -- IN  std_logic_vector(2 downto 0);
1111 
      cfg_interrupt_msienable => cfg_interrupt_msienable ,  -- IN  std_logic;
1112 
      cfg_interrupt_di        => cfg_interrupt_di        ,  -- OUT std_logic_vector(7 downto 0);
1113 
      cfg_interrupt_do        => cfg_interrupt_do        ,  -- IN  std_logic_vector(7 downto 0);
1114 
      cfg_interrupt_assert_n  => cfg_interrupt_assert_n  ,  -- OUT std_logic;
1115 
 
1116 
      -- Irpt Channel
1117 
      Irpt_Req                => Irpt_Req                ,  -- OUT std_logic;
1118 
      Irpt_RE                 => Irpt_RE                 ,  -- IN  std_logic;
1119 
      Irpt_Qout               => Irpt_Qout               ,  -- OUT std_logic_vector(127 downto 0);
1120 
 
1121 
      trn_clk                 => trn_clk                 ,  -- IN  std_logic;
1122 
      trn_reset_n             => trn_reset_n                -- IN  std_logic
1123 
      );
1124 
 
1125 
 
1126 
end architecture Behavioral;

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