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[/] [pcie_sg_dma/] [trunk/] [rtl/] [tx_Mem_Reader.vhd] - Blame information for rev 2

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1 2 weng_ziti 
----------------------------------------------------------------------------------
2 
-- Company:  ziti, Uni. HD
3 
-- Engineer:  wgao
4 
--
5 
-- Design Name:
6 
-- Module Name:    tx_Mem_Reader - Behavioral
7 
-- Project Name:
8 
-- Target Devices:
9 
-- Tool versions:
10 
-- Description:
11 
--
12 
-- Dependencies:
13 
--
14 
--
15 
-- Revision 1.00 - first release.  20.03.2008
16 
--
17 
-- Additional Comments:
18 
--
19 
----------------------------------------------------------------------------------
20 
 
21 
library IEEE;
22 
use IEEE.STD_LOGIC_1164.ALL;
23 
use IEEE.STD_LOGIC_ARITH.ALL;
24 
use IEEE.STD_LOGIC_UNSIGNED.ALL;
25 
 
26 
library work;
27 
use work.abb64Package.all;
28 
 
29 
-- Uncomment the following library declaration if instantiating
30 
-- any Xilinx primitives in this code.
31 
--library UNISIM;
32 
--use UNISIM.VComponents.all;
33 
 
34 
entity tx_Mem_Reader is
35 
    port (
36 
 
37 
      -- DDR Read Interface
38 
      DDR_rdc_sof        : OUT   std_logic;
39 
      DDR_rdc_eof        : OUT   std_logic;
40 
      DDR_rdc_v          : OUT   std_logic;
41 
      DDR_rdc_FA         : OUT   std_logic;
42 
      DDR_rdc_Shift      : OUT   std_logic;
43 
      DDR_rdc_din        : OUT   std_logic_vector(C_DBUS_WIDTH-1 downto 0);
44 
      DDR_rdc_full       : IN    std_logic;
45 
 
46 
      -- DDR payload FIFO Read Port
47 
      DDR_FIFO_RdEn      : OUT   std_logic;
48 
      DDR_FIFO_Empty     : IN    std_logic;
49 
      DDR_FIFO_RdQout    : IN    std_logic_vector(C_DBUS_WIDTH-1 downto 0);
50 
 
51 
 
52 
      -- Event Buffer read port
53 
      eb_FIFO_re         : OUT   std_logic;
54 
      eb_FIFO_empty      : IN    std_logic;
55 
      eb_FIFO_qout       : IN    std_logic_vector(C_DBUS_WIDTH-1 downto 0);
56 
 
57 
      -- Register Read interface
58 
      Regs_RdAddr        : OUT   std_logic_vector(C_EP_AWIDTH-1 downto 0);
59 
      Regs_RdQout        : IN    std_logic_vector(C_DBUS_WIDTH-1 downto 0);
60 
 
61 
      -- Read Command interface
62 
      RdNumber           : IN    std_logic_vector(C_TLP_FLD_WIDTH_OF_LENG-1 downto 0);
63 
      RdNumber_eq_One    : IN    std_logic;
64 
      RdNumber_eq_Two    : IN    std_logic;
65 
      StartAddr          : IN    std_logic_vector(C_DBUS_WIDTH-1 downto 0);
66 
      Shift_1st_QWord    : IN    std_logic;
67 
      FixedAddr          : IN    std_logic;
68 
      is_CplD            : IN    std_logic;
69 
      BAR_value          : IN    std_logic_vector(C_ENCODE_BAR_NUMBER-1 downto 0);
70 
      RdCmd_Req          : IN    std_logic;
71 
      RdCmd_Ack          : OUT   std_logic;
72 
 
73 
      -- Output port of the memory buffer
74 
      mbuf_Din           : OUT   std_logic_vector(C_DBUS_WIDTH*9/8-1 downto 0);
75 
      mbuf_WE            : OUT   std_logic;
76 
      mbuf_Full          : IN    std_logic;
77 
      mbuf_aFull         : IN    std_logic;
78 
      mbuf_UserFull      : IN    std_logic;   -- Test pin, intended for DDR flow interrupted
79 
 
80 
      -- Common ports
81 
      Tx_TimeOut         : OUT   std_logic;
82 
      Tx_eb_TimeOut      : OUT   std_logic;
83 
      mReader_Rst_n      : IN    std_logic;
84 
      trn_clk            : IN    std_logic
85 
    );
86 
 
87 
end tx_Mem_Reader;
88 
 
89 
 
90 
architecture Behavioral of tx_Mem_Reader is
91 
 
92 
 
93 
  type mReaderStates is           ( St_mR_Idle          -- Memory reader Idle
94 
 
95 
                                  , St_mR_CmdLatch      -- Capture the read command
96 
                                  , St_mR_Transfer      -- Acknowlege the command request
97 
 
98 
                                  , St_mR_DDR_A         -- DDR access state A
99 
--                                  , St_mR_DDR_B         -- DDR access state B
100 
                                  , St_mR_DDR_C         -- DDR access state C
101 
 
102 
                                  , St_mR_Last          -- Last word is reached
103 
                                  );
104 
 
105 
  -- State variables
106 
  signal   TxMReader_State        : mReaderStates;
107 
 
108 
 
109 
  -- DDR Read Interface
110 
  signal   DDR_rdc_sof_i          : std_logic;
111 
  signal   DDR_rdc_eof_i          : std_logic;
112 
  signal   DDR_rdc_v_i            : std_logic;
113 
  signal   DDR_rdc_Shift_i        : std_logic;
114 
  signal   DDR_rdc_din_i          : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
115 
  signal   DDR_rdc_full_i         : std_logic;
116 
 
117 
 
118 
  -- Register read address
119 
  signal   Regs_RdAddr_i          : std_logic_vector(C_EP_AWIDTH-1   downto 0);
120 
  signal   Regs_RdEn              : std_logic;
121 
  signal   Regs_Hit               : std_logic;
122 
  signal   Regs_Write_mbuf_r1     : std_logic;
123 
  signal   Regs_Write_mbuf_r2     : std_logic;
124 
  signal   Regs_Write_mbuf_r3     : std_logic;
125 
 
126 
  -- DDR FIFO read enable
127 
  signal   DDR_FIFO_RdEn_i        : std_logic;
128 
  signal   DDR_FIFO_RdEn_Mask     : std_logic;
129 
  signal   DDR_FIFO_Hit           : std_logic;
130 
  signal   DDR_FIFO_Write_mbuf_r1 : std_logic;
131 
  signal   DDR_FIFO_Write_mbuf_r2 : std_logic;
132 
  signal   DDR_FIFO_Write_mbuf_r3 : std_logic;
133 
 
134 
  -- Event Buffer
135 
  signal   eb_FIFO_Hit            : std_logic;
136 
  signal   eb_FIFO_Write_mbuf     : std_logic;
137 
  signal   eb_FIFO_Write_mbuf_r1  : std_logic;
138 
  signal   eb_FIFO_Write_mbuf_r2  : std_logic;
139 
  signal   eb_FIFO_re_i           : std_logic;
140 
  signal   eb_FIFO_RdEn_Mask_rise : std_logic;
141 
  signal   eb_FIFO_RdEn_Mask_rise_r1 : std_logic;
142 
  signal   eb_FIFO_RdEn_Mask_rise_r2 : std_logic;
143 
  signal   eb_FIFO_RdEn_Mask_rise_r3 : std_logic;
144 
  signal   eb_FIFO_RdEn_Mask      : std_logic;
145 
  signal   eb_FIFO_RdEn_Mask_r1   : std_logic;
146 
  signal   eb_FIFO_RdEn_Mask_r2   : std_logic;
147 
  signal   ebFIFO_Rd_1DW          : std_logic;
148 
  signal   eb_FIFO_qout_r1        : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
149 
  signal   eb_FIFO_qout_shift     : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
150 
  signal   eb_FIFO_qout_swapped   : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
151 
 
152 
  -- Memory data outputs
153 
  signal   eb_FIFO_Dout_wire      : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
154 
  signal   DDR_Dout_wire          : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
155 
  signal   Regs_RdQout_wire       : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
156 
  signal   mbuf_Din_wire_OR       : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
157 
 
158 
  -- Output port of the memory buffer
159 
  signal   mbuf_Din_i             : std_logic_vector(C_DBUS_WIDTH*9/8-1 downto 0);
160 
  signal   mbuf_WE_i              : std_logic;
161 
  signal   mbuf_Full_i            : std_logic;
162 
  signal   mbuf_aFull_i           : std_logic;
163 
  signal   mbuf_UserFull_i        : std_logic;
164 
  signal   mbuf_aFull_r1          : std_logic;
165 
 
166 
 
167 
  -- Read command request and acknowledge
168 
  signal   RdCmd_Req_i            : std_logic;
169 
  signal   RdCmd_Ack_i            : std_logic;
170 
 
171 
  signal   Shift_1st_QWord_k      : std_logic;
172 
  signal   is_CplD_k              : std_logic;
173 
  signal   may_be_MWr_k           : std_logic;
174 
  signal   TRem_n_last_QWord      : std_logic;
175 
 
176 
  signal   regs_Rd_Counter        : std_logic_vector(C_TLP_FLD_WIDTH_OF_LENG-1   downto 0);
177 
  signal   regs_Rd_Cntr_eq_One    : std_logic;
178 
  signal   regs_Rd_Cntr_eq_Two    : std_logic;
179 
  signal   DDR_Rd_Counter         : std_logic_vector(C_TLP_FLD_WIDTH_OF_LENG-1   downto 0);
180 
  signal   DDR_Rd_Cntr_eq_One     : std_logic;
181 
 
182 
  signal   ebFIFO_Rd_Counter      : std_logic_vector(C_TLP_FLD_WIDTH_OF_LENG-1   downto 0);
183 
  signal   ebFIFO_Rd_Cntr_eq_Two  : std_logic;
184 
 
185 
  signal   Address_var            : std_logic_vector(C_DBUS_WIDTH-1   downto 0);
186 
  signal   Address_step           : std_logic_vector(4-1   downto 0);
187 
  signal   TxTLP_eof_n            : std_logic;
188 
 
189 
  signal   TxTLP_eof_n_r1         : std_logic;
190 
--  signal   TxTLP_eof_n_r2         : std_logic;
191 
 
192 
  signal   TimeOut_Counter        : std_logic_vector(C_DBUS_WIDTH-1   downto 0);
193 
  signal   TimeOut_Indic_TX       : std_logic;
194 
  signal   TimeOut_Indic_eb_CplD  : std_logic;
195 
  signal   TimeOut_Indic_eb_MWr   : std_logic;
196 
  signal   TO_Cnt_Rst             : std_logic;
197 
  signal   Tx_TimeOut_i           : std_logic;
198 
  signal   Tx_eb_TimeOut_i        : std_logic;
199 
 
200 
 
201 
begin
202 
 
203 
   -- read command REQ + ACK
204 
   RdCmd_Req_i           <= RdCmd_Req;
205 
   RdCmd_Ack             <= RdCmd_Ack_i;
206 
 
207 
   -- Time out signal out
208 
   Tx_TimeOut            <= Tx_TimeOut_i;
209 
   Tx_eb_TimeOut         <= Tx_eb_TimeOut_i;
210 
 
211 
------------------------------------------------------------
212 
---             Memory read control
213 
------------------------------------------------------------
214 
 
215 
   -- Event Buffer read
216 
   eb_FIFO_re            <= eb_FIFO_re_i   ;
217 
 
218 
   -- DDR FIFO Read
219 
   DDR_rdc_sof           <= DDR_rdc_sof_i  ;
220 
   DDR_rdc_eof           <= DDR_rdc_eof_i  ;
221 
   DDR_rdc_v             <= DDR_rdc_v_i    ;
222 
   DDR_rdc_FA            <= '0'            ;  -- DDR_rdc_FA_i   ;
223 
   DDR_rdc_Shift         <= DDR_rdc_Shift_i;
224 
   DDR_rdc_din           <= DDR_rdc_din_i  ;
225 
   DDR_rdc_full_i        <= DDR_rdc_full   ;
226 
 
227 
   DDR_FIFO_RdEn         <= DDR_FIFO_RdEn_i;
228 
 
229 
 
230 
   -- Register address for read
231 
   Regs_RdAddr           <= Regs_RdAddr_i;
232 
 
233 
   -- Memory buffer write port
234 
   mbuf_Din              <= mbuf_Din_i;
235 
   mbuf_WE               <= mbuf_WE_i;
236 
   mbuf_Full_i           <= mbuf_Full;
237 
   mbuf_aFull_i          <= mbuf_aFull;
238 
   mbuf_UserFull_i       <= mbuf_UserFull;
239 
 
240 
 
241 
   --
242 
   Regs_RdAddr_i         <=  Address_var(C_EP_AWIDTH-1   downto 0);
243 
 
244 
-----------------------------------------------------
245 
-- Synchronous Delay: mbuf_aFull
246 
--
247 
   Synchron_Delay_mbuf_aFull:
248 
   process ( trn_clk )
249 
   begin
250 
     if trn_clk'event and trn_clk = '1' then
251 
         mbuf_aFull_r1      <= mbuf_aFull_i or mbuf_Full_i
252 
                            or mbuf_UserFull_i;
253 
      end if;
254 
   end process;
255 
 
256 
 
257 
-- ---------------------------------------------------
258 
-- State Machine: Tx Memory read control
259 
--
260 
   mR_FSM_Control:
261 
   process ( trn_clk, mReader_Rst_n)
262 
   begin
263 
      if mReader_Rst_n = '0' then
264 
         DDR_rdc_sof_i        <= '0';
265 
         DDR_rdc_eof_i        <= '0';
266 
         DDR_rdc_v_i          <= '0';
267 
         DDR_rdc_Shift_i      <= '0';
268 
         DDR_rdc_din_i        <= (OTHERS=>'0');
269 
 
270 
         eb_FIFO_Hit          <= '0';
271 
         eb_FIFO_re_i         <= '0';
272 
         eb_FIFO_RdEn_Mask    <= '0';
273 
 
274 
         DDR_FIFO_Hit         <= '0';
275 
         DDR_FIFO_RdEn_i      <= '0';
276 
         DDR_FIFO_RdEn_Mask   <= '0';
277 
         Regs_Hit             <= '0';
278 
         Regs_RdEn            <= '0';
279 
         regs_Rd_Counter      <= (Others=>'0');
280 
         DDR_Rd_Counter       <= (Others=>'0');
281 
         DDR_Rd_Cntr_eq_One   <= '0';
282 
 
283 
         ebFIFO_Rd_Counter    <= (Others=>'0');
284 
         ebFIFO_Rd_Cntr_eq_Two<= '0';
285 
 
286 
         regs_Rd_Cntr_eq_One  <= '0';
287 
         regs_Rd_Cntr_eq_Two  <= '0';
288 
 
289 
         Shift_1st_QWord_k    <= '0';
290 
         is_CplD_k            <= '0';
291 
         may_be_MWr_k         <= '0';
292 
         TRem_n_last_QWord    <= '0';
293 
 
294 
         Address_var          <= (Others=>'1');
295 
         TxTLP_eof_n          <= '1';
296 
 
297 
         TO_Cnt_Rst           <= '0';
298 
 
299 
         RdCmd_Ack_i          <= '0';
300 
         TxMReader_State      <= St_mR_Idle;
301 
 
302 
      elsif trn_clk'event and trn_clk = '1' then
303 
 
304 
         case TxMReader_State is
305 
 
306 
            when St_mR_Idle    =>
307 
              if RdCmd_Req_i='0' then
308 
                TxMReader_State      <= St_mR_Idle;
309 
                eb_FIFO_Hit          <= '0';
310 
                Regs_Hit             <= '0';
311 
                Regs_RdEn            <= '0';
312 
                TxTLP_eof_n          <= '1';
313 
                Address_var          <= (Others=>'1');
314 
                RdCmd_Ack_i          <= '0';
315 
                is_CplD_k            <= '0';
316 
                may_be_MWr_k         <= '0';
317 
              else
318 
                RdCmd_Ack_i          <= '1';
319 
                Shift_1st_QWord_k    <= Shift_1st_QWord;
320 
                TRem_n_last_QWord    <= Shift_1st_QWord xor RdNumber(0);
321 
                is_CplD_k            <= is_CplD;
322 
                may_be_MWr_k         <= not is_CplD;
323 
                TxTLP_eof_n          <= '1';
324 
                if BAR_value(C_ENCODE_BAR_NUMBER-2 downto 0)
325 
                   = CONV_STD_LOGIC_VECTOR(CINT_DDR_SPACE_BAR, C_ENCODE_BAR_NUMBER-1)
326 
                   then
327 
                   eb_FIFO_Hit      <= '0';
328 
                   DDR_FIFO_Hit     <= '1';
329 
                   Regs_Hit         <= '0';
330 
                   Regs_RdEn        <= '0';
331 
                   Address_var      <= Address_var;
332 
                   TxMReader_State  <= St_mR_DDR_A;
333 
                elsif BAR_value(C_ENCODE_BAR_NUMBER-2 downto 0)
334 
                      = CONV_STD_LOGIC_VECTOR(CINT_REGS_SPACE_BAR, C_ENCODE_BAR_NUMBER-1)
335 
                   then
336 
                   eb_FIFO_Hit      <= '0';
337 
                   DDR_FIFO_Hit     <= '0';
338 
                   Regs_Hit         <= '1';
339 
                   Regs_RdEn        <= '1';
340 
                   if Shift_1st_QWord='1' then
341 
                     Address_var(C_EP_AWIDTH-1 downto 0)  <= StartAddr(C_EP_AWIDTH-1 downto 0) - "100";
342 
                   else
343 
                     Address_var(C_EP_AWIDTH-1 downto 0)  <= StartAddr(C_EP_AWIDTH-1 downto 0);
344 
                   end if;
345 
                   TxMReader_State  <= St_mR_CmdLatch;
346 
                elsif BAR_value(C_ENCODE_BAR_NUMBER-2 downto 0)
347 
                      = CONV_STD_LOGIC_VECTOR(CINT_FIFO_SPACE_BAR, C_ENCODE_BAR_NUMBER-1)
348 
                   then
349 
                   eb_FIFO_Hit      <= '1';
350 
                   DDR_FIFO_Hit     <= '0';
351 
                   Regs_Hit         <= '0';
352 
                   Regs_RdEn        <= '0';
353 
                   Address_var      <= Address_var;
354 
                   TxMReader_State  <= St_mR_DDR_C;
355 
                else
356 
                   eb_FIFO_Hit      <= '0';
357 
                   DDR_FIFO_Hit     <= '0';
358 
                   Regs_Hit         <= '0';
359 
                   Regs_RdEn        <= '0';
360 
                   Address_var      <= Address_var;
361 
                   TxMReader_State  <= St_mR_CmdLatch;
362 
                end if;
363 
 
364 
              end if;
365 
 
366 
 
367 
            when St_mR_DDR_A    =>
368 
               DDR_rdc_sof_i        <= '1';
369 
               DDR_rdc_eof_i        <= '0';
370 
               DDR_rdc_v_i          <= '1';
371 
               DDR_rdc_Shift_i      <= Shift_1st_QWord_k;
372 
               DDR_rdc_din_i        <= C_ALL_ZEROS(C_DBUS_WIDTH-1 downto C_TLP_FLD_WIDTH_OF_LENG+2+32)
373 
                                     & RdNumber & "00"
374 
                                     & StartAddr(C_DBUS_WIDTH-1-32 downto 0);
375 
               Regs_RdEn            <= '0';
376 
               DDR_FIFO_RdEn_i      <= '0';
377 
               TxTLP_eof_n          <= '1';
378 
               RdCmd_Ack_i          <= '1';
379 
               TxMReader_State      <= St_mR_DDR_C;  -- St_mR_DDR_B;
380 
 
381 
 
382 
            when St_mR_DDR_C    =>
383 
               DDR_rdc_sof_i        <= '0';
384 
               DDR_rdc_eof_i        <= '0';
385 
               DDR_rdc_v_i          <= '0';
386 
               DDR_rdc_din_i        <= DDR_rdc_din_i;
387 
               RdCmd_Ack_i          <= '0';
388 
               TxTLP_eof_n          <= '1';
389 
--               if DDR_FIFO_Hit='1' and DDR_FIFO_Empty='1' then
390 
               if DDR_FIFO_Hit='1' and DDR_FIFO_Empty='1' and Tx_TimeOut_i='0' then
391 
                  TxMReader_State      <= St_mR_DDR_C;
392 
--               elsif eb_FIFO_Hit='1' and eb_FIFO_empty='1' then
393 
               elsif eb_FIFO_Hit='1' and eb_FIFO_empty='1' and Tx_eb_TimeOut_i='0' then
394 
                  TxMReader_State      <= St_mR_DDR_C;
395 
               else
396 
                  TxMReader_State      <= St_mR_CmdLatch;
397 
               end if;
398 
 
399 
 
400 
            when St_mR_CmdLatch    =>
401 
                  RdCmd_Ack_i          <= '0';
402 
                  if regs_Rd_Cntr_eq_One = '1' then
403 
                     Regs_RdEn            <= '0';
404 
                     Address_var          <= Address_var;
405 
                     TxTLP_eof_n          <= '0';
406 
                     TxMReader_State      <= St_mR_Last;
407 
                  elsif regs_Rd_Cntr_eq_Two = '1' then
408 
                     if Shift_1st_QWord_k='1' then
409 
                       TxMReader_State      <= St_mR_Transfer;
410 
                       Regs_RdEn            <= Regs_RdEn;  -- '1';
411 
                       TxTLP_eof_n          <= '1';
412 
                       Address_var(C_EP_AWIDTH-1 downto 0)  <= Address_var(C_EP_AWIDTH-1 downto 0) + "1000";
413 
                     else
414 
                       TxMReader_State      <= St_mR_Last;
415 
                       Regs_RdEn            <= '0';
416 
                       TxTLP_eof_n          <= '0';
417 
                       Address_var(C_EP_AWIDTH-1 downto 0)  <= Address_var(C_EP_AWIDTH-1 downto 0) + "1000";
418 
                     end if;
419 
                  else
420 
                     Regs_RdEn            <= Regs_RdEn;
421 
                     Address_var(C_EP_AWIDTH-1 downto 0)  <= Address_var(C_EP_AWIDTH-1 downto 0) + "1000";
422 
                     TxTLP_eof_n          <= '1';
423 
                     TxMReader_State      <= St_mR_Transfer;
424 
                  end if;
425 
 
426 
 
427 
            when St_mR_Transfer    =>
428 
                  RdCmd_Ack_i          <= '0';
429 
                  if DDR_FIFO_Hit='1' and DDR_FIFO_RdEn_Mask='1' then
430 
                     Address_var          <= Address_var;
431 
                     Regs_RdEn            <= '0';
432 
                     TxTLP_eof_n          <= '0';
433 
                     TxMReader_State      <= St_mR_Last;
434 
                  elsif eb_FIFO_Hit='1' and eb_FIFO_RdEn_Mask='1' then
435 
                     Address_var          <= Address_var;
436 
                     Regs_RdEn            <= '0';
437 
                     TxTLP_eof_n          <= '0';
438 
                     TxMReader_State      <= St_mR_Last;
439 
                  elsif eb_FIFO_Hit='0' and regs_Rd_Cntr_eq_One = '1' then
440 
                     Address_var          <= Address_var;
441 
                     Regs_RdEn            <= '0';
442 
                     TxTLP_eof_n          <= '0';
443 
                     TxMReader_State      <= St_mR_Last;
444 
                  elsif eb_FIFO_Hit='0' and regs_Rd_Cntr_eq_Two = '1' then
445 
                     Address_var          <= Address_var;
446 
                     Regs_RdEn            <= '0';
447 
                     TxTLP_eof_n          <= '0';
448 
                     TxMReader_State      <= St_mR_Last;
449 
                  elsif mbuf_aFull_r1 = '1' then
450 
                     Address_var          <= Address_var;
451 
                     Regs_RdEn            <= '0';
452 
                     TxTLP_eof_n          <= TxTLP_eof_n;
453 
                     TxMReader_State      <= St_mR_Transfer;
454 
                  else
455 
                     Address_var(C_EP_AWIDTH-1 downto 0)    <= Address_var(C_EP_AWIDTH-1 downto 0) + "1000";
456 
                     Regs_RdEn            <= Regs_Hit;
457 
                     TxTLP_eof_n          <= TxTLP_eof_n;
458 
                     TxMReader_State      <= St_mR_Transfer;
459 
                  end if;
460 
 
461 
 
462 
            when St_mR_Last    =>
463 
               Regs_RdEn            <= '0';
464 
               DDR_FIFO_RdEn_i      <= '0';
465 
               TxTLP_eof_n          <= (not DDR_FIFO_Hit) and (not eb_FIFO_Hit);
466 
               RdCmd_Ack_i          <= '0';
467 
               TxMReader_State      <= St_mR_Idle;
468 
 
469 
 
470 
            when Others    =>
471 
               Address_var          <= Address_var;
472 
               eb_FIFO_Hit          <= '0';
473 
               Regs_RdEn            <= '0';
474 
               DDR_FIFO_RdEn_i      <= '0';
475 
               TxTLP_eof_n          <= '1';
476 
               RdCmd_Ack_i          <= '0';
477 
               TxMReader_State      <= St_mR_Idle;
478 
 
479 
         end case;
480 
 
481 
 
482 
         case TxMReader_State is
483 
            when St_mR_Idle    =>
484 
              TO_Cnt_Rst   <= '1';
485 
 
486 
            when Others    =>
487 
              TO_Cnt_Rst   <= '0';
488 
 
489 
         end case;
490 
 
491 
 
492 
         case TxMReader_State is
493 
 
494 
            when St_mR_Idle    =>
495 
              DDR_FIFO_RdEn_i  <= '0';
496 
              DDR_FIFO_RdEn_Mask   <= '0';
497 
 
498 
            when Others    =>
499 
              if DDR_Rd_Cntr_eq_One = '1'
500 
                 and (DDR_FIFO_Empty='0' or Tx_TimeOut_i='1')
501 
                 and DDR_FIFO_RdEn_i='1'
502 
                 then
503 
                 DDR_FIFO_RdEn_Mask   <= '1';
504 
                 DDR_FIFO_RdEn_i      <= '0';
505 
              else
506 
                 DDR_FIFO_RdEn_Mask   <= DDR_FIFO_RdEn_Mask;
507 
                 DDR_FIFO_RdEn_i      <=  DDR_FIFO_Hit
508 
                                      and not mbuf_aFull_r1
509 
                                      and not DDR_FIFO_RdEn_Mask;
510 
              end if;
511 
         end case;
512 
 
513 
 
514 
         case TxMReader_State is
515 
 
516 
            when St_mR_Idle    =>
517 
              eb_FIFO_re_i        <= '0';
518 
              eb_FIFO_RdEn_Mask   <= '0';
519 
 
520 
            when Others    =>
521 
              if ebFIFO_Rd_Cntr_eq_Two = '1'
522 
                 and (eb_FIFO_empty='0' or Tx_eb_TimeOut_i='1')
523 
                 and eb_FIFO_re_i='1'
524 
                 then
525 
                 eb_FIFO_RdEn_Mask   <= '1';
526 
                 eb_FIFO_re_i        <= '0';
527 
              else
528 
                 eb_FIFO_RdEn_Mask   <= eb_FIFO_RdEn_Mask;
529 
                 eb_FIFO_re_i        <= eb_FIFO_Hit
530 
                                      and not mbuf_aFull_r1
531 
                                      and not eb_FIFO_RdEn_Mask;
532 
              end if;
533 
         end case;
534 
 
535 
 
536 
         case TxMReader_State is
537 
 
538 
            when St_mR_Idle    =>
539 
              if RdCmd_Req_i='1' and
540 
                 BAR_value(C_ENCODE_BAR_NUMBER-2 downto 0)
541 
                 /= CONV_STD_LOGIC_VECTOR(CINT_DDR_SPACE_BAR, C_ENCODE_BAR_NUMBER-1)
542 
                 then
543 
                 regs_Rd_Counter       <= RdNumber;
544 
                 regs_Rd_Cntr_eq_One   <= RdNumber_eq_One;
545 
                 regs_Rd_Cntr_eq_Two   <= RdNumber_eq_Two;
546 
              else
547 
                 regs_Rd_Counter       <= (Others=>'0');
548 
                 regs_Rd_Cntr_eq_One   <= '0';
549 
                 regs_Rd_Cntr_eq_Two   <= '0';
550 
              end if;
551 
 
552 
            when St_mR_CmdLatch    =>
553 
              if DDR_FIFO_Hit='0' then
554 
                 if Shift_1st_QWord_k='1' then
555 
                   regs_Rd_Counter          <= regs_Rd_Counter - '1';
556 
                   if regs_Rd_Counter = CONV_STD_LOGIC_VECTOR(2, C_TLP_FLD_WIDTH_OF_LENG) then
557 
                      regs_Rd_Cntr_eq_One   <= '1';
558 
                   else
559 
                      regs_Rd_Cntr_eq_One   <= '0';
560 
                   end if;
561 
                   if regs_Rd_Counter = CONV_STD_LOGIC_VECTOR(3, C_TLP_FLD_WIDTH_OF_LENG) then
562 
                      regs_Rd_Cntr_eq_Two   <= '1';
563 
                   else
564 
                      regs_Rd_Cntr_eq_Two   <= '0';
565 
                   end if;
566 
                 else
567 
                   regs_Rd_Counter          <= regs_Rd_Counter - "10";  -- '1';
568 
                   if regs_Rd_Counter = CONV_STD_LOGIC_VECTOR(3, C_TLP_FLD_WIDTH_OF_LENG) then
569 
                      regs_Rd_Cntr_eq_One   <= '1';
570 
                   else
571 
                      regs_Rd_Cntr_eq_One   <= '0';
572 
                   end if;
573 
                   if regs_Rd_Counter = CONV_STD_LOGIC_VECTOR(4, C_TLP_FLD_WIDTH_OF_LENG) then
574 
                      regs_Rd_Cntr_eq_Two   <= '1';
575 
                   else
576 
                      regs_Rd_Cntr_eq_Two   <= '0';
577 
                   end if;
578 
                 end if;
579 
              else
580 
                 regs_Rd_Counter       <= regs_Rd_Counter;
581 
                 regs_Rd_Cntr_eq_One   <= regs_Rd_Cntr_eq_One;
582 
                 regs_Rd_Cntr_eq_Two   <= regs_Rd_Cntr_eq_Two;
583 
              end if;
584 
 
585 
            when St_mR_Transfer    =>
586 
              if DDR_FIFO_Hit='0'
587 
                 and mbuf_aFull_r1 = '0'
588 
                 then
589 
                 regs_Rd_Counter           <= regs_Rd_Counter - "10";  -- '1';
590 
                 if regs_Rd_Counter = CONV_STD_LOGIC_VECTOR(1, C_TLP_FLD_WIDTH_OF_LENG) then
591 
                    regs_Rd_Cntr_eq_One   <= '1';
592 
                 elsif regs_Rd_Counter = CONV_STD_LOGIC_VECTOR(2, C_TLP_FLD_WIDTH_OF_LENG) then
593 
                    regs_Rd_Cntr_eq_One   <= '1';
594 
                 elsif regs_Rd_Counter = CONV_STD_LOGIC_VECTOR(3, C_TLP_FLD_WIDTH_OF_LENG) then
595 
                    regs_Rd_Cntr_eq_One   <= '1';
596 
                 else
597 
                    regs_Rd_Cntr_eq_One   <= '0';
598 
                 end if;
599 
                 if regs_Rd_Counter = CONV_STD_LOGIC_VECTOR(4, C_TLP_FLD_WIDTH_OF_LENG) then
600 
                    regs_Rd_Cntr_eq_Two   <= '1';
601 
                 else
602 
                    regs_Rd_Cntr_eq_Two   <= '0';
603 
                 end if;
604 
              else
605 
                 regs_Rd_Counter       <= regs_Rd_Counter;
606 
                 regs_Rd_Cntr_eq_One   <= regs_Rd_Cntr_eq_One;
607 
                 regs_Rd_Cntr_eq_Two   <= regs_Rd_Cntr_eq_Two;
608 
              end if;
609 
 
610 
            when Others    =>
611 
              regs_Rd_Counter       <= regs_Rd_Counter;
612 
              regs_Rd_Cntr_eq_One   <= regs_Rd_Cntr_eq_One;
613 
              regs_Rd_Cntr_eq_Two   <= regs_Rd_Cntr_eq_Two;
614 
 
615 
         end case;
616 
 
617 
 
618 
         case TxMReader_State is
619 
            when St_mR_Idle    =>
620 
              if RdCmd_Req_i='1' and
621 
                 BAR_value(C_ENCODE_BAR_NUMBER-2 downto 0)
622 
                 = CONV_STD_LOGIC_VECTOR(CINT_DDR_SPACE_BAR, C_ENCODE_BAR_NUMBER-1)
623 
                 then
624 
                 if RdNumber(0)='1' then
625 
                   DDR_Rd_Counter       <= RdNumber + '1';
626 
                   DDR_Rd_Cntr_eq_One   <= RdNumber_eq_One;
627 
                 elsif Shift_1st_QWord='1' then
628 
                   DDR_Rd_Counter       <= RdNumber + "10";
629 
                   DDR_Rd_Cntr_eq_One   <= RdNumber_eq_One;
630 
                 else
631 
                   DDR_Rd_Counter       <= RdNumber;
632 
                   DDR_Rd_Cntr_eq_One   <= RdNumber_eq_One or RdNumber_eq_Two;
633 
                 end if;
634 
              else
635 
                 DDR_Rd_Counter       <= (Others=>'0');
636 
                 DDR_Rd_Cntr_eq_One   <= '0';
637 
              end if;
638 
 
639 
            when Others    =>
640 
              if ((DDR_FIFO_Empty='0' or Tx_TimeOut_i='1') and DDR_FIFO_RdEn_i='1')
641 
                 then
642 
                 DDR_Rd_Counter       <= DDR_Rd_Counter - "10";  -- '1';
643 
                 if DDR_Rd_Counter = CONV_STD_LOGIC_VECTOR(4, C_TLP_FLD_WIDTH_OF_LENG) then
644 
                    DDR_Rd_Cntr_eq_One   <= '1';
645 
                 else
646 
                    DDR_Rd_Cntr_eq_One   <= '0';
647 
                 end if;
648 
              else
649 
                 DDR_Rd_Counter       <= DDR_Rd_Counter;
650 
                 DDR_Rd_Cntr_eq_One   <= DDR_Rd_Cntr_eq_One;
651 
              end if;
652 
 
653 
         end case;
654 
 
655 
 
656 
         case TxMReader_State is
657 
            when St_mR_Idle    =>
658 
              if RdCmd_Req_i='1' and
659 
                 BAR_value(C_ENCODE_BAR_NUMBER-2 downto 0)
660 
                 = CONV_STD_LOGIC_VECTOR(CINT_FIFO_SPACE_BAR, C_ENCODE_BAR_NUMBER-1)
661 
                 then
662 
                 if RdNumber_eq_One='1' then
663 
                   ebFIFO_Rd_Counter       <= RdNumber + '1';
664 
                   ebFIFO_Rd_Cntr_eq_Two   <= '1';
665 
                   ebFIFO_Rd_1DW           <= '1';
666 
                 else
667 
                   ebFIFO_Rd_Counter       <= RdNumber;
668 
                   ebFIFO_Rd_Cntr_eq_Two   <= RdNumber_eq_Two;  -- or RdNumber_eq_One;
669 
                   ebFIFO_Rd_1DW           <= '0';
670 
                 end if;
671 
              else
672 
                 ebFIFO_Rd_Counter       <= (Others=>'0');
673 
                 ebFIFO_Rd_Cntr_eq_Two   <= '0';
674 
                 ebFIFO_Rd_1DW           <= '0';
675 
              end if;
676 
 
677 
            when Others    =>
678 
              ebFIFO_Rd_1DW           <= ebFIFO_Rd_1DW;
679 
              if (eb_FIFO_empty='0' or Tx_eb_TimeOut_i='1') and eb_FIFO_re_i='1'
680 
                 then
681 
                 ebFIFO_Rd_Counter       <= ebFIFO_Rd_Counter - "10";  -- '1';
682 
                 if ebFIFO_Rd_Counter = CONV_STD_LOGIC_VECTOR(4, C_TLP_FLD_WIDTH_OF_LENG) then
683 
                    ebFIFO_Rd_Cntr_eq_Two   <= '1';
684 
                 else
685 
                    ebFIFO_Rd_Cntr_eq_Two   <= '0';
686 
                 end if;
687 
              else
688 
                 ebFIFO_Rd_Counter       <= ebFIFO_Rd_Counter;
689 
                 ebFIFO_Rd_Cntr_eq_Two   <= ebFIFO_Rd_Cntr_eq_Two;
690 
              end if;
691 
 
692 
         end case;
693 
 
694 
      end if;
695 
   end process;
696 
 
697 
 
698 
-----------------------------------------------------
699 
-- Synchronous Delay: mbuf_writes
700 
--
701 
   Synchron_Delay_mbuf_writes:
702 
   process ( trn_clk )
703 
   begin
704 
     if trn_clk'event and trn_clk = '1' then
705 
         Regs_Write_mbuf_r1      <= Regs_RdEn;
706 
         Regs_Write_mbuf_r2      <= Regs_Write_mbuf_r1;
707 
         Regs_Write_mbuf_r3      <= Regs_Write_mbuf_r2;
708 
 
709 
         DDR_FIFO_Write_mbuf_r1  <= DDR_FIFO_RdEn_i and (not DDR_FIFO_Empty or Tx_TimeOut_i);
710 
         DDR_FIFO_Write_mbuf_r2  <= DDR_FIFO_Write_mbuf_r1;
711 
         DDR_FIFO_Write_mbuf_r3  <= DDR_FIFO_Write_mbuf_r2;
712 
 
713 
         eb_FIFO_Write_mbuf      <= eb_FIFO_re_i and (not eb_FIFO_empty or Tx_eb_TimeOut_i);
714 
         eb_FIFO_Write_mbuf_r1   <= eb_FIFO_Write_mbuf;
715 
         eb_FIFO_Write_mbuf_r2   <= eb_FIFO_Write_mbuf_r1;
716 
 
717 
         eb_FIFO_RdEn_Mask_r1    <= eb_FIFO_RdEn_Mask;
718 
         eb_FIFO_RdEn_Mask_r2    <= eb_FIFO_RdEn_Mask_r1;
719 
 
720 
      end if;
721 
   end process;
722 
 
723 
 
724 
--------------------------------------------------------------------------
725 
--  Wires to be OR'ed to build mbuf_Din
726 
--------------------------------------------------------------------------
727 
 
728 
   eb_FIFO_Dout_wire     <= eb_FIFO_qout_r1 when (eb_FIFO_Hit='1' and Shift_1st_QWord_k='0')
729 
                            else eb_FIFO_qout_shift when (eb_FIFO_Hit='1' and Shift_1st_QWord_k='1')
730 
                            else (OTHERS=>'0');
731 
   DDR_Dout_wire         <= DDR_FIFO_RdQout when DDR_FIFO_Hit='1'  else (OTHERS=>'0');
732 
   Regs_RdQout_wire      <= Regs_RdQout     when Regs_Hit='1'      else (OTHERS=>'0');
733 
 
734 
   mbuf_Din_wire_OR      <= eb_FIFO_Dout_wire or DDR_Dout_wire   or Regs_RdQout_wire;
735 
 
736 
-----------------------------------------------------
737 
-- Synchronous Delay: mbuf_WE
738 
--
739 
   Synchron_Delay_mbuf_WE:
740 
   process ( trn_clk )
741 
   begin
742 
     if trn_clk'event and trn_clk = '1' then
743 
         mbuf_WE_i      <= DDR_FIFO_Write_mbuf_r1
744 
                        or Regs_Write_mbuf_r2
745 
                        or (eb_FIFO_Write_mbuf_r1 or (Shift_1st_QWord_k and eb_FIFO_RdEn_Mask_rise_r1))
746 
                        ;
747 
      end if;
748 
   end process;
749 
 
750 
 
751 
-----------------------------------------------------
752 
-- Synchronous Delay: TxTLP_eof_n
753 
--
754 
   Synchron_Delay_TxTLP_eof_n:
755 
   process ( trn_clk )
756 
   begin
757 
     if trn_clk'event and trn_clk = '1' then
758 
         TxTLP_eof_n_r1      <= TxTLP_eof_n;
759 
--         TxTLP_eof_n_r2      <= TxTLP_eof_n_r1;
760 
      end if;
761 
   end process;
762 
 
763 
--   eb_FIFO_qout_swapped  <= eb_FIFO_qout(C_DBUS_WIDTH/2-1 downto 0) & eb_FIFO_qout(C_DBUS_WIDTH-1 downto C_DBUS_WIDTH/2);
764 
   eb_FIFO_qout_swapped  <= eb_FIFO_qout(C_DBUS_WIDTH/2+7  downto C_DBUS_WIDTH/2)
765 
                          & eb_FIFO_qout(C_DBUS_WIDTH/2+15 downto C_DBUS_WIDTH/2+8)
766 
                          & eb_FIFO_qout(C_DBUS_WIDTH/2+23 downto C_DBUS_WIDTH/2+16)
767 
                          & eb_FIFO_qout(C_DBUS_WIDTH/2+31 downto C_DBUS_WIDTH/2+24)
768 
 
769 
                          & eb_FIFO_qout(7  downto 0)
770 
                          & eb_FIFO_qout(15 downto 8)
771 
                          & eb_FIFO_qout(23 downto 16)
772 
                          & eb_FIFO_qout(31 downto 24)
773 
                          ;
774 
 
775 
-----------------------------------------------------
776 
-- Synchronous Delay: eb_FIFO_qout
777 
--
778 
   Synchron_Delay_eb_FIFO_qout:
779 
   process ( trn_clk )
780 
   begin
781 
     if trn_clk'event and trn_clk = '1' then
782 
        eb_FIFO_RdEn_Mask_rise    <= eb_FIFO_RdEn_Mask and not eb_FIFO_RdEn_Mask_r1;
783 
        eb_FIFO_RdEn_Mask_rise_r1 <= eb_FIFO_RdEn_Mask_rise;
784 
        eb_FIFO_RdEn_Mask_rise_r2 <= eb_FIFO_RdEn_Mask_rise_r1;
785 
        eb_FIFO_qout_r1           <= eb_FIFO_qout_swapped;
786 
        eb_FIFO_qout_shift        <= eb_FIFO_qout_r1(C_DBUS_WIDTH/2-1 downto 0)
787 
                                   & eb_FIFO_qout_swapped(C_DBUS_WIDTH-1 downto C_DBUS_WIDTH/2);
788 
      end if;
789 
   end process;
790 
 
791 
-----------------------------------------------------
792 
-- Synchronous Delay: mbuf_Din
793 
--
794 
   Synchron_Delay_mbuf_Din:
795 
   process ( trn_clk, mReader_Rst_n)
796 
   begin
797 
      if mReader_Rst_n = '0' then
798 
         mbuf_Din_i           <= (C_DBUS_WIDTH=>'1', Others=>'0');
799 
 
800 
      elsif trn_clk'event and trn_clk = '1' then
801 
         if Tx_TimeOut_i='1' and DDR_FIFO_Hit='1' then
802 
           mbuf_Din_i(C_DBUS_WIDTH-1 downto 0)     <= (OTHERS=>'1');
803 
         elsif Tx_eb_TimeOut_i='1' and eb_FIFO_Hit='1' and is_CplD_k='1' then
804 
           mbuf_Din_i(C_DBUS_WIDTH-1 downto 0)     <= (OTHERS=>'1');
805 
         elsif Tx_eb_TimeOut_i='1' and eb_FIFO_Hit='1' and may_be_MWr_k='1' then
806 
           mbuf_Din_i(C_DBUS_WIDTH-1 downto 0)     <= (OTHERS=>'1');
807 
         else
808 
           mbuf_Din_i(C_DBUS_WIDTH-1 downto 0)     <= Endian_Invert_64(mbuf_Din_wire_OR);
809 
         end if;
810 
 
811 
         if DDR_FIFO_Hit='1' then
812 
           mbuf_Din_i(C_DBUS_WIDTH)                <= not DDR_FIFO_RdEn_Mask;
813 
           mbuf_Din_i(70)                          <= TRem_n_last_QWord;
814 
         elsif eb_FIFO_Hit='1' then
815 
           if Shift_1st_QWord_k='1' and ebFIFO_Rd_1DW='0' then
816 
              mbuf_Din_i(C_DBUS_WIDTH)                <= not eb_FIFO_RdEn_Mask_r2;
817 
           else
818 
              mbuf_Din_i(C_DBUS_WIDTH)                <= not eb_FIFO_RdEn_Mask_r1;
819 
           end if;
820 
           mbuf_Din_i(70)                          <= TRem_n_last_QWord;
821 
         else
822 
           mbuf_Din_i(C_DBUS_WIDTH)                <= TxTLP_eof_n_r1;
823 
           mbuf_Din_i(70)                          <= TRem_n_last_QWord;
824 
         end if;
825 
      end if;
826 
   end process;
827 
 
828 
 
829 
-----------------------------------------------------
830 
-- Synchronous: Time-out counter
831 
--
832 
   Synchron_TimeOut_Counter:
833 
   process ( trn_clk, TO_Cnt_Rst )
834 
   begin
835 
      if TO_Cnt_Rst='1' then
836 
         TimeOut_Counter        <= (OTHERS=>'0');
837 
         TimeOut_Indic_TX       <= '0';
838 
         TimeOut_Indic_eb_CplD  <= '0';
839 
         TimeOut_Indic_eb_MWr   <= '0';
840 
      elsif trn_clk'event and trn_clk = '1' then
841 
         TimeOut_Counter(21 downto 0)   <= TimeOut_Counter(21 downto 0) + '1';
842 
 
843 
         if TimeOut_Counter(21 downto 10)=X"FFF" then
844 
--         if TimeOut_Counter(4 downto 1)=X"F" then
845 
            TimeOut_Indic_TX       <= '1';
846 
         else
847 
            TimeOut_Indic_TX       <= '0';
848 
         end if;
849 
 
850 
         if TimeOut_Counter(7 downto 4)=X"F" then
851 
--         if TimeOut_Counter(3 downto 0)=X"F" then
852 
            TimeOut_Indic_eb_CplD  <= '1';
853 
         else
854 
            TimeOut_Indic_eb_CplD  <= '0';
855 
         end if;
856 
 
857 
         if TimeOut_Counter(10 downto 7)=X"F" then
858 
--         if TimeOut_Counter(3 downto 0)=X"F" then
859 
            TimeOut_Indic_eb_MWr   <= '1';
860 
         else
861 
            TimeOut_Indic_eb_MWr   <= '0';
862 
         end if;
863 
 
864 
      end if;
865 
   end process;
866 
 
867 
-----------------------------------------------------
868 
-- Synchronous: Tx_TimeOut
869 
--
870 
   SynchOUT_Tx_TimeOut:
871 
   process ( trn_clk, mReader_Rst_n )
872 
   begin
873 
      if mReader_Rst_n='0' then
874 
         Tx_TimeOut_i      <= '0';
875 
      elsif trn_clk'event and trn_clk = '1' then
876 
         if TimeOut_Indic_TX='1' then
877 
            Tx_TimeOut_i   <= '1';
878 
         else
879 
            Tx_TimeOut_i   <= Tx_TimeOut_i;
880 
         end if;
881 
      end if;
882 
   end process;
883 
 
884 
-----------------------------------------------------
885 
-- Synchronous: Tx_eb_TimeOut
886 
--
887 
   SynchOUT_Tx_eb_TimeOut:
888 
   process ( trn_clk, mReader_Rst_n )
889 
   begin
890 
      if mReader_Rst_n='0' then
891 
         Tx_eb_TimeOut_i      <= '0';
892 
      elsif trn_clk'event and trn_clk = '1' then
893 
         if TimeOut_Indic_eb_CplD='1' and is_CplD_k='1'
894 
            then
895 
            Tx_eb_TimeOut_i   <= '1';
896 
         elsif TimeOut_Indic_eb_MWr='1' and may_be_MWr_k='1'
897 
            then
898 
            Tx_eb_TimeOut_i   <= '1';
899 
         else
900 
            Tx_eb_TimeOut_i   <= Tx_eb_TimeOut_i;
901 
         end if;
902 
      end if;
903 
   end process;
904 
 
905 
end architecture Behavioral;

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