Subversion Repositories pcie_sg_dma

0. This directory contains simulation environment for the pcie_sg_dma design.

    tf64_pcie_trn.v is the simulation file in Verilog HDL.

    sg_sim.mpf is the ModelSim project file. So your ModelSim version has to support mixed HDL because the design files are mostly written in VHDL. If you want to help in translating this simulation into VHDL, contact me via

weng.ziti@gmail.com. Thanks in advance.

1. To start the simulation, open the sg_sim.mpf in ModelSim, and simulate the tf64_pcie_trn.v after compiling the work library.

2. The simulation takes the tlpControl module as the kernel UUT and tries to emulate the behavior of the PCIe core on the TRN layer.

Block RAM (bram_controller) is simulated for the RAM memory.

FIFO_Wrapper is simulated for the one-hole type memory.

Three BARs are implemented in the design,

BAR[0] --  4KB, registers; for PIO

BAR[1] --  1MB, BRAM; for PIO and DMA

BAR[2] --  4KB, FIFO; for half-bus (32-bit) PIO and and full-bus (64-bit) DMA

3. The TLP sending is done in the taks TLP_Feed_Rx, which simplifies the cycles control over an RX TLP sending.

    This also enables the user to build his or her simulation on the TRN layer.

4. This simulation runs for about 10 us and is sequenced with following 5 major test cases,

  (1) BAR[0] PIO write and read

  (2) BAR[1] PIO write and read

  (3) BAR[2] PIO write and read

  (4) BAR[1] DMA write and read

  (5) BAR[2] DMA write and read

  FSM_Tx_Desc_MRd process feeds CplD to the DMA descriptor MRd for DMA cases.

5. The process of FSM_TLP_Fmt is to check the validity of TX TLP format.

    The process of FSM_Rx_Fmt is to check the validity of RX TLP format, namely verification of verification.

    The simulation stops at any format failure if you try to develop your own simulations.

6. Any questions or suggestions, send me email to weng.ziti@gmail.com.