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weng_ziti |
###############################################################################
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#
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# File: xilinx_pci_exp_blk_plus_4_lane_ep_xc5vlx110t-ff1136-1.ucf
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#
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# Use this file only with the device listed below. Any other
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# combination is invalid. Do not modify this file except in
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# regions designated for "User" constraints.
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#
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# Copyright (c) 2008 Xilinx, Inc. All rights reserved.
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#
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###############################################################################
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# Define Device, Package And Speed Grade
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###############################################################################
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CONFIG PART = XC5VLX110T-FF1136-1;
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###############################################################################
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# User Time Names / User Time Groups / Time Specs
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###############################################################################
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###############################################################################
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# User Physical Constraints
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###############################################################################
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###############################################################################
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# Pinout and Related I/O Constraints
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###############################################################################
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#
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# SYS reset (input) signal. The sys_reset_n signal should be
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# obtained from the PCI Express interface if possible. For
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# slot based form factors, a system reset signal is usually
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# present on the connector. For cable based form factors, a
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# system reset signal may not be available. In this case, the
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# system reset signal must be generated locally by some form of
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# supervisory circuit. You may change the IOSTANDARD and LOC
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# to suit your requirements and VCCO voltage banking rules.
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#
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# # NET "sys_reset_n" LOC = "AE14" | IOSTANDARD = LVCMOS25 | PULLUP | NODELAY ;
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#NET "sys_reset_n" LOC = "H25" | IOSTANDARD = LVCMOS25 | PULLUP | NODELAY ;
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#
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# SYS clock 100 MHz (input) signal. The sys_clk_p and sys_clk_n
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# signals are the PCI Express reference clock. Virtex-5 GTP
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# Transceiver architecture requires the use of a dedicated clock
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# resources (FPGA input pins) associated with each GTP Transceiver Tile.
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# To use these pins an IBUFDS primitive (refclk_ibuf) is
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# instantiated in user's design.
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# Please refer to the Virtex-5 GTP Transceiver User Guide
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# (UG196) for guidelines regarding clock resource selection.
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#
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NET "sys_clk_p" LOC = "P4" ;
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NET "sys_clk_n" LOC = "P3" ;
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INST "refclk_ibuf" DIFF_TERM = "TRUE" ;
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NET "refclkout" LOC = B32 ;
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# LEDs
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Net LEDs_IO_pin<0> LOC=H13;
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Net LEDs_IO_pin<0> IOSTANDARD=LVCMOS25;
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Net LEDs_IO_pin<0> PULLDOWN;
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Net LEDs_IO_pin<0> SLEW=SLOW;
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Net LEDs_IO_pin<0> DRIVE=2;
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Net LEDs_IO_pin<1> LOC=J17 ;
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Net LEDs_IO_pin<1> IOSTANDARD=LVCMOS25;
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Net LEDs_IO_pin<1> PULLDOWN;
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Net LEDs_IO_pin<1> SLEW=SLOW;
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Net LEDs_IO_pin<1> DRIVE=2;
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Net LEDs_IO_pin<2> LOC=H15 ;
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Net LEDs_IO_pin<2> IOSTANDARD=LVCMOS25;
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Net LEDs_IO_pin<2> PULLDOWN;
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Net LEDs_IO_pin<2> SLEW=SLOW;
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Net LEDs_IO_pin<2> DRIVE=2;
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Net LEDs_IO_pin<3> LOC=G16 ;
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Net LEDs_IO_pin<3> IOSTANDARD=LVCMOS25;
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Net LEDs_IO_pin<3> PULLDOWN;
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Net LEDs_IO_pin<3> SLEW=SLOW;
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Net LEDs_IO_pin<3> DRIVE=2;
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Net LEDs_IO_pin<4> LOC=L18 ;
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Net LEDs_IO_pin<4> IOSTANDARD=LVCMOS25;
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Net LEDs_IO_pin<4> PULLDOWN;
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Net LEDs_IO_pin<4> SLEW=SLOW;
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Net LEDs_IO_pin<4> DRIVE=2;
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Net LEDs_IO_pin<5> LOC=H18 ;
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Net LEDs_IO_pin<5> IOSTANDARD=LVCMOS25;
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Net LEDs_IO_pin<5> PULLDOWN;
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Net LEDs_IO_pin<5> SLEW=SLOW;
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Net LEDs_IO_pin<5> DRIVE=2;
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Net LEDs_IO_pin<6> LOC=J19 ;
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Net LEDs_IO_pin<6> IOSTANDARD=LVCMOS25;
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Net LEDs_IO_pin<6> PULLDOWN;
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Net LEDs_IO_pin<6> SLEW=SLOW;
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Net LEDs_IO_pin<6> DRIVE=2;
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Net LEDs_IO_pin<7> LOC=J21 ;
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Net LEDs_IO_pin<7> IOSTANDARD=LVCMOS25;
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Net LEDs_IO_pin<7> PULLDOWN;
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Net LEDs_IO_pin<7> SLEW=SLOW;
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Net LEDs_IO_pin<7> DRIVE=2;
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#
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# Transceiver instance placement. This constraint selects the
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# transceivers to be used, which also dictates the pinout for the
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# transmit and receive differential pairs. Please refer to the
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# Virtex-5 GTP Transceiver User Guide (UG196) for more
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# information.
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#
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# PCIe Lanes 0, 1
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INST "make4Lanes.pcieCore/BU2/U0/pcie_ep0/pcie_blk/SIO/.pcie_gt_wrapper_i/GTD[0].GT_i" LOC = GTP_DUAL_X0Y4;
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# PCIe Lanes 2, 3
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INST "make4Lanes.pcieCore/BU2/U0/pcie_ep0/pcie_blk/SIO/.pcie_gt_wrapper_i/GTD[2].GT_i" LOC = GTP_DUAL_X0Y3;
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## Lock down the PLL:
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#INST "*/pcie_clocking_i/use_pll.pll_i" LOC = PLL_ADV_X0Y2;
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###############################################################################
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# Physical Constraints
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###############################################################################
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#
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# BlockRAM placement
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#
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INST "make4Lanes.pcieCore/BU2/U0/pcie_ep0/pcie_blk/pcie_mim_wrapper_i/bram_retry/generate_sdp.ram_sdp_inst" LOC = RAMB36_X3Y12 ;
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INST "make4Lanes.pcieCore/BU2/U0/pcie_ep0/pcie_blk/pcie_mim_wrapper_i/bram_tl_tx/generate_tdp2[1].ram_tdp2_inst" LOC = RAMB36_X3Y11 ;
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INST "make4Lanes.pcieCore/BU2/U0/pcie_ep0/pcie_blk/pcie_mim_wrapper_i/bram_tl_rx/generate_tdp2[1].ram_tdp2_inst" LOC = RAMB36_X3Y10 ;
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INST "make4Lanes.pcieCore/BU2/U0/pcie_ep0/pcie_blk/pcie_mim_wrapper_i/bram_tl_tx/generate_tdp2[0].ram_tdp2_inst" LOC = RAMB36_X3Y9 ;
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INST "make4Lanes.pcieCore/BU2/U0/pcie_ep0/pcie_blk/pcie_mim_wrapper_i/bram_tl_rx/generate_tdp2[0].ram_tdp2_inst" LOC = RAMB36_X3Y8 ;
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#
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# Timing critical placements
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#
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INST "make4Lanes.pcieCore/BU2/U0/pcie_ep0/pcie_blk_if/ll_bridge/tx_bridge/tx_bridge/shift_pipe1" LOC = "SLICE_X107Y56" ;
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INST "make4Lanes.pcieCore/BU2/U0/pcie_ep0/pcie_blk_if/ll_bridge/rx_bridge/arb_inst/completion_available" LOC = "SLICE_X106Y46" ;
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INST "make4Lanes.pcieCore/BU2/U0/pcie_ep0/pcie_blk_if/cf_bridge/management_interface/mgmt_rdata_d1_3" LOC = "SLICE_X107Y45" ;
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###############################################################################
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# Timing Constraints
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###############################################################################
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#
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# Timing requirements and related constraints.
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#
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NET "sys_clk_n" TNM_NET = sys_clk_n;
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TIMESPEC TS_sys_clk_n = PERIOD "sys_clk_n" 10 ns LOW 50%;
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NET "sys_clk_p" TNM_NET = sys_clk_p;
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TIMESPEC TS_sys_clk_p = PERIOD "sys_clk_p" 10 ns HIGH 50%;
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NET "make4Lanes.pcieCore/BU2/U0/pcie_ep0/pcie_blk/SIO/.pcie_gt_wrapper_i/gt_refclk_out[0]" TNM_NET = "MGTCLK" ;
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TIMESPEC "TS_MGTCLK" = PERIOD "MGTCLK" 100.00 MHz HIGH 50 % ;
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Net Button_Rst LOC = AM32 |IOSTANDARD = LVCMOS25;
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Net Button_Rst TIG;
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## System level constraints
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###############################################################################
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# End
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###############################################################################
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