Subversion Repositories pcie_sg_dma

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#

# File:   xilinx_pci_exp_blk_plus_4_lane_ep_xc5vlx110t-ff1136-1.ucf

#

# Use this file only with the device listed below.  Any other

# combination is invalid.  Do not modify this file except in

# regions designated for "User" constraints.

#

# Copyright (c) 2008 Xilinx, Inc.  All rights reserved.

#

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# Define Device, Package And Speed Grade

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CONFIG PART = XC5VLX110T-FF1136-1;

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# User Time Names / User Time Groups / Time Specs

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# User Physical Constraints

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# Pinout and Related I/O Constraints

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#

# SYS reset (input) signal.  The sys_reset_n signal should be

# obtained from the PCI Express interface if possible.  For

# slot based form factors, a system reset signal is usually

# present on the connector.  For cable based form factors, a

# system reset signal may not be available.  In this case, the

# system reset signal must be generated locally by some form of

# supervisory circuit.  You may change the IOSTANDARD and LOC

# to suit your requirements and VCCO voltage banking rules.

#

# # NET "sys_reset_n"      LOC = "AE14"  | IOSTANDARD = LVCMOS25 | PULLUP | NODELAY ;

#NET "sys_reset_n"      LOC = "H25"  | IOSTANDARD = LVCMOS25 | PULLUP | NODELAY ;

#

# SYS clock 100 MHz (input) signal. The sys_clk_p and sys_clk_n

# signals are the PCI Express reference clock. Virtex-5 GTP

# Transceiver architecture requires the use of a dedicated clock

# resources (FPGA input pins) associated with each GTP Transceiver Tile.

# To use these pins an IBUFDS primitive (refclk_ibuf) is

# instantiated in user's design.

# Please refer to the Virtex-5 GTP Transceiver User Guide

# (UG196) for guidelines regarding clock resource selection.

#

NET  "sys_clk_p"       LOC = "P4"  ;

NET  "sys_clk_n"       LOC = "P3"  ;

INST "refclk_ibuf"     DIFF_TERM = "TRUE" ;

NET  "refclkout"       LOC = B32   ;

# LEDs

Net LEDs_IO_pin<0> LOC=H13;

Net LEDs_IO_pin<0> IOSTANDARD=LVCMOS25;

Net LEDs_IO_pin<0> PULLDOWN;

Net LEDs_IO_pin<0> SLEW=SLOW;

Net LEDs_IO_pin<0> DRIVE=2;

Net LEDs_IO_pin<1> LOC=J17 ;

Net LEDs_IO_pin<1> IOSTANDARD=LVCMOS25;

Net LEDs_IO_pin<1> PULLDOWN;

Net LEDs_IO_pin<1> SLEW=SLOW;

Net LEDs_IO_pin<1> DRIVE=2;

Net LEDs_IO_pin<2> LOC=H15 ;

Net LEDs_IO_pin<2> IOSTANDARD=LVCMOS25;

Net LEDs_IO_pin<2> PULLDOWN;

Net LEDs_IO_pin<2> SLEW=SLOW;

Net LEDs_IO_pin<2> DRIVE=2;

Net LEDs_IO_pin<3> LOC=G16 ;

Net LEDs_IO_pin<3> IOSTANDARD=LVCMOS25;

Net LEDs_IO_pin<3> PULLDOWN;

Net LEDs_IO_pin<3> SLEW=SLOW;

Net LEDs_IO_pin<3> DRIVE=2;

Net LEDs_IO_pin<4> LOC=L18 ;

Net LEDs_IO_pin<4> IOSTANDARD=LVCMOS25;

Net LEDs_IO_pin<4> PULLDOWN;

Net LEDs_IO_pin<4> SLEW=SLOW;

Net LEDs_IO_pin<4> DRIVE=2;

Net LEDs_IO_pin<5> LOC=H18 ;

Net LEDs_IO_pin<5> IOSTANDARD=LVCMOS25;

Net LEDs_IO_pin<5> PULLDOWN;

Net LEDs_IO_pin<5> SLEW=SLOW;

Net LEDs_IO_pin<5> DRIVE=2;

Net LEDs_IO_pin<6> LOC=J19 ;

Net LEDs_IO_pin<6> IOSTANDARD=LVCMOS25;

Net LEDs_IO_pin<6> PULLDOWN;

Net LEDs_IO_pin<6> SLEW=SLOW;

Net LEDs_IO_pin<6> DRIVE=2;

Net LEDs_IO_pin<7> LOC=J21 ;

Net LEDs_IO_pin<7> IOSTANDARD=LVCMOS25;

Net LEDs_IO_pin<7> PULLDOWN;

Net LEDs_IO_pin<7> SLEW=SLOW;

Net LEDs_IO_pin<7> DRIVE=2;

#

# Transceiver instance placement.  This constraint selects the

# transceivers to be used, which also dictates the pinout for the

# transmit and receive differential pairs.  Please refer to the

# Virtex-5 GTP Transceiver User Guide (UG196) for more

# information.

#

# PCIe Lanes 0, 1

INST "make4Lanes.pcieCore/BU2/U0/pcie_ep0/pcie_blk/SIO/.pcie_gt_wrapper_i/GTD[0].GT_i" LOC = GTP_DUAL_X0Y4;

# PCIe Lanes 2, 3

INST "make4Lanes.pcieCore/BU2/U0/pcie_ep0/pcie_blk/SIO/.pcie_gt_wrapper_i/GTD[2].GT_i" LOC = GTP_DUAL_X0Y3;

## Lock down the PLL:

#INST "*/pcie_clocking_i/use_pll.pll_i" LOC = PLL_ADV_X0Y2;

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# Physical Constraints

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#

# BlockRAM placement

#

INST "make4Lanes.pcieCore/BU2/U0/pcie_ep0/pcie_blk/pcie_mim_wrapper_i/bram_retry/generate_sdp.ram_sdp_inst"      LOC = RAMB36_X3Y12 ;

INST "make4Lanes.pcieCore/BU2/U0/pcie_ep0/pcie_blk/pcie_mim_wrapper_i/bram_tl_tx/generate_tdp2[1].ram_tdp2_inst" LOC = RAMB36_X3Y11 ;

INST "make4Lanes.pcieCore/BU2/U0/pcie_ep0/pcie_blk/pcie_mim_wrapper_i/bram_tl_rx/generate_tdp2[1].ram_tdp2_inst" LOC = RAMB36_X3Y10 ;

INST "make4Lanes.pcieCore/BU2/U0/pcie_ep0/pcie_blk/pcie_mim_wrapper_i/bram_tl_tx/generate_tdp2[0].ram_tdp2_inst" LOC = RAMB36_X3Y9 ;

INST "make4Lanes.pcieCore/BU2/U0/pcie_ep0/pcie_blk/pcie_mim_wrapper_i/bram_tl_rx/generate_tdp2[0].ram_tdp2_inst" LOC = RAMB36_X3Y8 ;

#

# Timing critical placements

#

INST "make4Lanes.pcieCore/BU2/U0/pcie_ep0/pcie_blk_if/ll_bridge/tx_bridge/tx_bridge/shift_pipe1" LOC = "SLICE_X107Y56" ;

INST "make4Lanes.pcieCore/BU2/U0/pcie_ep0/pcie_blk_if/ll_bridge/rx_bridge/arb_inst/completion_available" LOC = "SLICE_X106Y46" ;

INST "make4Lanes.pcieCore/BU2/U0/pcie_ep0/pcie_blk_if/cf_bridge/management_interface/mgmt_rdata_d1_3" LOC = "SLICE_X107Y45" ;

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# Timing Constraints

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#

# Timing requirements and related constraints.

#

NET "sys_clk_n" TNM_NET = sys_clk_n;

TIMESPEC TS_sys_clk_n = PERIOD "sys_clk_n" 10 ns LOW 50%;

NET "sys_clk_p" TNM_NET = sys_clk_p;

TIMESPEC TS_sys_clk_p = PERIOD "sys_clk_p" 10 ns HIGH 50%;

NET "make4Lanes.pcieCore/BU2/U0/pcie_ep0/pcie_blk/SIO/.pcie_gt_wrapper_i/gt_refclk_out[0]" TNM_NET = "MGTCLK" ;

TIMESPEC "TS_MGTCLK"  = PERIOD "MGTCLK" 100.00 MHz HIGH 50 % ;

Net Button_Rst   LOC = AM32 |IOSTANDARD = LVCMOS25;

Net Button_Rst TIG;

## System level constraints

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# End

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