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cmagleby |
// ===========================================================================
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// File : ti_phy_top.if.vrh
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// Author : cwinward
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// Date : Mon Dec 3 11:03:46 MST 2007
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// Project : TI PHY design
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//
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// Copyright (c) notice
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// This code adheres to the GNU public license
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//
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// ===========================================================================
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//
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cmagleby |
// $Id: ti_phy_top.if.vrh,v 1.2 2008-01-15 03:25:07 cmagleby Exp $
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cmagleby |
//
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// ===========================================================================
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//
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// $Log: not supported by cvs2svn $
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cmagleby |
// Revision 1.1.1.1 2007/12/05 18:37:07 cmagleby
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// importing tb files
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//
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//
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cmagleby |
// ===========================================================================
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// Function : .This is the interface file linking verilog with VERA
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//
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// ===========================================================================
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// ===========================================================================
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#ifndef INC_TI_PHY_TOP_IF_VRH
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#define INC_TI_PHY_TOP_IF_VRH
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interface ti_phy_top {
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input rxclk CLOCK;
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//input [9:0] t1_count PSAMPLE #-1 verilog_node "dut.phy_layer_top_inst.tx_alignment_32_inst.ts_1024_count";
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output clk_50mhz OUTPUT_EDGE OUTPUT_SKEW;
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output [1:0] PUSH_BUTTON OUTPUT_EDGE OUTPUT_SKEW;
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output FPGA_RESET_n OUTPUT_EDGE OUTPUT_SKEW;
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cmagleby |
output PERST_n OUTPUT_EDGE OUTPUT_SKEW;
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output [15:0] rxdata16 OUTPUT_EDGE OUTPUT_SKEW;
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output [1:0] rxdatak16 OUTPUT_EDGE OUTPUT_SKEW;
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output rxvalid16 OUTPUT_EDGE OUTPUT_SKEW;
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output rxidle16 OUTPUT_EDGE OUTPUT_SKEW;
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output [2:0] rxstatus OUTPUT_EDGE OUTPUT_SKEW;
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output phystatus OUTPUT_EDGE OUTPUT_SKEW;
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input [7:0] LED INPUT_EDGE INPUT_SKEW;
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input txclk INPUT_EDGE INPUT_SKEW;
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input [15:0] txdata16 INPUT_EDGE INPUT_SKEW;
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input [1:0] txdatak16 INPUT_EDGE INPUT_SKEW;
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input txidle16 INPUT_EDGE INPUT_SKEW;
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input rxdet_loopb INPUT_EDGE INPUT_SKEW;
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input txcomp INPUT_EDGE INPUT_SKEW;
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input rxpol INPUT_EDGE INPUT_SKEW;
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input phy_reset_n INPUT_EDGE INPUT_SKEW;
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input [1:0] pwrdwn INPUT_EDGE INPUT_SKEW;
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input [16:0] sram_addr INPUT_EDGE INPUT_SKEW;
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input sram_adscn INPUT_EDGE INPUT_SKEW;
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input sram_adspn INPUT_EDGE INPUT_SKEW;
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input sram_advn INPUT_EDGE INPUT_SKEW;
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input [3:0] sram_ben INPUT_EDGE INPUT_SKEW;
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input [2:0] sram_ce INPUT_EDGE INPUT_SKEW;
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input sram_clk INPUT_EDGE INPUT_SKEW;
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input sram_gwn INPUT_EDGE INPUT_SKEW;
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input sram_mode INPUT_EDGE INPUT_SKEW;
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input sram_oen INPUT_EDGE INPUT_SKEW;
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input sram_wen INPUT_EDGE INPUT_SKEW;
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input sram_zz INPUT_EDGE INPUT_SKEW;
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inout [35:0] sram_data INPUT_EDGE INPUT_SKEW OUTPUT_EDGE OUTPUT_SKEW;
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} // end of interface ti_phy_top
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#endif
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