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cmagleby |
// ===========================================================================
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// File : ti_phy_top.test_top.v
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// Author : cmagleby
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// Date : Mon Dec 3 11:03:46 MST 2007
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// Project : TI PHY design
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//
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// Copyright (c) notice
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// This code adheres to the GNU public license
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// Please contact www.gutzlogic.com for details.
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// cmagleby@gutzlogic.com; cwinward@gutzlogic.com
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// ===========================================================================
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//
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cmagleby |
// $Id: ti_phy_top.test_top.v,v 1.3 2008-01-15 03:25:07 cmagleby Exp $
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cmagleby |
//
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// ===========================================================================
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//
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// $Log: not supported by cvs2svn $
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cmagleby |
// Revision 1.2 2007/12/05 23:00:33 cmagleby
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// add sram for real rtl
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//
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cmagleby |
// Revision 1.1.1.1 2007/12/05 18:37:07 cmagleby
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// importing tb files
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cmagleby |
//
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cmagleby |
//
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cmagleby |
// ===========================================================================
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// Function : This is the top level testbench file.
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//
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// ===========================================================================
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// ===========================================================================
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cmagleby |
`timescale 1 ns/100 ps
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cmagleby |
module ti_phy_top_test_top;
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cmagleby |
parameter simulation_cycle = 8;
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cmagleby |
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reg SystemClock;
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wire clk_50mhz;
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wire [1:0] PUSH_BUTTON;
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wire FPGA_RESET_n;
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cmagleby |
wire PERST_n;
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cmagleby |
wire rxclk;
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wire [15:0] rxdata16;
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wire [1:0] rxdatak16;
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wire rxvalid16;
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wire rxidle16;
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wire [2:0] rxstatus;
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wire phystatus;
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wire [7:0] LED;
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wire txclk;
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wire [15:0] txdata16;
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wire [1:0] txdatak16;
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wire txidle16;
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wire rxdet_loopb;
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wire txcomp;
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wire rxpol;
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wire phy_reset_n;
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wire [1:0] pwrdwn;
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wire [16:0] sram_addr;
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wire sram_adscn;
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wire sram_adspn;
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wire sram_advn;
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wire [3:0] sram_ben;
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wire [2:0] sram_ce;
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wire sram_clk;
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wire sram_gwn;
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wire sram_mode;
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wire sram_oen;
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wire sram_wen;
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wire sram_zz;
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wire [35:0] sram_data;
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assign rxclk = SystemClock;
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cmagleby |
assign PERST_n = FPGA_RESET_n;
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cmagleby |
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`ifdef SYNOPSYS_NTB
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ti_phy_top_test vshell(
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.SystemClock (SystemClock),
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.\ti_phy_top.clk_50mhz (clk_50mhz),
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.\ti_phy_top.PUSH_BUTTON (PUSH_BUTTON),
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.\ti_phy_top.FPGA_RESET_n (FPGA_RESET_n),
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cmagleby |
.\ti_phy_top.PERST_n (PERST_n),
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cmagleby |
.\ti_phy_top.rxclk (rxclk),
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.\ti_phy_top.rxdata16 (rxdata16),
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.\ti_phy_top.rxdatak16 (rxdatak16),
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.\ti_phy_top.rxvalid16 (rxvalid16),
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.\ti_phy_top.rxidle16 (rxidle16),
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.\ti_phy_top.rxstatus (rxstatus),
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.\ti_phy_top.phystatus (phystatus),
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.\ti_phy_top.sram_data (sram_data),
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.\ti_phy_top.LED (LED),
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.\ti_phy_top.txclk (txclk),
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.\ti_phy_top.txdata16 (txdata16),
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.\ti_phy_top.txdatak16 (txdatak16),
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.\ti_phy_top.txidle16 (txidle16),
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.\ti_phy_top.rxdet_loopb (rxdet_loopb),
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.\ti_phy_top.txcomp (txcomp),
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.\ti_phy_top.rxpol (rxpol),
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.\ti_phy_top.phy_reset_n (phy_reset_n),
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.\ti_phy_top.pwrdwn (pwrdwn),
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.\ti_phy_top.sram_addr (sram_addr),
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.\ti_phy_top.sram_adscn (sram_adscn),
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.\ti_phy_top.sram_adspn (sram_adspn),
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.\ti_phy_top.sram_advn (sram_advn),
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.\ti_phy_top.sram_ben (sram_ben),
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.\ti_phy_top.sram_ce (sram_ce),
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.\ti_phy_top.sram_clk (sram_clk),
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.\ti_phy_top.sram_gwn (sram_gwn),
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.\ti_phy_top.sram_mode (sram_mode),
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.\ti_phy_top.sram_oen (sram_oen),
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.\ti_phy_top.sram_wen (sram_wen),
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.\ti_phy_top.sram_zz (sram_zz)
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);
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`else
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vera_shell vshell(
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.SystemClock (SystemClock),
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.ti_phy_top_clk_50mhz (clk_50mhz),
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.ti_phy_top_PUSH_BUTTON (PUSH_BUTTON),
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cmagleby |
.ti_phy_top_FPGA_RESET_n (FPGA_RESET_),
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2 |
cmagleby |
.ti_phy_top_rxclk (rxclk),
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.ti_phy_top_rxdata16 (rxdata16),
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.ti_phy_top_rxdatak16 (rxdatak16),
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.ti_phy_top_rxvalid16 (rxvalid16),
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.ti_phy_top_rxidle16 (rxidle16),
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.ti_phy_top_rxstatus (rxstatus),
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.ti_phy_top_phystatus (phystatus),
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.ti_phy_top_sram_data (sram_data),
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.ti_phy_top_LED (LED),
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.ti_phy_top_txclk (txclk),
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.ti_phy_top_txdata16 (txdata16),
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.ti_phy_top_txdatak16 (txdatak16),
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.ti_phy_top_txidle16 (txidle16),
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.ti_phy_top_rxdet_loopb (rxdet_loopb),
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.ti_phy_top_txcomp (txcomp),
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.ti_phy_top_rxpol (rxpol),
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.ti_phy_top_phy_reset_n (phy_reset_n),
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.ti_phy_top_pwrdwn (pwrdwn),
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.ti_phy_top_sram_addr (sram_addr),
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.ti_phy_top_sram_adscn (sram_adscn),
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.ti_phy_top_sram_adspn (sram_adspn),
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.ti_phy_top_sram_advn (sram_advn),
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.ti_phy_top_sram_ben (sram_ben),
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.ti_phy_top_sram_ce (sram_ce),
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.ti_phy_top_sram_clk (sram_clk),
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.ti_phy_top_sram_gwn (sram_gwn),
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.ti_phy_top_sram_mode (sram_mode),
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.ti_phy_top_sram_oen (sram_oen),
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.ti_phy_top_sram_wen (sram_wen),
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.ti_phy_top_sram_zz (sram_zz)
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);
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`endif
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`ifdef emu
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/* DUT is in emulator, so not instantiated here */
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`else
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ti_phy_top dut(
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.clk_50mhz (clk_50mhz),
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.PUSH_BUTTON (PUSH_BUTTON),
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.FPGA_RESET_n (FPGA_RESET_n),
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7 |
cmagleby |
.PERST_n (PERST_n),
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2 |
cmagleby |
.rxclk (rxclk),
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.rxdata16 (rxdata16),
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.rxdatak16 (rxdatak16),
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.rxvalid16 (rxvalid16),
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.rxidle16 (rxidle16),
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.rxstatus (rxstatus),
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.phystatus (phystatus),
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.sram_data (sram_data),
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.LED (LED),
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.txclk (txclk),
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.txdata16 (txdata16),
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.txdatak16 (txdatak16),
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.txidle16 (txidle16),
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.rxdet_loopb (rxdet_loopb),
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.txcomp (txcomp),
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.rxpol (rxpol),
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.phy_reset_n (phy_reset_n),
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.pwrdwn (pwrdwn),
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.sram_addr (sram_addr),
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.sram_adscn (sram_adscn),
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.sram_adspn (sram_adspn),
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.sram_advn (sram_advn),
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.sram_ben (sram_ben),
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.sram_ce (sram_ce),
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.sram_clk (sram_clk),
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.sram_gwn (sram_gwn),
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.sram_mode (sram_mode),
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.sram_oen (sram_oen),
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.sram_wen (sram_wen),
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.sram_zz (sram_zz)
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);
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`endif
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always @ (posedge SystemClock) begin
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if (|rxdatak16)
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$display($time,":datak symbol");
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end
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reg set_once;
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//simulation short ts1 sets
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`ifdef REAL_RTL
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always @ (posedge SystemClock) begin
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if (dut.phy_layer_top_inst.send_ts1 & ~set_once) begin
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force dut.phy_layer_top_inst.tx_alignment_32_inst.ts_1024_count = 10'b1111000000;
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set_once <= #1 1'b1;
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end
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else begin
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release dut.phy_layer_top_inst.tx_alignment_32_inst.ts_1024_count;
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if (dut.phy_layer_top_inst.ltssm_32bit_inst.start_link_training_pm) begin
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set_once <= #1 1'b0;
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end
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end
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end // always @ (posedge ti_phy_top_inst.clk_125mhz)
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4 |
cmagleby |
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/* -----\/----- EXCLUDED -----\/-----
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idt71v25761s200 AUTO_TEMPLATE (
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.D (sram_data[31:0]),
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.DP (sram_data[35:32]),
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// Inputs
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.A (sram_addr),
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.oe_ (sram_oen),
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.ce_ (sram_ce[0]),
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.cs0 (sram_ce[1]),
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.cs1_ (sram_ce[2]),
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.lbo_ (sram_mode),
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.gw_ (sram_gwn),
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.bwe_ (sram_wen),
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.bw4_ (sram_ben[3]),
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.bw3_ (sram_ben[2]),
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.bw2_ (sram_ben[1]),
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.bw1_ (sram_ben[0]),
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.adsp_(sram_adspn),
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.adsc_(sram_adscn),
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.adv_ (sram_advn),
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.clk (sram_clk));
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-----/\----- EXCLUDED -----/\----- */
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idt71v25761s200 SRAM_MODEL_inst (/*AUTOINST*/
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// Inouts
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.D (sram_data[31:0]), // Templated
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.DP (sram_data[35:32]), // Templated
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// Inputs
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.A (sram_addr), // Templated
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.oe_ (sram_oen), // Templated
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.ce_ (sram_ce[0]), // Templated
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.cs0 (sram_ce[1]), // Templated
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.cs1_ (sram_ce[2]), // Templated
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.lbo_ (sram_mode), // Templated
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.gw_ (sram_gwn), // Templated
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.bwe_ (sram_wen), // Templated
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.bw4_ (sram_ben[3]), // Templated
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.bw3_ (sram_ben[2]), // Templated
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.bw2_ (sram_ben[1]), // Templated
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.bw1_ (sram_ben[0]), // Templated
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.adsp_(sram_adspn), // Templated
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.adsc_(sram_adscn), // Templated
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.adv_ (sram_advn), // Templated
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.clk (sram_clk)); // Templated
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2 |
cmagleby |
`endif
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initial begin
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//****************************************************************************************
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//force scramble bypass until the tb can scramble and de-scramble data.
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//force dut.phy_layer_top_inst.make_rxdata_path16.scramble16_inst.scram_bypass = 2'b11;
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//force dut.phy_layer_top_inst.make_tx_data_path16.scramble16_inst.scram_bypass = 2'b11;
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//****************************************************************************************
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set_once = 0;
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SystemClock = 0;
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forever begin
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#(simulation_cycle/2)
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SystemClock = ~SystemClock;
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end
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4 |
cmagleby |
end // initial begin
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2 |
cmagleby |
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| 277 |
4 |
cmagleby |
`ifdef REAL_RTL
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2 |
cmagleby |
initial begin
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$fsdbDumpfile("vera_test.fsdb");
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$fsdbDumpvars(dut);
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end
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| 282 |
4 |
cmagleby |
`endif
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2 |
cmagleby |
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endmodule
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