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[/] [pdp1/] [trunk/] [rtl/] [vhdl/] [pdp1rotshift.vhd] - Blame information for rev 14

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1 3 yannv
----------------------------------------------------------------------------------
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-- Company: 
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-- Engineer: 
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-- 
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-- Create Date:    15:39:56 08/10/2009 
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-- Design Name: 
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-- Module Name:    pdp1rotshift - Behavioral 
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-- Project Name: 
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-- Target Devices: 
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-- Tool versions: 
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-- Description: 
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--
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-- Dependencies: 
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--
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-- Revision: 
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-- Revision 0.01 - File Created
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-- Additional Comments: 
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--
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----------------------------------------------------------------------------------
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library IEEE;
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use IEEE.STD_LOGIC_1164.ALL;
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use IEEE.numeric_std.ALL;
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entity pdp1rotshift is
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    Port ( ac : in  STD_LOGIC_VECTOR (0 to 17);
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           io : in  STD_LOGIC_VECTOR (0 to 17);
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           right : in  STD_LOGIC;                               -- '0' for left, '1' for right
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           shift : in  STD_LOGIC;                       -- '1' for shift, '0' for rotate
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           words : in  STD_LOGIC_VECTOR (0 to 1);
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           acout : out  STD_LOGIC_VECTOR (0 to 17);
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           ioout : out  STD_LOGIC_VECTOR (0 to 17));
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end pdp1rotshift;
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architecture Behavioral of pdp1rotshift is
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        signal input, output: std_logic_vector(0 to 35);
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        signal word: std_logic_vector(0 to 17);
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        constant use_readable_code: boolean := true;
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begin
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        cond_gen: if use_readable_code generate
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                with words select
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                        input <= AC&AC when "01",
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                                                IO&IO when "10",
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                                                AC&IO when "11",
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                                                (others=>'-') when others;
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                output <= std_logic_vector(unsigned(input) rol 1) when right='0' and shift='0' else
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                                         std_logic_vector(unsigned(input) sll 1) when right='0' and shift='1' else
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                                         std_logic_vector(unsigned(input) ror 1) when right='1' and shift='0' else
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                                         std_logic_vector(unsigned(input) srl 1) when right='1' and shift='1' else
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                                         (others=>'-');
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                word <= output(0 to 17) when right='1' else output(18 to 35);
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                with words select
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                        acout <= word when "01",
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                                                output(0 to 17) when "11",
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                                                ac when others;
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                with words select
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                        ioout <= word when "10",
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                                                output(18 to 35) when "11",
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                                                io when others;
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        end generate;
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        cond_explicit_rtl: if not use_readable_code generate
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                acout(0) <= ac(0) when words(1)='0' else           -- not working on AC
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                                                                        ac(1) when right='0' else                                        -- shift/rot left
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                                                                        '0' when shift='1' else                                          -- shift right
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                                                                        ac(17) when words(0)='0' else             -- rotate ac right
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                                                                        io(17) when words(0)='1' else            -- rotate ac&io right
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                                                                        '-';
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                acout(1 to 16) <= ac(1 to 16) when words(1)='0' else     -- not working on AC
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                                                                                                ac(2 to 17) when right='0' else                          -- left
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                                                                                                ac(0 to 15) when right='1' else                          -- right
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                                                                                                (others=>'-');
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                acout(17) <= ac(17) when words(1)='0' else               -- not working on ac
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                                                                        ac(16) when right='1' else                                      -- shift/rot right
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                                                                        io(0) when words(0)='1' else                      -- shift/rot left ac&io
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                                                                        '0' when shift='1' else                                                  -- shift ac left
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                                                                        ac(0) when shift='0' else                                 -- rotate ac left
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                                                                        '-';
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                ioout(0) <= io(0) when words(0)='0' else                            -- not working on IO
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                                                                io(1) when right='0' else                                                        -- left
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                                                                ac(17) when words(1)='1' else                   -- ac&io right
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                                                                '0' when shift='1' else                                                          -- shift io right
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                                                                io(17) when shift='0' else                                               -- rotate io right
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                                                                '-';
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                ioout(1 to 16) <= io(1 to 16) when words(0)='0' else
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                                                                                        io(2 to 17) when right='0' else
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                                                                                        io(0 to 15) when right='1' else
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                                                                                        (others=>'-');
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                ioout(17) <= io(17) when words(0)='0' else
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                                                                        io(16) when right='1' else
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                                                                        '0' when shift='1' else
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                                                                        ac(0) when words(1)='1' else
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                                                                        io(0) when words(1)='0' else
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                                                                        '-';
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        end generate;
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end Behavioral;
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