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[/] [pdp8/] [trunk/] [de0_nano/] [pdp8_top.vhd] - Blame information for rev 5

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--!
2
--! DE0-Nano PDP-8 Processor
3
--!
4
--! \brief
5
--!      PDP-8 implementation for the DE0-Nano board
6
--!
7
--! \details
8
--!
9
--! \file
10
--!      pdp8_top.vhd
11
--!
12
--! \author
13
--!    Joe Manojlovich - joe.manojlovich (at) gmail (dot) com
14
--!
15
--------------------------------------------------------------------
16
--
17
--  Copyright (C) 2012 Joe Manojlovich
18
--
19
-- This source file may be used and distributed without
20
-- restriction provided that this copyright statement is not
21
-- removed from the file and that any derivative work contains
22
-- the original copyright notice and the associated disclaimer.
23
--
24
-- This source file is free software; you can redistribute it
25
-- and/or modify it under the terms of the GNU Lesser General
26
-- Public License as published by the Free Software Foundation;
27
-- version 2.1 of the License.
28
--
29
-- This source is distributed in the hope that it will be
30
-- useful, but WITHOUT ANY WARRANTY; without even the implied
31
-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
32
-- PURPOSE. See the GNU Lesser General Public License for more
33
-- details.
34
--
35
-- You should have received a copy of the GNU Lesser General
36
-- Public License along with this source; if not, download it
37
-- from http://www.gnu.org/licenses/lgpl.txt
38
--
39
--------------------------------------------------------------------
40
--
41
-- Comments are formatted for doxygen
42
--
43
 
44
LIBRARY ieee;
45
USE ieee.std_logic_1164.all;
46
USE ieee.std_logic_arith.all;
47
USE ieee.std_logic_unsigned.all;
48
use ieee.numeric_std;
49
use work.uart_types.all;                        --! UART Types
50
use work.dk8e_types.all;                        --! DK8E Types
51
use work.kc8e_types.all;                        --! KC8E Types
52
use work.kl8e_types.all;                        --! KL8E Types
53
use work.rk8e_types.all;                        --! RK8E Types
54
use work.rk05_types.all;                        --! RK05 Types
55
use work.ls8e_types.all;                        --! LS8E Types
56
use work.pr8e_types.all;                        --! PR8E Types
57
use work.cpu_types.all;                         --! CPU Types
58
use work.sd_types.all;                          --! SD Types
59
use work.sdspi_types.all;                       --! SPI Types
60
use work.oct_7seg;
61
 
62
ENTITY pdp8_top IS
63
  generic(
64
    invert_reset : std_logic := '0' -- 0 : not invert, 1 invert
65
    );
66
 
67
  PORT (
68
    SW : IN STD_LOGIC_VECTOR(3 DOWNTO 0) := (others => 'Z');     --! Toggle switches
69
    KEY : IN STD_LOGIC_VECTOR(1 DOWNTO 0) := (others => 'Z');    --! Push buttons
70
    CLOCK_50 : IN STD_LOGIC;                                     --! Input clock
71
    LED : OUT STD_LOGIC_VECTOR(7 DOWNTO 0) := (others => 'Z');   --! Output green LEDs
72
 
73
         TTY1_TXD : OUT STD_LOGIC;                                    --! UART send line
74
         TTY1_RXD : IN STD_LOGIC;                                     --! UART receive line
75
         TTY2_TXD : OUT STD_LOGIC;                                    --! UART send line
76
         TTY2_RXD : IN STD_LOGIC;                                     --! UART receive line      
77
         LPR_TXD : OUT STD_LOGIC;                                     --! LPR send line
78
         LPR_RXD : IN STD_LOGIC;                                      --! LPR receive line
79
         LPR_CTS : IN STD_LOGIC;
80
         LPR_RTS : OUT STD_LOGIC;
81
         PTR_TXD : OUT STD_LOGIC;
82
         PTR_RXD : IN STD_LOGIC;
83
         PTR_CTS : IN STD_LOGIC;
84
         PTR_RTS : OUT STD_LOGIC;
85
         USB_CLK_12MHZ : OUT STD_LOGIC; -- FIXME
86
         RESET : OUT STD_LOGIC;
87
         fpMISO : IN STD_LOGIC;
88
         fpMOSI : OUT STD_LOGIC;
89
         fpFS : OUT STD_LOGIC;
90
         fpSCLK : OUT STD_LOGIC;
91
 
92
         swLOCK : IN STD_LOGIC;
93
         swCONT : IN STD_LOGIC;
94
         swBOOT : IN STD_LOGIC;
95
         swEXAM : IN STD_LOGIC;
96
         swLDADDR : IN STD_LOGIC;
97
         swHALT : IN STD_LOGIC;
98
         swLDEXTD : IN STD_LOGIC;
99
         swSTEP : IN STD_LOGIC;
100
         swD0 : IN STD_LOGIC;
101
         swDEP : IN STD_LOGIC;
102
         swD1 : IN STD_LOGIC;
103
         swROT0 : IN STD_LOGIC;
104
         swD2 : IN STD_LOGIC;
105
         swROT1 : IN STD_LOGIC;
106
         swD3 : IN STD_LOGIC;
107
         swROT2 : IN STD_LOGIC;
108
         swD4 : IN STD_LOGIC;
109
         swROT3 : IN STD_LOGIC;
110
         swD5 : IN STD_LOGIC;
111
         swROT4 : IN STD_LOGIC;
112
         swD6 : IN STD_LOGIC;
113
         swROT5 : IN STD_LOGIC;
114
         swD7 : IN STD_LOGIC;
115
         swROT6 : IN STD_LOGIC;
116
         swROT7 : IN STD_LOGIC;
117
         sdCS : OUT STD_LOGIC; --! SD card chip select
118
         swD8 : IN STD_LOGIC;
119
         sdCLK : OUT STD_LOGIC; --! SD card clock
120
         swD9 : IN STD_LOGIC;
121
         sdDI : OUT STD_LOGIC; --! SD card master out slave in
122
         swD10 : IN STD_LOGIC;
123
         sdDO : IN STD_LOGIC; --! SD card master in slave out
124
         swD11 : IN STD_LOGIC;
125
         sdCD: IN STD_LOGIC;
126
         swCLEAR : IN STD_LOGIC;
127
         swWP : IN STD_LOGIC
128
 
129
    );
130
END pdp8_top;
131
 
132
 architecture rtl of pdp8_top is
133
  signal rk8eSTAT : rk8eSTAT_t;
134
  signal swCNTL : swCNTL_t := (others => '0');                       --! Front Panel Control Switches
135
  signal swROT : swROT_t := dispIR;                                  --! Front panel rotator switch
136
  signal swOPT  : swOPT_t;                                           --! PDP-8 options\
137
  signal swDATA : swDATA_t;             --! Front panel switches  
138
  signal ledDATA : data_t;
139
 
140
  signal dly: std_logic := '0';         --! Delay used for reset logic
141
  signal rst: std_logic := '0';         --! Internal reset line
142
  signal int_reset : std_logic;         --! Initial reset line
143
  signal rst_out : std_logic;           --! Reset line output to PDP-8
144
 
145
  constant max_count : natural := 24000;
146
  signal op : std_logic;
147
 
148
  type display_type is (S0, S1, S2, S3, S4, S5);
149
  signal state: display_type := S0;
150
  signal i : integer range 0 to 32 := 0;
151
  --signal i : std_logic_vector(7 downto 0) := (others => '0');
152
  signal data7 : std_logic_vector(31 downto 0); -- := X"fa00fa00"; -- (others => '0');
153
 
154
 
155
begin
156
 
157
  swOPT.KE8       <= '1';
158
  swOPT.KM8E      <= '1';
159
  swOPT.TSD       <= '1';
160
  swOPT.STARTUP   <= '1'; -- Setting the 'STARTUP' bit will cause the PDP8 to boot
161
  -- to the address in the switch register
162
 
163
  int_reset <= '0';
164
 
165
  ----------------------------------------------------------------------------
166
  --  RESET signal generator.
167
  ----------------------------------------------------------------------------
168
  process(CLOCK_50)
169
  begin
170
    if(rising_edge(CLOCK_50)) then
171
      dly <= ( not(int_reset) and     dly  and not(rst) )
172
             or ( not(int_reset) and not(dly) and     rst  );
173
      rst <= ( not(int_reset) and not(dly) and not(rst) );
174
    end if;
175
  end process;
176
 
177
  rst_out <= rst xor invert_reset ;
178
 
179
  --
180
  -- Front Panel Data Switches
181
  --
182
 
183
  swDATA          <= o"0023";
184
  --swDATA          <= o"7400";   
185
 
186
    compteur : process(CLOCK_50, rst_out)
187
        variable count : natural range 0 to max_count := 0;
188
    begin
189
                        if rising_edge(CLOCK_50) then
190
            if count < max_count/2 then
191
                op    <='1';
192
                count := count + 1;
193
            elsif count < max_count then
194
                op    <='0';
195
                count := count + 1;
196
            else
197
                count := 0;
198
                op    <='1';
199
            end if;
200
        end if;
201
    end process compteur;
202
 
203
                --      LED(6) <= op;
204
 
205
  ----------------------------------------------------------------------------
206
  -- Display toggle switch (stand in for rotator switch)
207
  ---------------------------------------------------------------------------  
208
  toggle_switch : process(CLOCK_50)
209
  begin
210
    if rising_edge(KEY(0)) then
211
      swROT <= swROT + 1;
212
    end if;
213
  end process toggle_switch;
214
 
215
 
216
  display : process(CLOCK_50)
217
  begin
218
 
219
        if rising_edge(CLOCK_50) then
220
 
221
                if op = '1'
222
                then
223
                        state <= S1;
224
                        i <= 0;
225
                        RESET <= '1';
226
                end if;
227
 
228
--              if state = S0
229
--              then
230
--                      LED(1) <= '1';
231
--                      LED(2) <= '1';
232
--                      LED(3) <= '1';
233
--                      LED(4) <= '1';
234
--                      LED(5) <= '1';
235
--              end if;
236
 
237
                if state = S1
238
                then
239
                        fpFS <= '0';
240
                        state <= S2;
241
 
242
--                      LED(1) <= '1';
243
--                      LED(2) <= '0';
244
--                      LED(3) <= '0';
245
--                      LED(4) <= '0';
246
--                      LED(5) <= '0';
247
                end if;
248
 
249
                if state = S2
250
                then
251
--                      LED(1) <= '0';
252
--                      LED(2) <= '1';
253
--                      LED(3) <= '0';
254
--                      LED(4) <= '0';
255
--                      LED(5) <= '0';
256
 
257
                        if i = 32
258
                        then
259
                                state <= S5;
260
                        else
261
                                fpSCLK <= '0';
262
                                state <= S3;
263
                        end if;
264
                end if;
265
 
266
                if state = S3
267
                then
268
                        fpMOSI <= data7(31 - i);
269
                        i <= i + 1;
270
                        state <= S4;
271
 
272
--                      LED(1) <= '0';
273
--                      LED(2) <= '0';
274
--                      LED(3) <= '1';
275
--                      LED(4) <= '0';
276
--                      LED(5) <= '0';
277
                end if;
278
 
279
                if state = S4
280
                then
281
                        fpSCLK <= '1';
282
                        state <= S2;
283
 
284
--                      LED(1) <= '0';
285
--                      LED(2) <= '0';
286
--                      LED(3) <= '0';
287
--                      LED(4) <= '1';
288
--                      LED(5) <= '0';
289
                end if;
290
 
291
                if state = S5
292
                then
293
                        fpFS <= '1';
294
                        state <= S0;
295
 
296
--                      LED(1) <= '0';
297
--                      LED(2) <= '0';
298
--                      LED(3) <= '0';
299
--                      LED(4) <= '0';
300
--                      LED(5) <= '1';
301
                end if;
302
        end if;
303
 
304
end process display;
305
 
306
  ----------------------------------------------------------------------------
307
  -- PDP8 Processor
308
  ---------------------------------------------------------------------------    
309
  iPDP8 : entity work.ePDP8 (rtl) port map (
310
    -- System
311
    clk      => CLOCK_50,                   --! 50 MHz Clock
312
    rst      => rst_out,                    --! Reset Button
313
    -- CPU Configuration
314
    swCPU    => swPDP8A,                    --! CPU Configured to emulate PDP8A
315
    swOPT    => swOPT,                      --! Enable Options
316
    -- Real Time Clock Configuration
317
    swRTC    => clkDK8EC2,                  --! RTC 50 Hz interrupt
318
    -- TTY1 Interfaces
319
    tty1BR   => uartBR9600,                 --! TTY1 is 9600 Baud
320
    tty1HS   => uartHSnone,                 --! TTY1 has no flow control
321
    tty1CTS  => '1',                        --! TTY1 doesn't need CTS
322
    tty1RTS  => open,                       --! TTY1 doesn't need RTS
323
    tty1RXD  => TTY1_RXD,                   --! TTY1 RXD (to RS-232 interface)
324
    tty1TXD  => TTY1_TXD,                   --! TTY1 TXD (to RS-232 interface)
325
    -- TTY2 Interfaces
326
    tty2BR   => uartBR9600,                 --! TTY2 is 9600 Baud
327
    tty2HS   => uartHSnone,                 --! TTY2 has no flow control
328
    tty2CTS  => '1',                        --! TTY2 doesn't need CTS
329
    tty2RTS  => open,                       --! TTY2 doesn't need RTS
330
    tty2RXD  => '1',                        --! TTY2 RXD (tied off)
331
    tty2TXD  => open,                       --! TTY2 TXD (tied off)
332
    -- LPR Interface
333
    lprBR    => uartBR9600,                 --! LPR is 9600 Baud
334
    lprHS    => uartHSnone,                 --! LPR has no flow control
335
    lprDTR   => '1',                        --! LPR doesn't need DTR
336
    lprDSR   => open,                       --! LPR doesn't need DSR
337
    lprRXD   => '1',                        --! LPR RXD (tied off)
338
    lprTXD   => open,                       --! LPR TXD (tied off)
339
    -- Paper Tape Reader Interface
340
    ptrBR    => uartBR9600,                 --! PTR is 9600 Baud
341
    ptrHS    => uartHSnone,                 --! PTR has no flow control
342
    ptrCTS   => '1',                        --! PTR doesn't need CTS
343
    ptrRTS   => open,                       --! PTR doesn't need RTS
344
    ptrRXD   => '1',                        --! PTR RXD (tied off)
345
    ptrTXD   => open,                       --! PTR TXD (tied off)
346
    -- Secure Digital Disk Interface
347
    sdCD     => '0',                        --! SD Card Detect
348
    sdWP     => '0',                        --! SD Write Protect
349
    sdMISO   => sdDO,                       --! SD Data In
350
    sdMOSI   => sdDI,                       --! SD Data Out
351
    sdSCLK   => sdCLK,                      --! SD Clock
352
    sdCS     => sdCS,                       --! SD Chip Select
353
    -- Status
354
    rk8eSTAT => rk8eSTAT,                   --! Disk Status (Ignore)
355
    -- Switches and LEDS
356
    swROT    => swROT,                      --! Data LEDS display PC
357
    swDATA   => swDATA,                     --! RK8E Boot Loader Address
358
    swCNTL   => swCNTL,                     --! Switches
359
    ledRUN => LED(7),                       --! Run LED
360
    ledDATA => ledDATA,                        --! Data output register
361
    ledADDR => open                         --! Address output register
362
    );
363
 
364
         --data7(7 downto 0) <= rk8eSTAT.sdSTAT.state;
365
         --data7(15 downto 8) <= rk8eSTAT.sdSTAT.err;
366
         --data7(23 downto 16) <= rk8eSTAT.sdSTAT.val;
367
         --data7(31 downto 24) <= rk8eSTAT.sdSTAT.debug;
368
 
369
--       digit1 : entity hex_7seg port map (
370
--              CLOCK_50 => CLOCK_50,
371
--              hex_digit => rk8eSTAT.sdSTAT.debug(4 to 7),
372
--              seg => data7(13 downto 7)
373
--       );
374
--       
375
--       digit2 : entity hex_7seg port map (
376
--              CLOCK_50 => CLOCK_50,
377
--              hex_digit => rk8eSTAT.sdSTAT.debug(0 to 3),
378
--              seg => data7(6 downto 0)
379
--       );
380
--       
381
--       digit3 : entity hex_7seg port map (
382
--              CLOCK_50 => CLOCK_50,
383
--              hex_digit => rk8eSTAT.sdSTAT.err(4 to 7),
384
--              seg => data7(20 downto 14)
385
--       );
386
--       
387
--       digit4 : entity hex_7seg port map (
388
--              CLOCK_50 => CLOCK_50,
389
--              hex_digit => rk8eSTAT.sdSTAT.err(0 to 3),
390
--              seg => data7(27 downto 21)
391
--       );
392
 
393
 
394
--       digit3 : entity oct_7seg port map (
395
--              CLOCK_50 => CLOCK_50,
396
--              oct_digit => ledDATA(3 to 5),
397
--              seg => data7(13 downto 7)
398
--       );
399
--
400
--       digit4 : entity oct_7seg port map (
401
--              CLOCK_50 => CLOCK_50,
402
--              oct_digit => ledDATA(0 to 2),
403
--              seg => data7(6 downto 0)
404
--       );              
405
 
406
         digit1 : entity oct_7seg port map (
407
                CLOCK_50 => CLOCK_50,
408
                oct_digit => ledDATA(9 to 11),
409
                seg => data7(27 downto 21)
410
         );
411
 
412
         digit2 : entity oct_7seg port map (
413
                CLOCK_50 => CLOCK_50,
414
                oct_digit => ledDATA(6 to 8),
415
                seg => data7(20 downto 14)
416
         );
417
 
418
         digit3 : entity oct_7seg port map (
419
                CLOCK_50 => CLOCK_50,
420
                oct_digit => ledDATA(3 to 5),
421
                seg => data7(13 downto 7)
422
         );
423
 
424
         digit4 : entity oct_7seg port map (
425
                CLOCK_50 => CLOCK_50,
426
                oct_digit => ledDATA(0 to 2),
427
                seg => data7(6 downto 0)
428
         );
429
 
430
end rtl;

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