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--!

--! PDP-8 Processor

--!

--! \brief

--!      CPU Processor

--!

--! \details

--!      I hope you like state machines because this is implemented as one big

--!      state machine.

--!

--! \file

--!      cpu.vhd

--!

--! \author

--!      Rob Doyle - doyle (at) cox (dot) net

--!

--------------------------------------------------------------------------------

--

--  Copyright (C) 2009, 2010, 2011, 2012 Rob Doyle

--

-- This source file may be used and distributed without restriction provided

-- that this copyright statement is not removed from the file and that any

-- derivative work contains the original copyright notice and the associated

-- disclaimer.

--

-- This source file is free software; you can redistribute it and/or modify it

-- under the terms of the GNU Lesser General Public License as published by the

-- Free Software Foundation; version 2.1 of the License.

--

-- This source is distributed in the hope that it will be useful, but WITHOUT

-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS

-- FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public License for more

-- details.

--

-- You should have received a copy of the GNU Lesser General Public License

-- along with this source; if not, download it from

-- http://www.gnu.org/licenses/lgpl.txt

--

--------------------------------------------------------------------------------

--

-- Comments are formatted for doxygen

--

library ieee;                                   --! IEEE Library

use ieee.std_logic_1164.all;                    --! IEEE 1164

use ieee.numeric_std.all;                       --! IEEE Numeric Standard

use work.cpu_types.all;

-- synthesis translate_off

use std.textio.all;                             --! std textio

use ieee.std_logic_textio.all;                  --! IEEE std_logic_textio

-- synthesis translate_on

--

--! CPU Entity

--

entity eCPU is port (

    sys     : in  sys_t;                        --! Clock/Reset

    swCPU   : in  swCPU_t;                      --! CPU Configuration

    swOPT   : in  swOPT_t;                      --! Options Configuration

    swDATA  : in  swDATA_t;                     --! Data Switch Inputs

    swCNTL  : in  swCNTL_t;                     --! Control Switch Inputs

    dev     : in  dev_t;                        --! Device Output

    cpu     : out cpu_t                         --! CPU Output

);

end eCPU;

--

--! CPU RTL

--

architecture rtl of eCPU is

    --

    -- Registers

    --

    signal LAC      : ldata_t;                  --! Link and Accumulator

    alias  L        : std_logic is LAC (0);     --! Link Bit

    alias  AC       : data_t is LAC(1 to 12);   --! Accumulator

    signal IR       : data_t;                   --! Instruction Register

    signal PC       : addr_t;                   --! Program Counter

    signal MA       : addr_t;                   --! Memory Address Register

    signal MB       : data_t;                   --! Memory Buffer (output)

    signal MD       : data_t;                   --! Memory Data Register (input)

    signal MQ       : data_t;                   --! MQ Register

    signal MQA      : data_t;                   --! MQA Register

    signal SC       : sc_t;                     --! SC Register

    signal SP1      : addr_t;                   --! Stack Pointer

    signal SP2      : addr_t;                   --! Stack Pointer

    signal SR       : data_t;                   --! Switch Register

    --

    -- Register Operation

    --

    signal acOP     : acOP_t;                   --! AC operation

    signal pcOP     : pcOP_t;                   --! PC operation

    signal irOP     : irOP_t;                   --! IR operation

    signal maOP     : maOP_t;                   --! MA operation

    signal mbOP     : mbOP_t;                   --! MB operation

    signal mqOP     : mqOP_t;                   --! MQ operation

    signal mqaOP    : mqaOP_t;                  --! MQA operation

    signal scOP     : scOP_t;                   --! SC operation

    signal sp1OP    : spOP_t;                   --! SP1 operation

    signal sp2OP    : spOP_t;                   --! SP2 operation

    signal srOP     : srOP_t;                   --! SR operation

    --

    -- Memory Extension Control Registers

    --

    signal IB       : field_t;                  --! Instruction Buffer

    signal INF      : field_t;                  --! Instruction Field

    signal DF       : field_t;                  --! Data Field

    signal SF       : sf_t;                     --! Save Field

    --

    -- Memory Extension Control Register Operations

    --

    signal ibOP     : ibOP_t;                   --! IB operation

    signal ifOP     : ifOP_t;                   --! IF operation

    signal dfOP     : dfOP_t;                   --! DF operation

    signal sfOP     : sfOP_t;                   --! SF operation

    signal IRQ      : std_logic;                --! IRQ Flag

    --

    -- KM8x Time Share Registers

    --

    signal UB       : std_logic;                --! User Buffer Flag

    signal UF       : std_logic;                --! User Flag

    --

    -- KM8x Time Share Register Operations

    --

    signal ubOP     : ubOP_t;                   --! User Buffer operation

    signal ufOP     : ufOP_t;                   --! USER Flag operation

    --

    -- BTSTRP:

    --

    signal BTSTRP   : std_logic;                --! BTSTRP Register

    signal btstrpOP : btstrpOP_t;               --! BTSTRP operation

    --

    -- CTRLFF:

    -- The Control Panel Register (CTRLFF), is set when the CPREQ is granted.

    -- CTRLFF prevents further CPREQs from being granted, bypasses the

    -- interrupt enable system and redefines several of the internal control

    -- instructions.  As long as the CTRLFF is set, LXPAR is used for all

    -- instruction, direct data and indirect pointer references.  Also, while

    -- CTRLFF is set, the INTGNT line is held inactive but the Interrupt Grant

    -- Flip Flop is not cleared.  IOTs executed while CTRLFF is set do not clear

    -- the Interrupt grant flip flop.

    --

    signal CTRLFF   : std_logic;                --! CTRLFF

    signal ctrlffOP : ctrlffOP_t;               --! CTRLFF operation

    --

    -- EAE:

    -- EAE Long Operations

    --

    signal EAE      : eae_t;                    --! EAE Register

    signal eaeOP    : eaeOP_t;                  --! EAE operation

    --

    -- EMODE:

    -- The EMODE bit is set at reset and is set by the SWAB and cleared by the

    -- SWBA instructions.  This enables EAE Mode A and EAE Mode B instructions.

    --

    signal EMODE    : std_logic;                --! EAE Mode

    signal emodeOP  : emodeOP_t;                --! EAE Mode operation

    --

    -- FZ:

    -- The Force Zero Flag (FZ) is used to implement Extended memory operations

    -- for Panel Mode instructions.  When set, forces control panel instruction

    -- field access to field zero.  Indirect data accesses are not affected.

    --

    signal FZ       : std_logic;                --! Force Zero

    signal fzOP     : fzOP_t;                   --! FZ operation

    --

    -- HLTTRP:

    -- The HLTTRP flip-flop allows the cpu to single step through code.

    -- The HLTTRP flip-flop is set by a HLT instruction.

    --

    signal HLTTRP   : std_logic;                --! HLTTRP Register

    signal hlttrpOP : hlttrpOP_t;               --! HLTTRP operation

    --

    -- GTF:

    --

    signal GTF      : std_logic;                --! Greater than Flag

    signal gtfOP    : gtfOP_t;                  --! GTF operation

    --

    --! ID:

    --! The ION Delay (ID) register delays the effect of the ION

    --! instruction until the instruction after the ION

    --! instruction has executed.   This will allow a return

    --! from interrupt to be executed before the next interrupt

    --! request is serviced.

    --

    signal ID       : std_logic;                --! ION Delay Flip-flop

    signal idOP     : idOP_t;                   --! ION Delay Operation

    --

    -- IE:

    -- The Interrupt Enable Register (IE) enables and disables interrupts.

    --

    signal IE       : std_logic;                --! Interrupt Enable

    signal ieOP     : ieOP_t;                   --! IE operation

    --

    -- II:

    -- The Interrupt Inhibit (II) Register is set whenever there is an

    -- instruction executed that could change the Instruction Field.  These

    -- include CIF, CDI, RMF, RTF, CAF, CUF, SUF.  The II Register is

    -- cleared when the next JMP, JMS, RTN1, or RTN2 instruction is executed.

    -- This prevents an interrupt from occuring between the CIF (or like)

    -- instruction and the return (or like) instruction.

    --

    signal II       : std_logic;                -- Interrupt Inhibit Register

    signal iiOP     : iiOP_t;                   -- Interrupt Inhibit Operation

    --

    -- PDF:

    -- The Panel Data Flag (PDF) is used to contol whether indirectly addressed

    -- data references by Control Panel AND, TAD, ISZ or DCA instructions

    -- reference panel memory or main memory.  If PDF is set, this flag causes

    -- indirect references from control panel memory to address control panel

    -- memory by asserting LXPAR.  If PDF is cleared, this flag causes indirect

    -- references from control panel memory to address main memory by asserting

    -- LXMAR.  The PDF is cleared unconditionally whenever the panel mode is

    -- entered for any reason.  It is also cleared by the Clear Panel Data

    -- (CPD) instruction.  The PDF is set by the Set Panel Data (SPD)

    -- instruction. The state of the Panel Data flag is ignored when not

    -- operating in panel mode.

    --

    signal PDF      : std_logic;                --! Panel Data Flag

    signal pdfOP    : pdfOP_t;                  --! PDF operation

    --

    -- PEX:

    -- The Panel Exit Delay (PEX) Register is set by the PEX instruction.

    -- When a JMP, JMS, RET1, or RET2 instruction is executed with the PEX

    -- Register set, the CPU will exit panel mode.  The PEX Register is

    -- cleared by the JMP, JMS, RET1, or RET2 instruction.

    --

    signal PEX      : std_logic;                -- PEX Register

    signal pexOP    : pexOP_t;                  -- PEX Operation

    --

    -- PNLTRP:

    -- A Panel Trap is one of the many ways to enter panel mode.  The Panel Trap

    -- Register (PNLTRP) is set by any of the PR0, PR1, PR2, PR3 instructions.

    -- The PNLTRP flag can be examined and cleared by the PRS instruction.

    --

    signal PNLTRP   : std_logic;                --! PNLTRP Flag

    signal pnltrpOP : pnltrpOP_t;               --! PNLTRP operation

    --

    -- PRWON:

    -- The Power-On Trap Register (PWRTRP) is set when STRTUP is negated during

    -- RESET, The Power-On Register (PWRTRP) is reset by a PRS or PEX

    -- instruction.

    --

    signal PWRTRP   : std_logic;                --! PWRTRP Register

    signal pwrtrpOP : pwrtrpOP_t;               --! PWRTRP operation

    --

    -- USRTRP:

    -- User Mode Trap.

    --

    signal USRTRP   : std_logic;                --! USR Interrupt

    signal usrtrpOP : usrtrpOP_t;               --! USR Interrupt operation

    --

    -- XMA

    --

    signal XMA      : field_t;                  --! XMA Register

    signal xmaOP    : xmaOP_t;                  --! XMA operation

    --

    -- Bus Control Signals

    --

    signal busb     : busOP_t;                  --! Bus Operation output

    signal busOP    : busOP_t;                  --! Bus Operation input

    signal ioclrb   : std_logic;                --! IOCLR register output

    signal ioclrOP  : std_logic;                --! IOCLR register input

    signal wrb      : std_logic;                --! WR signal register input

    signal wrOP     : std_logic;                --! WR signal register output

    signal rdb      : std_logic;                --! RD signal register output

    signal rdOP     : std_logic;                --! RD signal register input

    signal ifetchb  : std_logic;                --! IFETCH signal register output

    signal ifetchOP : std_logic;                --! IFETCH signal register input

    signal datafb   : std_logic;                --! DATAF signal register output

    signal datafOP  : std_logic;                --! DATAF signal register input

    signal lxdarb   : std_logic;                --! LXDAR signal register output

    signal lxdarOP  : std_logic;                --! LXDAR signal register input

    signal lxmarb   : std_logic;                --! LXMAR signal register output

    signal lxmarOP  : std_logic;                --! LXMAR signal register input

    signal lxparb   : std_logic;                --! LXPAR signal register output

    signal lxparOP  : std_logic;                --! LXPAR signal register input

    signal memselb  : std_logic;                --! MEMSEL signal register output

    signal memselOP : std_logic;                --! MEMSEL signal register input

    signal intgntb  : std_logic;                --! INTGNT signal register output

    signal dmagnt   : std_logic;                --! DMAGNT signal register input

    signal intgntOP : std_logic;                --! INTGNT signal register input

    signal waitfb   : std_logic;                --! WAITF signal register output

    signal waitfOP  : std_logic;                --! WAITF signal register input

    signal oops     : std_logic;

    --

    -- State Information

    --

    type state_t is (

        stateReset,

        stateInit,

        stateCheckReq,

        stateFetchAddr,

        stateFetchData,

        stateLoadIR,

        stateDecodeInstruction,

        --

        -- MRI States

        --

        stateMRIreadAddr,

        stateMRIreadDataIND,

        stateMRIreadIncAddr,

        stateMRIreadIndData,

        stateMRIexecute,

        --

        -- IOT states

        --

        stateIOTdecode,

        stateIOT,

        --

        -- Stack Operation States

        --

        statePOPaddr,

        statePOPdata,

        stateRTN1,

        stateRTN2,

        stateRTNaddr,

        stateRTNdata,

        --

        -- OPR Groups

        --

        stateOprGroup1Seq3,

        stateOprGroup1Seq4,

        stateOprGroup2Seq2,

        stateOprGroup3Seq3,

        --

        -- Front Panel States

        --

        stateHalt,

        stateContinue,

        stateLoadADDR,

        stateLoadEXTD,

        stateClear,

        stateDepositWriteData,

        stateDeposit,

        stateExamine,

        stateExamineReadAddr,

        stateExamineReadData,

        stateHaltDone,

        --

        -- EAE States

        --

        stateEAEfetchAddr,

        stateEAEfetchData,

        stateEAEindWrite,

        stateEAEindReadAddr,

        stateEAEindReadData,

        stateEAEshift,

        stateEAEwait,

        stateEAEnmi,

        stateEAEshiftDVI,

        stateEAEsubDVI,

        stateEAEmuy,

        stateEAEreadDADaddr0,

        stateEAEreadDADaddr1,

        stateEAEreadDADdata0,

        stateEAEreadDADdata1,

        stateEAEdst,

        --

        -- HALT states

        --

        stateDone,

        stateLALA

    );

    signal   state      : state_t;

    signal   nextState  : state_t;

    constant maAutoIncr : std_logic_vector(3 to 11) := o"001";

    --

    -- Output files for state dumpState

    --

    -- synthesis translate_off

    file     FIL        : text is out "STD_OUTPUT";

    file     STDOUT     : text is out "STD_OUTPUT";

  --file     FIL        : text is out "trace.txt";

    -- synthesis translate_on

    --

    -- vectorize

    --

    function vectorize(s: std_logic) return std_logic_vector is

        variable v: std_logic_vector(0 to 0);

    begin

        v(0) := s;

        return v;

    end;

    --

    -- dumpState()

    --

    procedure dumpState(PC : in addr_t) is

        -- synthesis translate_off

        variable LIN : line;

        -- synthesis translate_on

    begin

        -- synthesis translate_off

        write (LIN, string'("ST:"));

        write (LIN, string'(" PC="));

        owrite(LIN, PC);

        write (LIN, string'(", IR="));

        owrite(LIN, IR);

        write (LIN, string'(", LAC="));

        owrite(LIN, "00" & LAC);

        write (LIN, string'(", MQ="));

        owrite(LIN, MQ);

        write (LIN, string'(", SR="));

        owrite(LIN, SR);

        write (LIN, string'(", IF="));

        owrite(LIN, INF);

        write (LIN, string'(", DF="));

        owrite(LIN, DF);

        write (LIN, string'(", IB="));

        owrite(LIN, IB);

        write (LIN, string'(", UB="));

        owrite(LIN, "00" & vectorize(UB));

        write (LIN, string'(", UF="));

        owrite(LIN, "00" &  vectorize(UF));

        write (LIN, string'(", USF="));

        owrite(LIN, "00" &  SF(0 to 0));

        write (LIN, string'(", ISF="));

        owrite(LIN, SF(1 to 3));

        write (LIN, string'(", DSF="));

        owrite(LIN, SF(4 to 6));

        write (LIN, string'(", SC="));

        owrite(LIN, '0' & SC);

        write (LIN, string'(", GTF="));

        owrite(LIN, "00" & vectorize(GTF));

        write (LIN, string'(", EMODE="));

        owrite(LIN, "00" & vectorize(EMODE));

        write (LIN, string'(", IEFF="));

        owrite(LIN, "00" & vectorize(IE));

        write (LIN, string'(", IDFF="));

        owrite(LIN, "00" & vectorize(ID));

        write (LIN, string'(", IIFF="));

        owrite(LIN, "00" & vectorize(II));

        write (LIN, string'(", IRQ="));

        owrite(LIN, "00" & vectorize(IRQ));

        write (LIN, string'(", SP1="));

        owrite(LIN, SP2);

        write (LIN, string'(", SP2="));

        owrite(LIN, SP1);

        write (LIN, string'("; MA=00000"));

        --owrite(LIN, XMA & MA);

        writeline(FIL, LIN);

        -- synthesis translate_on

    end dumpState;

    --

    -- dispHALT

    --

    procedure dispHALT(signal PC : in addr_t) is

        -- synthesis translate_off

       variable LIN : line;

        -- synthesis translate_on

    begin

        -- synthesis translate_off

        write (LIN, string'("CPU Halted at PC = "));

        owrite(LIN, PC);

        writeline(STDOUT, LIN);

        -- synthesis translate_on

    end dispHALT;

    --

    -- dispCONT

    --

    procedure dispCONT(signal PC : in addr_t) is

        -- synthesis translate_off

        variable LIN : line;

        -- synthesis translate_on

    begin

        -- synthesis translate_off

        write (LIN, string'("CPU Continued at PC = "));

        owrite(LIN, PC);

        writeline(STDOUT, LIN);

        -- synthesis translate_on

    end dispCONT;

begin

    IRQ <= '1' when ((dev.intr = '1') or

                     (USRTRP = '1' and swOPT.TSD = '0') or

                     (usrtrpOP = usrtrpopSET and swOPT.TSD = '0')) else '0';

    --

    --  ALU

    --

    iALU : entity work.eALU (rtl) port map (

        sys     => sys,

        acOP    => acOP,

        BTSTRP  => BTSTRP,

        GTF     => GTF,

        HLTTRP  => HLTTRP,

        IE      => IE,

        IRQ     => IRQ,

        PNLTRP  => PNLTRP,

        PWRTRP  => PWRTRP,

        DF      => DF,

        EAE     => EAE,

        INF     => INF,

        IR      => IR,

        MA      => MA,

        MD      => MD,

        MQ      => MQ,

        PC      => PC,

        SC      => SC,

        SF      => SF,

        SP1     => SP1,

        SP2     => SP2,

        SR      => SR,

        UF      => UF,

        LAC     => LAC

    );

    --

    -- CTRLFF

    --

    iCTRLFF : entity work.eCTRLFF (rtl) port map (

        sys      => sys,

        ctrlffOP => ctrlffOP,

        CTRLFF   => CTRLFF

    );

    --

    -- EAE Register

    --

    iEAE : entity work.eEAE (rtl) port map (

        sys     => sys,

        eaeOP   => eaeOP,

        MD      => MD,

        MQ      => MQ,

        AC      => AC,

        EAE     => EAE

    );

    --

    -- EAE Mode A

    --

    iEMODE : entity work.eEMODE (rtl) port map (

        sys     => sys,

        emodeOP => emodeOP,

        EMODE   => EMODE

    );

    --

    -- FZ Flip Flop

    --

    iFZ : entity work.eFZ (rtl) port map (

        sys  => sys,

        fzOP => fzOP,

        FZ   => FZ

    );

    --

    -- GTF

    --

    iGTF : entity work.eGTF (rtl) port map (

        sys   => sys,

        gtfOP => gtfOP,

        AC    => AC,

        GTF   => GTF

    );

    --

    -- HLTTRP

    --

    iHLTTRP : entity work.eHLTTRP (rtl) port map (

        sys      => sys,

        hlttrpOP => hlttrpOP,

        HLTTRP   => HLTTRP

    );

    --

    -- Program Counter (PC)

    --

    iPC : entity work.ePC (rtl) port map (

        sys  => sys,

        pcOP => pcOP,

        IR   => IR,

        MA   => MA,

        MB   => MB,

        MD   => MD,

        SR   => SR,

        PC   => PC

    );

    --

    -- Multiplier Quotient Register (MQ)

    --

    iMQ : entity work.eMQ (rtl) port map (

        sys  => sys,

        mqOP => mqOP,

        AC   => AC,

        MD   => MD,

        EAE  => EAE,

        MQ   => MQ

    );

    --

    -- Auxillary Multiplier Quotient Register (MQA)

    --

    iMQA : entity work.eMQA (rtl) port map (

        sys   => sys,

        mqaOP => mqaOP,

        MQ    => MQ,

        MQA   => MQA

    );

    --

    -- Interrupt Enable Register

    --

    iIE : entity work.eIE (rtl) port map (

        sys  => sys,

        ieOP => ieOP,

        IE   => IE

    );

    --

    -- Interrupt Inhibit Register

    --

    iII : entity work.eII (rtl) port map (

        sys  => sys,

        iiOP => iiOP,

        II   => II

    );

    --

    -- USRTRP Register

    --

    iUSRTRP : entity work.eUSRTRP (rtl) port map (

        sys      => sys,

        usrtrpOP => usrtrpOP,

        USRTRP   => USRTRP

    );

    --

    -- Instruction Register (IR)

    --

    iIR: entity work.eIR (rtl) port map (

        sys   => sys,

        irOP  => irOP,

        MD    => MD,

        IR    => IR

    );

    --

    -- Memory Address Register (MA)

    --

    iMA : entity work.eMA (rtl) port map (