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--------------------------------------------------------------------
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--!
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--! PDP-8 Processor
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--!
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--! \brief
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--! RK05 Disk Simulation
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--!
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--! \file
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--! rk05.vhd
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--!
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--! \author
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--! Rob Doyle - doyle (at) cox (dot) net
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--!
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--! \details
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--!
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--! An RK05 has the following parameters:
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--!
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--! -# 2 heads per disk
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--! -# 203 cylinders (or tracks) per head.
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--! -# 16 sectors per cylinder (or track).
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--! -# 256 words per sector.
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--!
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--! Assuming the 12-bit word is stored in two bytes, an
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--! RK05 image requires 3,325,952 bytes of storage.
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--!
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--! It is a matter of good fortune that the RK05 has 256
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--! word sectors and a standard Secure Digital chip has
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--! 512 byte sectors. As before, the mapping between the
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--! 12 bit data and the two bytes of the Secure Digital
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--! chip is borrowed from SIMH.
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--!
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--! The SD drive requires a 32-bit address that selects 512-
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--! byte sectors. 512 byte sectors work nicely because a 512-
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--! byte sector maps nicely to a 256 word (12-bit) sector by
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--! ignoring the 4- MSB bits out of every 16-bits.
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--!
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--! The mapping between DISK, HEAD, CYL, and SECTOR and Secure
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--! Digital (SD) Sectors is as follows:
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--!
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--! \verbatim
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--!
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--! +-----+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+
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--! SD: |31-15|14|13|12|11|10| 9| 8| 7| 6| 5| 4| 3| 2| 1| 0|
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--! +-----+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+
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--! RK8E: | 0 |D0|D1|C0|C1|C2|C3|C4|C5|C6|C7|H0|S0|S1|S2|S3|
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--! +-----+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+
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--!
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--! where:
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--! D(0:1) : RK8E Disk Select
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--! C(0:7) : RK8E Cylinder Select
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--! H(0:0) : RK8E Head Select
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--! S(0:3) : RK8E Sector Select
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--!
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--! \endverbatim
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--!
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--! Therefore the total system capacity is 6651904 words. This
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--! occupies 8388608 words (16 MB) of disk space because we
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--! round up the 203 cylinders to 256 and convert to bytes.
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--!
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--! The Secure Digital card can read or write a sector in about
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--! 400 microseconds. Obviously this is way faster than a real
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--! RK05 Disk Drive operated.
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--!
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--! In order to simulate the actual timing, four RK05 "Disk
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--! Simulators" are implemented in this code. The purpose of
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--! Disk Simulators is to simulate the head seek timing and to
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--! simulate the rotational latency of a real disk. Note: the
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--! Disk Simulators don't actually read or write data - their
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--! purpose is strictly to simulate timing.
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--!
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--! When the RK05 simulator finishes, the Secure Digital
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--! Interface device reads or writes the data to the physical
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--! media.
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--!
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--! This device simulates the timing of an RK05.
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--!
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--! The following table is used for determining seek timing:
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--!
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--! \verbatim
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--! +-----+----------+
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--! | 0 | 0 ms |
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--! +-----+----------+
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--! | 1 | 10 ms |
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--! +-----+----------+
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--! | 2 | 20 ms |
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--! +-----+----------+
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--! | 4 | 30 ms |
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--! +-----+----------+
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--! | 7 | 40 ms |
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--! +-----+----------+
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--! | 15 | 50 ms |
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--! +-----+----------+
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--! | 30 | 60 ms |
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--! +-----+----------+
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--! | 55 | 70 ms |
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--! +-----+----------+
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--! | 99 | 80 ms |
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--! +-----+----------+
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--! | 205 | 90 ms |
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--! +-----+----------+
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--! \endverbatim
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--!
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--! \note
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--! The sector mapping described above has matches SIMH.
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--! Therefore SIMH disk images may be used for this
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--! application without reformatting.
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--!
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--! \note
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--! This doesn't simulate the read/write actions of the RK05.
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--! It merely simulates the latency on the RK05.
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--! When the RK8E receives a command to do something, it
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--! determines which RK05 the command is intended. The RK8E
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--! passes the command to the RK05 where the disk latencies
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--! are simulated. When the latencies have expired, the RK05
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--! passes the command to the single Secure Disk device where
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--! the actual read/write operation occurs.
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--!
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--------------------------------------------------------------------
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--
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-- Copyright (C) 2009, 2010, 2011, 2012 Rob Doyle
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--
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-- This source file may be used and distributed without
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-- restriction provided that this copyright statement is not
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-- removed from the file and that any derivative work contains
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-- the original copyright notice and the associated disclaimer.
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--
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-- This source file is free software; you can redistribute it
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-- and/or modify it under the terms of the GNU Lesser General
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-- Public License as published by the Free Software Foundation;
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-- version 2.1 of the License.
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--
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-- This source is distributed in the hope that it will be
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-- useful, but WITHOUT ANY WARRANTY; without even the implied
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-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
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-- PURPOSE. See the GNU Lesser General Public License for more
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-- details.
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--
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-- You should have received a copy of the GNU Lesser General
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-- Public License along with this source; if not, download it
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-- from http://www.gnu.org/licenses/lgpl.txt
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--
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--------------------------------------------------------------------
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--
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-- Comments are formatted for doxygen
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--
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library ieee; --! IEEE Library
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use ieee.std_logic_1164.all; --! IEEE 1164
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use ieee.numeric_std.all; --! IEEE Numeric Standard
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use work.cpu_types.all; --! CPU types
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use work.rk05_types.all; --! RK05 types
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use work.sd_types.all; --! SD Types
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--
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--! RK05 Disk Simulation Entity
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--
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entity eRK05 is port (
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sys : in sys_t; --! Clock/Reset
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ioclr : in std_logic; --! IOCLR
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simtime : in std_logic; --! Simulate RK05 Timing
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sdWP : in std_logic; --! WP from SD Card (Asserted when WP)
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sdCD : in std_logic; --! CD from SD Card (Asserted when No Card)
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sdFAIL : in std_logic; --! SD Failure
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rk05INH : in rk05WRINH_t; --! Write Inhibited
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rk05MNT : in rk05MNT_t; --! Drive is Mounted
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rk05OP : in rk05OP_t; --! RK05 OP
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rk05CYL : in rk05CYL_t; --! RK05 Cylinder
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rk05HEAD : in rk05HEAD_t; --! RK05 Head
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rk05SECT : in rk05SECT_t; --! RK05 Sector
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rk05DRIVE : in rk05DRIVE_t; --! RK05 Drive
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rk05LEN : in rk05LEN_t; --! RK05 Read/Write Length
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rk05MEMaddr : in addr_t; --! RK05 Memory Address
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rk05STAT : out rk05STAT_t --! RK05 Status
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);
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end eRK05;
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--
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--! RK05 Disk Simulation RTL
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--
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architecture rtl of eRK05 is
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type state_t is (stateIDLE,
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stateSeekONLY,
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stateSeekRDWR,
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stateWaitRDWR,
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stateDONE); --! State type definition
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signal state : state_t; --! State
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signal active : std_logic; --! Activity (timed oneshot)
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signal rk05WRLOCK : rk05WRINH_t; --! write locked
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signal rk05state : rk05STATE_t; --! Returned State
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signal rk05RECAL : std_logic; --! Recalibrate
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signal curCYL : rk05CYL_t; --! Current Cylinder
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signal diskADDR : sdDISKaddr_t; --! Disk Address
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signal delayCount : integer range 0 to 45000000; --! time delay counter
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signal sdOP : sdOP_t; --! SD OP
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signal sdLEN : sdLEN_t; --! SD Read/Write Length
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signal sdMEMaddr : addr_t; --! SD Memory Address
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signal sdDISKaddr : sdDISKaddr_t; --! SD Disk Address
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constant tenMS : integer := 500000; --! 10 milliseconds
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constant shortDelay : integer := 50; --! 1 microseconds
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constant sdADDRpad : std_logic_vector(0 to 16) := (others => '0');
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constant rk05CYL0 : rk05CYL_t := (others => '0');
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--!
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--! This function returns the number of 50 MHz clock cycles to delay
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--! for the seek delay simulation.
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--!
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function seekDelay(newCYL : rk05CYL_t; oldCYL : rk05CYL_t) return integer is
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variable diffCYL : integer range 0 to 255;
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begin
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if newCYL > oldCYL then
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diffCYL := to_integer(unsigned(newCYL) - unsigned(oldCYL));
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else
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diffCYL := to_integer(unsigned(oldCYL) - unsigned(newCYL));
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end if;
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if diffCYL < 1 then
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return 0; -- 0 ms
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elsif diffCYL < 2 then
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return tenMS * 1; -- 10 ms
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elsif diffCYL < 3 then
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return tenMS * 2; -- 20 ms
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elsif diffCYL < 5 then
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return tenMS * 3; -- 30 ms
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elsif diffCYL < 8 then
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return tenMS * 4; -- 40 ms
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elsif diffCYL < 16 then
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return tenMS * 5; -- 50 ms
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elsif diffCYL < 31 then
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return tenMS * 6; -- 60 ms
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elsif diffCYL < 56 then
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return tenMS * 7; -- 70 ms
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elsif diffCYL < 100 then
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return tenMS * 8; -- 80 ms
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else
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return tenMS * 9; -- 90 ms
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end if;
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end seekDelay;
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begin
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--
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-- Disk Address
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--
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diskADDR <= sdADDRpad & rk05DRIVE & rk05CYL & rk05HEAD & rk05SECT;
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--
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--! State machine
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--
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RK05_SIM : process(sys, ioclr)
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begin
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if sys.rst = '1' or ioclr = '1' then
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delayCount <= 0;
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rk05WRLOCK <= '0';
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rk05RECAL <= '0';
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state <= stateIdle;
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sdOP <= sdopNOP;
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sdLEN <= '0';
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curCYL <= (others => '0');
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sdMEMaddr <= (others => '0');
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sdDISKaddr <= (others => '0');
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elsif rising_edge(sys.clk) then
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if ioclr = '1' then
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delayCount <= 0;
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rk05WRLOCK <= '0';
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rk05RECAL <= '0';
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state <= stateIdle;
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sdOP <= sdopNOP;
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sdLEN <= '0';
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curCYL <= (others => '0');
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sdMEMaddr <= (others => '0');
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sdDISKaddr <= (others => '0');
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else
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if rk05OP = rk05opCLR then
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rk05WRLOCK <= '0';
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sdOP <= sdopABORT;
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state <= stateDONE;
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else
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case state is
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--
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-- Nothing happening
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--
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when stateIDLE =>
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case rk05OP is
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--
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-- IDLE:
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-- Nothing to do
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--
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when rk05opNOP =>
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null;
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--
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-- Reset:
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-- Handled above
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--
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when rk05opCLR =>
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null;
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--
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-- Wrprot:
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-- Write protect the drive
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--
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when rk05opWRPROT =>
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rk05WRLOCK <= '1';
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--
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-- Recalibrate:
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-- Seek to cylinder 0
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--
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when rk05opRECAL =>
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sdOP <= sdopNOP;
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sdLEN <= rk05LEN;
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sdMEMaddr <= rk05MEMaddr;
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sdDISKaddr <= diskADDR;
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rk05RECAL <= '1';
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curCYL <= rk05CYL0;
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if simtime = '1' then
|
| 340 |
|
|
delayCount <= seekDelay(curCYL, rk05CYL0);
|
| 341 |
|
|
else
|
| 342 |
|
|
delayCount <= shortDelay;
|
| 343 |
|
|
end if;
|
| 344 |
|
|
state <= stateSeekONLY;
|
| 345 |
|
|
|
| 346 |
|
|
--
|
| 347 |
|
|
-- Seek Operation
|
| 348 |
|
|
-- Seek to new cyclinder
|
| 349 |
|
|
--
|
| 350 |
|
|
|
| 351 |
|
|
when rk05opSEEK =>
|
| 352 |
|
|
sdOP <= sdopNOP;
|
| 353 |
|
|
sdLEN <= rk05LEN;
|
| 354 |
|
|
sdMEMaddr <= rk05MEMaddr;
|
| 355 |
|
|
sdDISKaddr <= diskADDR;
|
| 356 |
|
|
curCYL <= rk05CYL;
|
| 357 |
|
|
if simtime = '1' then
|
| 358 |
|
|
delayCount <= seekDelay(curCYL, rk05CYL);
|
| 359 |
|
|
else
|
| 360 |
|
|
delayCount <= shortDelay;
|
| 361 |
|
|
end if;
|
| 362 |
|
|
state <= stateSeekONLY;
|
| 363 |
|
|
|
| 364 |
|
|
--
|
| 365 |
|
|
-- Read Operation
|
| 366 |
|
|
--
|
| 367 |
|
|
|
| 368 |
|
|
when rk05opREAD =>
|
| 369 |
|
|
sdOP <= sdopRD;
|
| 370 |
|
|
sdLEN <= rk05LEN;
|
| 371 |
|
|
sdMEMaddr <= rk05MEMaddr;
|
| 372 |
|
|
sdDISKaddr <= diskADDR;
|
| 373 |
|
|
curCyl <= rk05CYL;
|
| 374 |
|
|
if simtime = '1' then
|
| 375 |
|
|
delayCount <= seekDelay(curCYL, rk05CYL);
|
| 376 |
|
|
else
|
| 377 |
|
|
delayCount <= shortDelay;
|
| 378 |
|
|
end if;
|
| 379 |
|
|
state <= stateSeekRDWR;
|
| 380 |
|
|
|
| 381 |
|
|
--
|
| 382 |
|
|
-- Write Operation
|
| 383 |
|
|
--
|
| 384 |
|
|
|
| 385 |
|
|
when rk05opWRITE =>
|
| 386 |
|
|
sdOP <= sdopWR;
|
| 387 |
|
|
sdLEN <= rk05LEN;
|
| 388 |
|
|
sdMEMaddr <= rk05MEMaddr;
|
| 389 |
|
|
sdDISKaddr <= diskADDR;
|
| 390 |
|
|
curCyl <= rk05CYL;
|
| 391 |
|
|
if simtime = '1' then
|
| 392 |
|
|
delayCount <= seekDelay(curCYL, rk05CYL);
|
| 393 |
|
|
else
|
| 394 |
|
|
delayCount <= shortDelay;
|
| 395 |
|
|
end if;
|
| 396 |
|
|
state <= stateSeekRDWR;
|
| 397 |
|
|
|
| 398 |
|
|
--
|
| 399 |
|
|
-- Anything else?
|
| 400 |
|
|
--
|
| 401 |
|
|
|
| 402 |
|
|
when others =>
|
| 403 |
|
|
null;
|
| 404 |
|
|
|
| 405 |
|
|
end case;
|
| 406 |
|
|
|
| 407 |
|
|
--
|
| 408 |
|
|
-- stateSeekONLY:
|
| 409 |
|
|
-- Simulate Seek Timing on Seeks
|
| 410 |
|
|
--
|
| 411 |
|
|
|
| 412 |
|
|
when stateSeekONLY =>
|
| 413 |
|
|
if delayCount = 0 then
|
| 414 |
|
|
state <= stateDONE;
|
| 415 |
|
|
else
|
| 416 |
|
|
delayCount <= delayCount - 1;
|
| 417 |
|
|
end if;
|
| 418 |
|
|
|
| 419 |
|
|
--
|
| 420 |
|
|
-- stateSeekRDWR:
|
| 421 |
|
|
-- Simulate Seek Timing on Read/Writes
|
| 422 |
|
|
--
|
| 423 |
|
|
|
| 424 |
|
|
when stateSeekRDWR =>
|
| 425 |
|
|
if delayCount = 0 then
|
| 426 |
|
|
if simtime = '1' then
|
| 427 |
|
|
delayCount <= tenMS;
|
| 428 |
|
|
else
|
| 429 |
|
|
delayCount <= shortDelay;
|
| 430 |
|
|
end if;
|
| 431 |
|
|
state <= stateWaitRDWR;
|
| 432 |
|
|
else
|
| 433 |
|
|
delayCount <= delayCount - 1;
|
| 434 |
|
|
end if;
|
| 435 |
|
|
|
| 436 |
|
|
--
|
| 437 |
|
|
-- stateWaitRDWR:
|
| 438 |
|
|
-- Simuate rotational latency on Read/Writes
|
| 439 |
|
|
--
|
| 440 |
|
|
|
| 441 |
|
|
when stateWaitRDWR =>
|
| 442 |
|
|
if delayCount = 0 then
|
| 443 |
|
|
state <= stateDone;
|
| 444 |
|
|
else
|
| 445 |
|
|
delayCount <= delayCount - 1;
|
| 446 |
|
|
end if;
|
| 447 |
|
|
|
| 448 |
|
|
--
|
| 449 |
|
|
-- stateDone:
|
| 450 |
|
|
--
|
| 451 |
|
|
|
| 452 |
|
|
when stateDONE =>
|
| 453 |
|
|
rk05RECAL <= '0';
|
| 454 |
|
|
state <= stateIDLE;
|
| 455 |
|
|
|
| 456 |
|
|
--
|
| 457 |
|
|
-- Anything else?
|
| 458 |
|
|
--
|
| 459 |
|
|
|
| 460 |
|
|
when others =>
|
| 461 |
|
|
null;
|
| 462 |
|
|
|
| 463 |
|
|
end case;
|
| 464 |
|
|
end if;
|
| 465 |
|
|
end if;
|
| 466 |
|
|
end if;
|
| 467 |
|
|
end process RK05_SIM;
|
| 468 |
|
|
|
| 469 |
|
|
--
|
| 470 |
|
|
--! Activity Timer for LED
|
| 471 |
|
|
--
|
| 472 |
|
|
|
| 473 |
|
|
ACTIVITY : process(sys)
|
| 474 |
|
|
variable timer : integer range 0 to 4999999; --! Timer
|
| 475 |
|
|
constant maxTIME : integer := 4999999; --! Time delay
|
| 476 |
|
|
begin
|
| 477 |
|
|
if sys.rst = '1' then
|
| 478 |
|
|
timer := 0;
|
| 479 |
|
|
active <= '0';
|
| 480 |
|
|
elsif rising_edge(sys.clk) then
|
| 481 |
|
|
if ((rk05OP = rk05opRECAL) or
|
| 482 |
|
|
(rk05OP = rk05opSEEK ) or
|
| 483 |
|
|
(rk05OP = rk05opREAD ) or
|
| 484 |
|
|
(rk05OP = rk05opWRITE)) then
|
| 485 |
|
|
timer := maxTIME;
|
| 486 |
|
|
active <= '1';
|
| 487 |
|
|
elsif timer = 0 then
|
| 488 |
|
|
active <= '0';
|
| 489 |
|
|
else
|
| 490 |
|
|
timer := timer - 1;
|
| 491 |
|
|
end if;
|
| 492 |
|
|
end if;
|
| 493 |
|
|
end process ACTIVITY;
|
| 494 |
|
|
|
| 495 |
|
|
--
|
| 496 |
|
|
-- Combinational logic
|
| 497 |
|
|
--
|
| 498 |
|
|
|
| 499 |
|
|
with state select
|
| 500 |
|
|
rk05state <= rk05stIDLE when stateIDLE,
|
| 501 |
|
|
rk05stDONE when stateDONE,
|
| 502 |
|
|
rk05stBUSY when others;
|
| 503 |
|
|
|
| 504 |
|
|
rk05STAT.active <= active;
|
| 505 |
|
|
rk05STAT.state <= rk05state;
|
| 506 |
|
|
rk05STAT.mounted <= rk05MNT and not(sdFAIL) and not(sdCD);
|
| 507 |
|
|
rk05STAT.WRINH <= rk05INH or rk05WRLOCK or sdWP;
|
| 508 |
|
|
rk05STAT.recal <= rk05RECAL;
|
| 509 |
|
|
rk05STAT.sdOP <= sdOP;
|
| 510 |
|
|
rk05STAT.sdLEN <= sdLEN;
|
| 511 |
|
|
rk05STAT.sdMEMaddr <= sdMEMaddr;
|
| 512 |
|
|
rk05STAT.sdDISKaddr <= sdDISKaddr;
|
| 513 |
|
|
|
| 514 |
|
|
end rtl;
|
