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[/] [phr/] [branches/] [placas_1.0/] [placas/] [FPGA/] [libreria/] [DIP4-8_OSC.mod] - Blame information for rev 410

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Line No. Rev Author Line
1 5 guanucolui 
PCBNEW-LibModule-V1  jue 08 mar 2012 12:33:34 ART
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# encoding utf-8
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$INDEX
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DIP4-8_OSC
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$EndINDEX
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$MODULE DIP4-8_OSC
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Po 0 0 0 15 4AAE6004 4F58D144 ~~
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Li DIP4-8_OSC
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Cd Module Dil 14 pins, pads ronds
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Kw DIL
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Sc 4F58D144
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AR DIP4-8_OSC
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Op 0 0 0
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T0 -3000 0 400 400 900 70 N V 21 N "OSC1"
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T1 1100 0 400 400 0 80 N I 21 N "OSC"
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T2 -2000 1100 300 300 0 60 N V 21 N "NC"
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T2 -2100 -1050 300 300 0 60 N V 21 N "Vcc"
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DS 0 750 0 1050 60 21
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DS 950 750 0 750 60 21
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DS 2150 750 3000 750 60 21
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DS 3000 750 3000 1050 60 21
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T2 1550 750 300 300 0 60 N V 21 N "GND"
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DS 1100 -800 0 -800 60 21
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DS 0 -800 0 -1100 60 21
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DS 2250 -800 3000 -800 60 21
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DS 3000 -800 3000 -1100 60 21
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T2 1700 -800 300 300 0 60 N V 21 N "CLK"
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DS 500 1500 2500 1500 60 21
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DS -2500 1500 -500 1500 60 21
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DS 500 -1500 2500 -1500 60 21
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DS -2500 -1500 -500 -1500 60 21
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DS -3500 1500 -4000 1500 80 21
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DS 4000 1500 3500 1500 80 21
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DS 3500 -1500 4000 -1500 80 21
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DS -4000 -1500 -3500 -1500 80 21
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DS 4000 -1500 4000 1500 80 21
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DS -4000 1500 -4000 -1500 80 21
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DS -4000 -500 -3500 -500 80 21
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DS -3500 -500 -3500 500 80 21
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DS -3500 500 -4000 500 80 21
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$PAD
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Sh "NC" R 600 600 0 0 0
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Dr 280 0 0
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At STD N 00C0FFFF
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Ne 0 ""
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Po -3000 1500
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$EndPAD
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$PAD
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Sh "GND" C 500 500 0 0 0
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Dr 280 0 0
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At STD N 00E0FFFF
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Ne 1 "DGND_1"
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Po 3000 1500
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$EndPAD
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$PAD
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Sh "CLK" C 500 500 0 0 0
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Dr 280 0 0
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At STD N 00E0FFFF
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Ne 2 "N-000019"
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Po 3000 -1500
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$EndPAD
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$PAD
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Sh "Vcc" C 500 500 0 0 0
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Dr 280 0 0
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At STD N 00E0FFFF
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Ne 3 "Vcco_1"
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Po -3000 -1500
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$EndPAD
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$PAD
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Sh "GND" C 500 500 0 0 0
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Dr 280 0 0
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At STD N 00E0FFFF
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Ne 1 "DGND_1"
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Po 0 1500
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$EndPAD
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$PAD
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Sh "CLK" C 500 500 0 0 0
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Dr 280 0 0
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At STD N 00E0FFFF
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Ne 2 "N-000019"
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Po 0 -1500
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$EndPAD
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$SHAPE3D
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Na "../libs/xtal_ret.wrl"
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Sc 1.000000 1.000000 1.000000
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Of 0.000000 0.000000 0.100000
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Ro 0.000000 0.000000 0.000000
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$EndSHAPE3D
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$EndMODULE  DIP4-8_OSC
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$EndLIBRARY

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