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[/] [phr/] [branches/] [placas_1.0/] [placas/] [FPGA/] [tmp/] [fpga_2.pro] - Blame information for rev 336

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Line No. Rev Author Line
1 17 guanucolui
update=vie 20 abr 2012 20:27:30 ART
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last_client=pcbnew
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[pcbnew]
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version=1
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PadDrlX=320
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PadDimH=600
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PadDimV=600
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BoardThickness=630
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RouteTo=15
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RouteBo=0
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Segm45=1
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Racc45=1
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SgPcb45=1
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TxtPcbV=800
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TxtPcbH=600
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TxtModV=600
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TxtModH=600
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TxtModW=120
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VEgarde=100
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DrawLar=150
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EdgeLar=150
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TxtLar=120
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MSegLar=150
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WpenSer=10
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[pcbnew/libraries]
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LibDir=
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LibName1=sockets
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LibName2=connect
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LibName3=discret
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LibName4=pin_array
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LibName5=divers
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LibName6=libcms
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LibName7=display
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LibName8=valves
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LibName9=led
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LibName10=dip_sockets
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LibName11=xilinx_spartan3_virtex4_and_5
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LibName12=xilinx_virtexii-xc2v80&flashprom
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LibName13=libreria/DIP4-8_OSC
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LibName14=libreria/HOLE
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LibName15=libreria/pin_array_x1
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LibName16=libreria/TPS75003_PM_INV

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