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[/] [phr/] [branches/] [placas_1.0/] [placas/] [FPGA/] [tmp/] [fpga_2.pro] - Blame information for rev 405

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update=vie 20 abr 2012 20:27:30 ART
last_client=pcbnew
[pcbnew]
version=1
PadDrlX=320
PadDimH=600
PadDimV=600
BoardThickness=630
RouteTo=15
RouteBo=0
Segm45=1
Racc45=1
SgPcb45=1
TxtPcbV=800
TxtPcbH=600
TxtModV=600
TxtModH=600
TxtModW=120
VEgarde=100
DrawLar=150
EdgeLar=150
TxtLar=120
MSegLar=150
WpenSer=10
[pcbnew/libraries]
LibDir=
LibName1=sockets
LibName2=connect
LibName3=discret
LibName4=pin_array
LibName5=divers
LibName6=libcms
LibName7=display
LibName8=valves
LibName9=led
LibName10=dip_sockets
LibName11=xilinx_spartan3_virtex4_and_5
LibName12=xilinx_virtexii-xc2v80&flashprom
LibName13=libreria/DIP4-8_OSC
LibName14=libreria/HOLE
LibName15=libreria/pin_array_x1
LibName16=libreria/TPS75003_PM_INV

Line No.	Rev	Author	Line
1	17	guanucolui	`update=vie 20 abr 2012 20:27:30 ART`
2			`last_client=pcbnew`
3			`[pcbnew]`
4			`version=1`
5			`PadDrlX=320`
6			`PadDimH=600`
7			`PadDimV=600`
8			`BoardThickness=630`
9			`RouteTo=15`
10			`RouteBo=0`
11			`Segm45=1`
12			`Racc45=1`
13			`SgPcb45=1`
14			`TxtPcbV=800`
15			`TxtPcbH=600`
16			`TxtModV=600`
17			`TxtModH=600`
18			`TxtModW=120`
19			`VEgarde=100`
20			`DrawLar=150`
21			`EdgeLar=150`
22			`TxtLar=120`
23			`MSegLar=150`
24			`WpenSer=10`
25			`[pcbnew/libraries]`
26			`LibDir=`
27			`LibName1=sockets`
28			`LibName2=connect`
29			`LibName3=discret`
30			`LibName4=pin_array`
31			`LibName5=divers`
32			`LibName6=libcms`
33			`LibName7=display`
34			`LibName8=valves`
35			`LibName9=led`
36			`LibName10=dip_sockets`
37			`LibName11=xilinx_spartan3_virtex4_and_5`
38			`LibName12=xilinx_virtexii-xc2v80&flashprom`
39			`LibName13=libreria/DIP4-8_OSC`
40			`LibName14=libreria/HOLE`
41			`LibName15=libreria/pin_array_x1`
42			`LibName16=libreria/TPS75003_PM_INV`

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[/] [phr/] [branches/] [placas_1.0/] [placas/] [FPGA/] [tmp/] [fpga_2.pro] - Blame information for rev 405