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[/] [phr/] [branches/] [placas_1.0/] [placas/] [FPGA/] [xc3s50a-vq100.bak] - Blame information for rev 405

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Line No. Rev Author Line
1 12 guanucolui 
EESchema-LIBRARY Version 2.3  Date: jue 23 feb 2012 13:22:31 ART
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#encoding utf-8
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#
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# XC3S50A-VQ100
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#
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DEF XC3S50A-VQ100 U 0 40 Y Y 1 F N
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F0 "U" 1050 2600 60 H V C CNN
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F1 "XC3S50A-VQ100" 950 -2700 60 H V C CNN
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DRAW
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T 900 650 -1450 200 0 0 0 BANK0  Normal 0 C C
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T 900 650 400 200 0 0 0 BANK1  Normal 0 C C
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T 900 -550 1100 200 0 0 0 BANK2  Normal 0 C C
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T 900 -650 -1450 200 0 0 0 BANK3  Normal 0 C C
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S -1350 2500 1250 -2500 0 0 0 N
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P 4 0 0 0  -1000 -2200  -800 -2200  -800 -700  -1000 -700 N
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P 4 0 0 0  -900 2100  -700 2100  -700 150  -900 150 N
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P 4 0 0 0  900 1050  750 1050  750 -350  900 -350 N
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P 4 1 0 0  900 -700  750 -700  750 -2200  900 -2200 N
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X TMS 1 1550 1950 300 L 50 50 1 1 I
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X TDI 2 1550 2050 300 L 50 50 1 1 I
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X IO 3 -1650 -2100 300 R 50 50 1 1 B
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X IO 4 -1650 -2000 300 R 50 50 1 1 B
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X IO 5 -1650 -1900 300 R 50 50 1 1 B
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X IO 6 -1650 -1800 300 R 50 50 1 1 B
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X IO/VREF 7 -1650 -1700 300 R 50 50 1 1 B
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X GND 8 -650 -2800 300 U 50 50 1 1 W
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X IO/LHCLK0 9 -1650 -1600 300 R 50 50 1 1 B
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X IO/LHCLK1 10 -1650 -1500 300 R 50 50 1 1 B
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X IO 20 -1650 -900 300 R 50 50 1 1 B
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X IO/VS1 30 -1650 500 300 R 50 50 1 1 B
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X IO/GCLK14 40 -1650 1400 300 R 50 50 1 1 B
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X IO/D2 50 -1650 2000 300 R 50 50 1 1 B
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X IO/RHCLK1 60 1550 650 300 L 50 50 1 1 B
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X IO 70 1550 50 300 L 50 50 1 1 B
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X GND 80 250 -2800 300 U 50 50 1 1 W
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X IO/GCLK11 90 1550 -1700 300 L 50 50 1 1 B
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X VCCO_3 11 -250 2800 300 D 50 50 1 1 W
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X I 21 -1650 -800 300 R 50 50 1 1 I
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X IO/VS0 31 -1650 600 300 R 50 50 1 1 B
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X IO/GCLK15 41 -1650 1500 300 R 50 50 1 1 B
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X DIN/IO(BANK2) 51 1550 1300 300 L 50 50 1 1 B
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X IO/RHCLK2 61 1550 550 300 L 50 50 1 1 B
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X IO 71 1550 -50 300 L 50 50 1 1 B
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X VCCINT(1.2V) 81 800 2800 300 D 50 50 1 1 W
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X GND 91 450 -2800 300 U 50 50 1 1 W
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X IO/LHCLK2 12 -1650 -1400 300 R 50 50 1 1 B
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X VCCAUX(CONFIG) 22 -650 2800 300 D 50 50 1 1 W
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X IO 32 -1650 700 300 R 50 50 1 1 B
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X GND 42 -350 -2800 300 U 50 50 1 1 W
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X IO/RHCLK3 62 1550 450 300 L 50 50 1 1 B
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X IO 72 1550 -150 300 L 50 50 1 1 B
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X IO/VREF 82 1550 -1000 300 L 50 50 1 1 B
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X VCCAUX(CONFIG) 92 -450 2800 300 D 50 50 1 1 W
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X IO/LHCLK3 13 -1650 -1300 300 R 50 50 1 1 B
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X M1/IO(BANK2) 23 -1650 -300 300 R 50 50 1 1 B
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X IO 33 -1650 800 300 R 50 50 1 1 B
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X IO/GCLK0 43 -1650 1600 300 R 50 50 1 1 B
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X CCLK/IO(BANK2) 53 1550 1400 300 L 50 50 1 1 B C
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X GND 63 -50 -2800 300 U 50 50 1 1 W
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X IO 73 1550 -250 300 L 50 50 1 1 B
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X IO/GCLK4 83 1550 -1100 300 L 50 50 1 1 B
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X IO 93 1550 -1800 300 L 50 50 1 1 B
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X GND 14 -550 -2800 300 U 50 50 1 1 W
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X M2/IO(BANK2) 24 -1650 -400 300 R 50 50 1 1 B
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X IO/D7 34 -1650 900 300 R 50 50 1 1 B
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X IO/GCLK1 44 -1650 1700 300 R 50 50 1 1 B
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X DONE 54 1550 1500 300 L 50 50 1 1 C
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X IO/RHCLK6 64 1550 350 300 L 50 50 1 1 B
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X GND 74 150 -2800 300 U 50 50 1 1 W
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X IO/GCLK5 84 1550 -1200 300 L 50 50 1 1 B
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X IO 94 1550 -1900 300 L 50 50 1 1 B
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X IO/LHCLK6 15 -1650 -1200 300 R 50 50 1 1 B
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X M0/I0(BANK2) 25 -1650 -200 300 R 50 50 1 1 B
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X IO/D6 35 -1650 1000 300 R 50 50 1 1 B
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X VCCO_2 45 -50 2800 300 D 50 50 1 1 W
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X VCCAUX(CONFIG) 55 -550 2800 300 D 50 50 1 1 W
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X IO/RHCLK7 65 1550 250 300 L 50 50 1 1 B
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X TDO 75 1550 2150 300 L 50 50 1 1 O
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X IO/GCLK6 85 1550 -1300 300 L 50 50 1 1 B
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X GND 95 550 -2800 300 U 50 50 1 1 W
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X IO/HLCLK7 16 -1650 -1100 300 R 50 50 1 1 B
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X VCCO_2 26 -150 2800 300 D 50 50 1 1 W
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X IO/D5 36 -1650 1100 300 R 50 50 1 1 B
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X IO/MOSI/CSI_B 46 -1650 1800 300 R 50 50 1 1 B
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X IO 56 1550 950 300 L 50 50 1 1 B
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X VCCINT(1.2V) 66 700 2800 300 D 50 50 1 1 W
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X TCK 76 1550 2250 300 L 50 50 1 1 I
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X IO/GCLK7 86 1550 -1400 300 L 50 50 1 1 B
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X VCCO_0 96 250 2800 300 D 50 50 1 1 P
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X VCCINT(1.2V) 17 500 2800 300 D 50 50 1 1 W
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X IO/CSO_B 27 -1650 200 300 R 50 50 1 1 B
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X IO/D4 37 -1650 1200 300 R 50 50 1 1 B
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X GND 47 -250 -2800 300 U 50 50 1 1 W
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X IO 57 1550 850 300 L 50 50 1 1 B
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X VCCO_1 67 50 2800 300 D 50 50 1 1 W
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X IO/VREF 77 1550 -800 300 L 50 50 1 1 B
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X GND 87 350 -2800 300 U 50 50 1 1 W
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X I 97 1550 -2000 300 L 50 50 1 1 I
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X GND 18 -450 -2800 300 U 50 50 1 1 W
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X IO/RDWR_B 28 -1650 300 300 R 50 50 1 1 B
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X VCCINT(1.2V) 38 600 2800 300 D 50 50 1 1 W
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X INIT_B/IO(BANK2) 48 1550 1200 300 L 50 50 1 1 C
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X GND 58 -150 -2800 300 U 50 50 1 1 W
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X IO/VREF 68 1550 150 300 L 50 50 1 1 B
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X IO 78 1550 -900 300 L 50 50 1 1 B
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X IO/GCLK8 88 1550 -1500 300 L 50 50 1 1 B
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X IO/VREF 98 1550 -2100 300 L 50 50 1 1 B
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X IO 19 -1650 -1000 300 R 50 50 1 1 B
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X IO/VS2 29 -1650 400 300 R 50 50 1 1 B
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X IO/VREF 39 -1650 1300 300 R 50 50 1 1 B
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X IO/D3 49 -1650 1900 300 R 50 50 1 1 B
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X IO/RHCLK0 59 1550 750 300 L 50 50 1 1 B
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X GND 69 50 -2800 300 U 50 50 1 1 W
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X VCCO_0 79 150 2800 300 D 50 50 1 1 P
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X IO/GCLK9 89 1550 -1600 300 L 50 50 1 1 B
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X PUDC_B/IO(BANK1) 99 1550 1600 300 L 50 50 1 1 B
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X PROG_B 100 1550 1700 300 L 50 50 1 1 I I
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ENDDRAW
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ENDDEF
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#
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#End Library

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