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\documentclass[portrait,a0paper,fontscale=0.260]{baposter}
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\usepackage [utf8] {inputenc}
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\usepackage [spanish] {babel}
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\usepackage{times}
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\usepackage{graphicx}
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\graphicspath{{images/}}
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\usepackage{multicol}
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%\definecolor{lightBlue}{rgb}{0.834,0.836,0.838}
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\definecolor{lightBlue}{rgb}{1,1,1}
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\definecolor{darkBlue}{rgb}{0.055,0.59,1}
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%\definecolor{lightBlue}{rgb}{0.55,0.55,0.9}
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%\definecolor{darkBlue}{rgb}{0.085,0.085,0.312}
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\definecolor{lightBG}{rgb}{1,1,1}
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\definecolor{darkBG}{rgb}{0.8,0.8,0.8}
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 %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
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 % Save space in lists. Use this after the opening of the list
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 %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
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 \newcommand{\compresslist}{%
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 \setlength{\itemsep}{0pt}%
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 \setlength{\parskip}{0pt}%
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 \setlength{\parsep}{0pt}%
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 }
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\begin{document}
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\begin{poster}{
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 grid=false,
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 columns=6,
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 % Column spacing
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 colspacing=0.7em,
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 % Color style
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 headerColorOne=cyan!20!white!90!black,
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 borderColor=black,
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 % Format of textbox
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 textborder=roundedleft,
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boxColorOne=white,
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linewidth=1.5pt,
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 % Format of text header
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headerborder=open,
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headershape=roundedright,
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headershade=shadeTB,
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headerColorOne=darkBlue,
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headerColorTwo=lightBlue,
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headerfont=\large\sffamily\textbf,
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headerFontColor=black,
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background=plain, %shadeTD
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bgColorOne=lightBG,
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bgColorTwo=darkBG,
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headerheight=0.12\textheight,
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eyecatcher=false
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}
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{ % Poster eye catcher (top-left logo)
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 Eye Catcher, empty if option eyecatcher=no
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}
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{ %Poster title
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 \huge \sffamily Plataforma de Hardware Reconfigurable
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}
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{ % poster Authors
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 \large{\\[0.5ex]
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 Luis Alberto Guanuco (lguanuco@electronica.frc.utn.edu.ar)\\
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 Sergio Daniel Olmedo (solmedo@scdt.frc.utn.edu.ar)\\
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 Alexis Maximiliano Quinteros (50214@electronica.frc.utn.edu.ar)}
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}
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{ % University logo (top-right logo)
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 \begin{tabular}{r}
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 \includegraphics[height=0.04\textheight]{CUDARlogo.pdf}\\
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 \includegraphics[height=0.035\textheight]{UTNlogo.pdf}
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 \end{tabular}
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}
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%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
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%%% Now define the boxes that make up the poster
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%%%---------------------------------------------------------------------------
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%%% Each box has a name and can be placed absolutely or relatively.
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%%% The only inconvenience is that you can only specify a relative position
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%%% towards an already declared box. So if you have a box attached to the
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%%% bottom, one to the top and a third one which should be inbetween, you
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%%% have to specify the top and bottom boxes before you specify the middle
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%%% box.
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%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
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%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
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  \headerbox{Introducción} {name=contribution,column=0,row=0,span=3}{
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%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
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El proyecto Plataforma de Hardware Reconfigurable tiene como objetivo principal desarrollar recursos académicos para la difusión y actualización tecnológica relacionado al área digital a través de Dispositivos Lógicos Programables (PLDs).
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El desarrollo comprende el diseño de hardware y software que se publican bajo licencias libres.
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  }
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%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
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  \headerbox{Características de la PHR}{name=dos,column=0,below=contribution, span=3}{
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%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
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\begin{description}
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\compresslist
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\item [FPGA:] Xilinx Spartan-3A XC3S200A (encapsulado VQG100).
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\item [Memoria PROM:] Xilinx XCF02S.
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\item [Voltaje de entrada:] 5V.
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\item [Relojes:] Un reloj fijo y tres seleccionables:
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        \begin{description}
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        \compresslist
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        \item [Clock 0:] 50 MHz.
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        \item [Clock 1:] 16 MHz, 1 MHz, 500 kHz y 250 kHz.
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        \item [Clock 2:] 125 kHz, 62.5 kHz, 31.25 kHz, 15.625 kHz.
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        \item [Clock 3:] 3.9062 kHz, 1.9531 kHz, 976,56251 Hz.
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   \end{description}
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\item [Conectores con E/S de propósito general:] 28 pines en total.
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\item [Periféricos:] 8 LEDs, 8 llaves (DIP switch), 4 pulsadores, Display de 7 segmentos cuádruple, Puerto serie.
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\end{description}
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}
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%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
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  \headerbox{Diagrama de bloques}{name=tres,column=3,row=0,span=3}{
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%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
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\begin{center}
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\includegraphics[width=0.95\textwidth]{block.pdf}
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\end{center}
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}
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 %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
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   \headerbox{Placas del proyecto}{name=diez,column=0,below=dos,span=4}{
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 %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
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\begin{center}
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\includegraphics[height=0.25\textwidth]{phr.png}\hspace{2em}
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\includegraphics[height=0.25\textwidth]{phr_top.png}
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\end{center}
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    La \emph{Plataforma de Hardware Reconfigurable} consiste fundamentalmente en tres módulos
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de soporte físico. El módulo principal es la placa PHR donde se encuentran el chip FPGA, relojes,
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interfaces de entradas y salidas, periféricos (tales como LEDs, botones, llaves DIP, Displays de siete
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segmentos), etc. Además tiene conectores especiales para otros dos módulos sin los cuales la placa principal carece de funcionalidad.
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\begin{multicols}{2}
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\begin{center}
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\includegraphics[width=0.35\textwidth]{s3power.png}
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\end{center}
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Para cumplir con las especificaciones se utiliza la placa S3Power, que fue desarrollada por el Instituto Nacional de Tecnología Industrial (INTI) y que está disponible bajo licencia GNU.
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La función de la placa S3Power la realiza principalmente el chip TPS75003 el cuál tiene un regulador lineal y controladores para dos fuentes conmutadas, lo cual permite suministrar energía regulada con tres valores de tensión y distintas características de arranque. Los voltajes utilizados por la FPGA son de 1.2V, 2.5V y 3.3V.
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\columnbreak
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\begin{center}
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\includegraphics[width=0.44\textwidth]{oocdlink.png}
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\end{center}
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Esta placa es la interfaz que permite la comunicación entre una computadora y la placa PHR. Su característica modular, o de circuito separado de la placa PHR principal, hace que su utilización no quede restringida a la FPGA y posibilita la interacción con los multiples dispositivos que soportan JTAG.
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La placa OOCD Link incluye el chip FT2232D que establece una interfaz JTAG controlable mediante una conexión USB.
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\end{multicols}
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   }
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%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
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  \headerbox{Configuración de la FPGA}{name=trece,column=4,below=dos, span=2}{
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%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
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\begin{center}
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\includegraphics[width=.9\textwidth]{front-end.pdf}
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\end{center}
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Para transferir el diseño del usuario a la FPGA, PHR se sirve de las funciones de xc3sprog, un conjunto de aplicaciones de licencia libre que funciona en linea de comandos y que puede programar varios dispositivos mediante JTAG.
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No obstante su funcionalidad, xc3sprog puede resultar no intuitivo para el usuario principiante,
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por lo que se ofrece una interfaz gráfica denominada PHR GUI para invocar a xc3sprog de una manera muy simple.
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}
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%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
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  \headerbox{Referencias}{name=ref,column=4,below=trece, span=2}{
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%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
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References.
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}
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\end{poster}
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\end{document}
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