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guanucolui |
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x="256.83859"
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y="103.49354"
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id="tspan3168">Caracteristicas generales
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x="256.83859"
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y="121.94328"
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id="tspan3172"> --> Diagrama 3d identificación de sus partes.
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sodipodi:role="line"
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x="256.83859"
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y="140.39302"
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id="tspan3232" />
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x="256.83859"
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y="158.84276"
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id="tspan3234">Herramienta de software EDA
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x="256.83859"
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y="177.2925"
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267 |
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id="tspan3285"> --> KiCAD
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268 |
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sodipodi:role="line"
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x="256.83859"
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270 |
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y="195.74223"
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271 |
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id="tspan3289"> --> Acceder a los archivos del diseño
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272 |
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sodipodi:role="line"
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x="256.83859"
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y="214.19197"
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id="tspan3283" />
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sodipodi:role="line"
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x="256.83859"
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y="232.64171"
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id="tspan3281">Dispositivos PLDs (CPLD, FPGA)
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sodipodi:role="line"
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x="256.83859"
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y="251.09145"
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id="tspan3260"> --> Características tecnológicas
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284 |
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sodipodi:role="line"
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x="256.83859"
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y="269.54117"
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287 |
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id="tspan3262"> --> Sobre familia FPGA
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288 |
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sodipodi:role="line"
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x="256.83859"
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y="287.99091"
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291 |
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id="tspan3268"> --> Recursos de la FPGA utilizada
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292 |
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sodipodi:role="line"
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x="256.83859"
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294 |
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y="306.44064"
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id="tspan3178" />
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x="256.83859"
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y="324.89038"
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id="tspan3293">Alimentación
|
300 |
|
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sodipodi:role="line"
|
301 |
|
|
x="256.83859"
|
302 |
|
|
y="343.34012"
|
303 |
|
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id="tspan3301"> --> Características generales
|
304 |
|
|
sodipodi:role="line"
|
305 |
|
|
x="256.83859"
|
306 |
|
|
y="361.78986"
|
307 |
|
|
id="tspan3287"> --> Especificaciones para la FPGA del fabricante (Xilinx Inc.)
|
308 |
|
|
sodipodi:role="line"
|
309 |
|
|
x="256.83859"
|
310 |
|
|
y="380.23959"
|
311 |
|
|
id="tspan3291"> --> redes de capacitores de bypass y desacople
|
312 |
|
|
sodipodi:role="line"
|
313 |
|
|
x="256.83859"
|
314 |
|
|
y="398.68933"
|
315 |
|
|
id="tspan3305"> --> Consejos de "ruteo" (PCB)
|
316 |
|
|
sodipodi:role="line"
|
317 |
|
|
x="256.83859"
|
318 |
|
|
y="417.1391"
|
319 |
|
|
id="tspan3309"> --> Esquema de conexión en bloque (socket)
|
320 |
|
|
sodipodi:role="line"
|
321 |
|
|
x="256.83859"
|
322 |
|
|
y="435.58884"
|
323 |
|
|
id="tspan3323"> --> esquemático y foto/3d.
|
324 |
|
|
sodipodi:role="line"
|
325 |
|
|
x="256.83859"
|
326 |
|
|
y="454.03857"
|
327 |
|
|
id="tspan3313" />
|
328 |
|
|
sodipodi:role="line"
|
329 |
|
|
x="256.83859"
|
330 |
|
|
y="472.48831"
|
331 |
|
|
id="tspan3206">Componentes
|
332 |
|
|
sodipodi:role="line"
|
333 |
|
|
x="256.83859"
|
334 |
|
|
y="490.93805"
|
335 |
|
|
id="tspan3182"> --> (Llaves,pulsadores,led, rs232,clks, etc).
|
336 |
|
|
sodipodi:role="line"
|
337 |
|
|
x="256.83859"
|
338 |
|
|
y="509.38779"
|
339 |
|
|
id="tspan3184"> (por c/u)--> ubicación en placa (foto)
|
340 |
|
|
sodipodi:role="line"
|
341 |
|
|
x="256.83859"
|
342 |
|
|
y="527.83752"
|
343 |
|
|
id="tspan3186"> --> características eléctrica
|
344 |
|
|
sodipodi:role="line"
|
345 |
|
|
x="256.83859"
|
346 |
|
|
y="546.28723"
|
347 |
|
|
id="tspan3194"> --> esquemático
|
348 |
|
|
sodipodi:role="line"
|
349 |
|
|
x="256.83859"
|
350 |
|
|
y="564.737"
|
351 |
|
|
id="tspan3188"> --> conexión a puerto FPGA (siempre tabla)
|
352 |
|
|
sodipodi:role="line"
|
353 |
|
|
x="256.83859"
|
354 |
|
|
y="583.18671"
|
355 |
|
|
id="tspan3214"> --> consejo de uso "sano"
|
356 |
|
|
sodipodi:role="line"
|
357 |
|
|
x="256.83859"
|
358 |
|
|
y="601.63647"
|
359 |
|
|
id="tspan3222" />
|
360 |
|
|
sodipodi:role="line"
|
361 |
|
|
x="256.83859"
|
362 |
|
|
y="620.08618"
|
363 |
|
|
id="tspan3176">Puerto JTAG
|
364 |
|
|
sodipodi:role="line"
|
365 |
|
|
x="256.83859"
|
366 |
|
|
y="638.53595"
|
367 |
|
|
id="tspan3248"> --> Descripción Eléctrica del protocolo JTAG
|
368 |
|
|
sodipodi:role="line"
|
369 |
|
|
x="256.83859"
|
370 |
|
|
y="656.98566"
|
371 |
|
|
id="tspan3252"> --> Ubicación en placa (foto)
|
372 |
|
|
sodipodi:role="line"
|
373 |
|
|
x="256.83859"
|
374 |
|
|
y="675.43542"
|
375 |
|
|
id="tspan3256"> --> esquemático
|
376 |
|
|
sodipodi:role="line"
|
377 |
|
|
x="256.83859"
|
378 |
|
|
y="693.88513"
|
379 |
|
|
id="tspan3345"> --> Modos de configuración de la FPGA
|
380 |
|
|
sodipodi:role="line"
|
381 |
|
|
x="256.83859"
|
382 |
|
|
y="712.3349"
|
383 |
|
|
id="tspan3351"> --> conexión a puerto FPGA (siempre tabla)
|
384 |
|
|
sodipodi:role="line"
|
385 |
|
|
x="256.83859"
|
386 |
|
|
y="730.78461"
|
387 |
|
|
id="tspan3258"> --> consejo de uso "sano"
|
388 |
|
|
sodipodi:role="line"
|
389 |
|
|
x="256.83859"
|
390 |
|
|
y="749.23438"
|
391 |
|
|
id="tspan3246" />
|
392 |
|
|
sodipodi:role="line"
|
393 |
|
|
x="256.83859"
|
394 |
|
|
y="767.68408"
|
395 |
|
|
id="tspan3228" />
|
396 |
|
|
sodipodi:role="line"
|
397 |
|
|
x="256.83859"
|
398 |
|
|
y="786.13385"
|
399 |
|
|
id="tspan3230" />
|
400 |
|
|
|
401 |
|
|
xml:space="preserve"
|
402 |
|
|
style="font-size:31.46223259px;font-style:normal;font-variant:normal;font-weight:normal;font-stretch:normal;text-align:start;line-height:125%;writing-mode:lr-tb;text-anchor:start;fill:#000000;fill-opacity:1;stroke:none;font-family:LMRoman9;-inkscape-font-specification:LMRoman9"
|
403 |
|
|
x="-145.61296"
|
404 |
|
|
y="-127.04601"
|
405 |
|
|
id="text2814-5-2"
|
406 |
|
|
sodipodi:linespacing="125%">
|
407 |
|
|
sodipodi:role="line"
|
408 |
|
|
x="-145.61296"
|
409 |
|
|
y="-127.04601"
|
410 |
|
|
id="tspan3086">Introducción
|
411 |
|
|
|
412 |
|
|
xml:space="preserve"
|
413 |
|
|
style="font-size:21.33618164px;font-style:normal;font-variant:normal;font-weight:normal;font-stretch:normal;text-align:start;line-height:125%;writing-mode:lr-tb;text-anchor:start;fill:#000000;fill-opacity:1;stroke:none;font-family:LMRoman9;-inkscape-font-specification:LMRoman9"
|
414 |
|
|
x="-119.36004"
|
415 |
|
|
y="-91.485306"
|
416 |
|
|
id="text2814-7-1"
|
417 |
|
|
sodipodi:linespacing="125%">
|
418 |
|
|
sodipodi:role="line"
|
419 |
|
|
x="-119.36004"
|
420 |
|
|
y="-91.485306"
|
421 |
|
|
id="tspan2926-9-3">Caracteristicas HW/SW
|
422 |
|
|
sodipodi:role="line"
|
423 |
|
|
x="-119.36004"
|
424 |
|
|
y="-64.815079"
|
425 |
|
|
id="tspan3119">Diagramas en bloques
|
426 |
|
|
sodipodi:role="line"
|
427 |
|
|
x="-119.36004"
|
428 |
|
|
y="-38.144852"
|
429 |
|
|
id="tspan3121">Licencias Libres/Abiertas
|
430 |
|
|
sodipodi:role="line"
|
431 |
|
|
x="-119.36004"
|
432 |
|
|
y="-11.474625"
|
433 |
|
|
id="tspan3123" />
|
434 |
|
|
|
435 |
|
|
xml:space="preserve"
|
436 |
|
|
style="font-size:31.46223259px;font-style:normal;font-variant:normal;font-weight:normal;font-stretch:normal;text-align:start;line-height:125%;writing-mode:lr-tb;text-anchor:start;fill:#000000;fill-opacity:1;stroke:none;font-family:LMRoman9;-inkscape-font-specification:LMRoman9"
|
437 |
|
|
x="1221.7596"
|
438 |
|
|
y="959.16742"
|
439 |
|
|
id="text2814-5-4-7"
|
440 |
|
|
sodipodi:linespacing="125%">
|
441 |
|
|
sodipodi:role="line"
|
442 |
|
|
id="tspan2816-8-7-1"
|
443 |
|
|
x="1221.7596"
|
444 |
|
|
y="959.16742">Apéndice
|
445 |
|
|
|
446 |
|
|
xml:space="preserve"
|
447 |
|
|
style="font-size:21.33618164px;font-style:normal;font-variant:normal;font-weight:normal;font-stretch:normal;text-align:start;line-height:125%;writing-mode:lr-tb;text-anchor:start;fill:#000000;fill-opacity:1;stroke:none;font-family:LMRoman9;-inkscape-font-specification:LMRoman9"
|
448 |
|
|
x="1236.9219"
|
449 |
|
|
y="993.17572"
|
450 |
|
|
id="text2814-7-4"
|
451 |
|
|
sodipodi:linespacing="125%">
|
452 |
|
|
sodipodi:role="line"
|
453 |
|
|
x="1236.9219"
|
454 |
|
|
y="993.17572"
|
455 |
|
|
id="tspan2926-9-63">Esquemáticos
|
456 |
|
|
sodipodi:role="line"
|
457 |
|
|
x="1236.9219"
|
458 |
|
|
y="1019.8459"
|
459 |
|
|
id="tspan3380">archivo/s UCF de la placa PHR
|
460 |
|
|
sodipodi:role="line"
|
461 |
|
|
x="1236.9219"
|
462 |
|
|
y="1046.5161"
|
463 |
|
|
id="tspan3386">scripts de OpenOCD y xc3sprog
|
464 |
|
|
sodipodi:role="line"
|
465 |
|
|
x="1236.9219"
|
466 |
|
|
y="1073.1864"
|
467 |
|
|
id="tspan3390">Directorio de proyeecto (repo. SVN)
|
468 |
|
|
sodipodi:role="line"
|
469 |
|
|
x="1236.9219"
|
470 |
|
|
y="1099.8566"
|
471 |
|
|
id="tspan3384" />
|
472 |
|
|
|
473 |
|
|
|