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[/] [phr/] [trunk/] [doc/] [financiamiento/] [adec/] [informes/] [manual_usuario/] [ref/] [estructura_del_manual.svg] - Blame information for rev 109

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1 109 guanucolui
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         id="tspan3168">Caracteristicas generales
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         y="121.94328"
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         id="tspan3172"> --> Diagrama 3d identificación de sus partes.
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         id="tspan3232" />
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         x="256.83859"
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         y="158.84276"
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         id="tspan3234">Herramienta de software EDA
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         x="256.83859"
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         y="177.2925"
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         id="tspan3285"> --> KiCAD
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         x="256.83859"
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         y="195.74223"
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         id="tspan3289"> --> Acceder a los archivos del diseño
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         id="tspan3281">Dispositivos PLDs (CPLD, FPGA)
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         y="251.09145"
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         id="tspan3260"> --> Características tecnológicas
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         y="269.54117"
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         y="361.78986"
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         id="tspan3287"> --> Especificaciones para la FPGA del fabricante (Xilinx Inc.)
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         y="417.1391"
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         id="tspan3309">       --> Esquema de conexión en bloque (socket)
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         x="256.83859"
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         y="472.48831"
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         id="tspan3206">Componentes
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         id="tspan3182"> --> (Llaves,pulsadores,led, rs232,clks, etc).
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         id="tspan3184">       (por c/u)--> ubicación en placa (foto)
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         x="256.83859"
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         y="527.83752"
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         x="256.83859"
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         y="546.28723"
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         x="256.83859"
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         y="564.737"
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         id="tspan3188">                   --> conexión a puerto FPGA (siempre tabla)
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         id="tspan3176">Puerto JTAG
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         y="638.53595"
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         y="712.3349"
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         id="tspan3258"> --> consejo de uso "sano"
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         id="tspan2926-9-3">Caracteristicas HW/SW
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         id="tspan3119">Diagramas en bloques
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         x="1221.7596"
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         y="959.16742">Apéndice
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