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<!-- saved from url=(0054)http://arch.ece.gatech.edu/research/3dmaps/3dmaps.html -->
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<html><head><meta http-equiv="Content-Type" content="text/html; charset=UTF-8">
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<title>3D-MAPS Many-Core Processor</title>
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<meta name="keywords" content="3D IC, Georgia Tech, 3D MAPS, 3D architecture, 3-D IC, 3D-MAPS">
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<meta description="description" content="3D IC architecture research using die stacking and TSV at Georgia Tech">
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<meta name="author" content="Hsien-Hsin Lee">
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<font face="verdana" size="2">
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<h3>
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<font color="blue">
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The 3D-MAPS Many-Core Processor</font></h3>
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<h5>
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<font color="green">
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Announcements
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</font>
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</h5>
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<ul>
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<li> 10/24/11: We taped out 3D-MAPS V2 to MOSIS/Tezzaron MPW run.
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</li><li> 02/21/12: 3D-MAPS V1 is presented at ISSCC 2012. Here is our <a href="http://arch.ece.gatech.edu/pub/isscc12.pdf" target="new">
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paper</a> and <a href="http://arch.ece.gatech.edu/present/isscc12.pdf" target="new">presentation</a>.
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</li></ul>
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<h5>
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<font color="green">
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Media Coverages
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</font>
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</h5>
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<ul>
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<li> <a href="http://www.i-micronews.com/news/3D-MAPS-multicore-processor-closer-look,8706.html" target="new">3D-MAPS multicore processor: A closer look</a> (I-Micronews)
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</li><li> <a href="http://eda360insider.wordpress.com/2012/03/01/3d-thursday-three-on-3d-papers-from-isscc/" target="new">3D Thursday: Threee on 3D --- papers from ISSCC</a> (EDA360 Insider)
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</li><li> <a href="http://www.electroiq.com/blogs/insights_from_leading_edge/2012/04/iftle-97-date-in-dresden-synopsys-3d-eda-solution.html" target="new">3D EDA Solution</a> (Solid State Technology)
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</li><li> <a href="http://www.electroiq.com/blogs/insights_from_leading_edge/2012/03/iftle-93-2-5-3d-at-the-2012-ieee-isscc.html" target="new">IFTLE 93 2.5 / 3D at the 2012 IEEE ISSCC</a> (Solid State Technology)
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</li><li> <a href="http://www.eetimes.com/electronics-news/4236570/ISSCC--Picture-from-a-silicon-exhibition?pageNumber=1" target="new">ISSCC: Pictures from a silicon exhibition</a> (EE Times)
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</li><li> <a href="http://www.theregister.co.uk/2011/12/22/isscc_2012_chip_preview/" target="new">
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New chippery on parade at ISSCC: CPU and memory makers strut their stuff</a>
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(The Register)
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</li><li> <a href="http://www.theregister.co.uk/2012/02/24/3d_chips/page3.html" target="new">
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Real apps, real benchmarks. Georgia Institute of Technology's "3D-MAPS: 3D
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massively parallel processor with stacked memory"</a> (The Register)
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</li></ul>
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<h5>
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<font color="green">
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Overview
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</font>
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</h5>
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3D-MAPS (3D <u>MA</u>ssively <u>P</u>arallel processor with <u>S</u>tacked
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memory) V1 is a logic+memory 2-tier 3D IC, where the logic die consists of 64
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general purpose processor cores running at 277MHz, and the memory die contains
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256KB SRAM. <font color="red"> This 3D IC is arguably the FIRST many-core general
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purpose 3D processor developed in academia.</font> This 3D processor achieves up
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to 64GB/s memory bandwidth while consuming 5W power. This project is led by
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<a href="http://users.ece.gatech.edu/limsk/">Prof. Sung Kyu Lim</a> (PI) and <a href="http://users.ece.gatech.edu/~leehs/">Prof. Hsien-Hsin Lee</a> (co-PI) from the Georgia
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Institute of Technology and Dr. Gabriel Loh (co-PI) from AMD with funding from
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the US Department of Defense. There have been 20+ students involved in this
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project working on architecture, programming, CAD tools, circuit and physical
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design, packaging, board design, and testing. Our collaborators include KAIST,
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Tezzaron, Amkor Inc, and Board Lab.
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<p><img src="./3D-MAPS Many-Core Processor_files/team.JPG"></p><p>
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</p><p>The fabrication of this chip is completed in July 2011 using the 130nm
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GlobalFoundies device technology and 1.2um TSV diameter Tezzaron technology. The
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packaging is completed in August 2011 by Amkor. 8 parallel applications are
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developed to demonstrate the bandwidth and power benefit of 3D MAPS processor.
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This processor contains 33M transistors, 50K TSVs, and 50K face-to-face
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connections in 5mm x 5mm footprint and 0.8mm thickness.
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</p><p>The core architecture is developed from scratch by our architecture team to
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benefit from single-cycle access to SRAM. One of the two instructions we issue
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in one cycle can be memory read/write, so it is possible to access memory at
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every clock cycle. Our RTL-to-GDSII tool chain is based on commercial tools from
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Synopsys, Cadence, and Mentor Graphics. Since these tools can only handle 2D
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ICs, we have developed plug-ins to handle TSVs and 3D stacking.
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</p><p> Here is our <a href="http://arch.ece.gatech.edu/pub/cicc10.pdf" target="new">
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CICC 2010</a> and <a href="http://arch.ece.gatech.edu/pub/3dtest10.pdf" target="new">
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3D-TEST 2010</a> papers on 3D-MAPS V1.
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</p><p>We are currently working on 3D-MAPS V2 that features 128 cores and 2GB DRAM
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stacked in 5 dies. Here are the differences:</p><p>
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<table border="1">
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<tbody><tr>
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<td></td>
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<td align="center"><font color="blue">3D-MAPS V1</font></td>
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<td align="center"><font color="blue">3D-MAPS V2</font></td>
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</tr>
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<tr>
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<td># of tiers</td>
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<td align="center">2, one logic and one SRAM</td>
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<td align="center">5, two logic and three DRAM</td>
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</tr>
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<tr>
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<td># of cores</td>
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<td align="center">64</td>
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<td align="center">128</td>
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</tr>
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<tr>
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<td>logic footprint</td>
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<td align="center">5mm x 5mm</td>
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<td align="center">10mm x 10mm</td>
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</tr>
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<tr>
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<td>DRAM footprint</td>
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<td align="center">-</td>
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<td align="center">20mm x 12mm</td>
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</tr>
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<tr>
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<td>device technology</td>
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<td align="center">130nm, Globalfoundries</td>
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<td align="center">130nm, Globalfoundries</td>
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</tr>
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<tr>
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<td>bonding style</td>
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<td align="center">face-to-face</td>
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<td align="center">face-to-face & face-to-back</td>
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</tr>
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<tr>
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<td>TSV technology</td>
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<td align="center">Tezzaron, 1.2um diam</td>
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<td align="center">Tezzaron, 1.2um diam</td>
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</tr>
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</tbody></table>
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</p><h5>
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<font color="green">
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3D-MAPS V1 Specifications
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</font>
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</h5>
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<p><img src="./3D-MAPS Many-Core Processor_files/spec.jpg"></p><p>
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</p><h5>
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<font color="green">
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3D-MAPS V1 Measurement Results
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</font>
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</h5>
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3D-MAPS V1 supports 42 instructions, and we wrote 8 parallel applications and
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ran them on our chip. Here are the memory bandwidth and power measurement
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results.<p>
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<table border="1">
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<tbody><tr>
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<td>application</td>
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<td align="center">memory BW (GB/s)</td>
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<td align="center">power consumption (W)</td>
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</tr>
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<tr>
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<td>AES encryption</td>
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<td align="center">49.5</td>
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<td align="center">4.032</td>
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</tr>
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<tr>
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<td>edge detection</td>
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<td align="center">15.6</td>
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<td align="center">3.768</td>
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</tr>
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<tr>
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<td>histogram</td>
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<td align="center">30.3</td>
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<td align="center">3.588</td>
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</tr>
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<tr>
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<td>k-means clustering</td>
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<td align="center">40.6</td>
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<td align="center">4.014</td>
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</tr>
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<tr>
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<td>matrix multiply</td>
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<td align="center">13.8</td>
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<td align="center">3.789</td>
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</tr>
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<tr>
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<td>median filter</td>
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<td align="center"><font color="red">63.8</font></td>
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<td align="center"><font color="red">4.007</font></td>
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</tr>
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<tr>
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<td>motion estimation</td>
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<td align="center">24.1</td>
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<td align="center">3.830</td>
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</tr>
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<tr>
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<td>string search</td>
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<td align="center">8.9</td>
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<td align="center">3.876</td>
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</tr>
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</tbody></table>
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</p><p>The theoretical maximum memory bandwidth 3D-MAPS V1 can achieve is 70.9GB/s,
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which is computed by 277MHz x 64 (cores) x 4 Bytes (1 word). One of our
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applications, median filter, got very close to this theoretical value at the
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lowest power consumption. As a comparison, here are the maximum achievable
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bandwidth values of the state-of-the-art processor and memory technology (as of
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Sep 2011):
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</p><ul>
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<li> Intel i7 Extreme Edition + Samsung DDR3 1600 MHz = 1600 MHz x 2 ch x 8
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Bytes = 25.6 GB/s
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</li><li> Intel Xeon E7 + Samsung DDR3 1066 MHz = 1066 MHz x 4 ch x 8 Bytes = 34.1
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GB/s
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</li></ul>
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3D-MAPS V1 is fabricated in 130nm technology in 5mm x 5mm footprint. If 3D-MAPS
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V1 is fabricated in 45nm in 15mm x 15mm footprint (as in Intel i7), the maximum
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memory bandwidth skyrockets as follows:
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<ul>
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<li> 277 MHz X 5 (speedup from 45nm) x 64 ch x 9 (more area) x 4 (smaller cores)
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x 4 Bytes = <font color="red">12,764 GB/s</font>
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</li></ul>
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This truly demonstrates the enormous memory bandwidth benefit of core+memory 3D
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IC.
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<h5>
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<font color="green">
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3D-MAPS V1 Photos
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</font>
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</h5>
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<font color="blue">
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<img src="./3D-MAPS Many-Core Processor_files/3D-MAPS-V1-fig8.jpg"><br>FIGURE 1: This is the stacking information of
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3D-MAPS V1. We use bonding wires and TSVs for the package-to-chip signal and P/G
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delivery. Chip-to-chip communication is done using F2F pads. The bonding wires
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did not break the TSVs underneath during manufacturing. Each IO cell contains
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204 redundant TSVs.<p>
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<img src="./3D-MAPS Many-Core Processor_files/3D-MAPS-V1-fig1.JPG"><br><font color="blue">FIGURE 2: The topside of
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3D-MAPS V1 is actually the backside of the core die that is thinned down to
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12um. With bare eyes, we can only see dummy TSVs and IO cells.</font></p><p><font color="blue">
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<img src="./3D-MAPS Many-Core Processor_files/3D-MAPS-V1-fig3.JPG"><br>FIGURE 3: SEM image of Tezzaron TSVs and
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face-to-face bond pads.</font></p><p><font color="blue">
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<img src="./3D-MAPS Many-Core Processor_files/3D-MAPS-V1-fig10.jpg"><br>FIGURE 4: More SEM images of TSVs and F2F
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pads.</font></p><p><font color="blue">
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<img src="./3D-MAPS Many-Core Processor_files/3D-MAPS-V1-fig4.png"><br>FIGURE 5: The above image is obtained using an
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infrared microscope with 6um depth. Since the top surface of 3D-MAPS V1 is the
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thinned substrate of top die, we had to use an IR microscope to reveal the
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circuitry that is buried under this substrate. The white dots are dummy TSVs we
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had to add to satisfy the TSV density rule set by Tezzaron.</font></p><p><font color="blue">
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<img src="./3D-MAPS Many-Core Processor_files/3D-MAPS-V1-fig7.jpg"><br>FIGURE 6: Some details of single core and
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single IO cell.</font></p><p><font color="blue">
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<img src="./3D-MAPS Many-Core Processor_files/3D-MAPS-V1-fig2.JPG"><br>FIGURE 7: Bare die and its package
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side-by-side.</font></p><p><font color="blue">
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<img src="./3D-MAPS Many-Core Processor_files/3D-MAPS-V1-fig5.JPG"><br>FIGURE 8: The open TSV above, fortunately, does
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not cause any problem because all of the TSVs shown are redundant. The top die
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(= core die) is thinned down to 12um, and the bottom die (= memory die) height
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is 765um, making the total thickness to be roughly 0.8mm.</font></p><p><font color="blue">
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<img src="./3D-MAPS Many-Core Processor_files/3D-MAPS-V1-fig6.JPG"><br>FIGURE 9: A dummy TSV</font></p><p><font color="blue">
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<img src="./3D-MAPS Many-Core Processor_files/3D-MAPS-V1-fig9.jpg"><br>FIGURE 10: Layouts of full-die (core and
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memory) and single core/memory tile.</font></p><p><font color="blue">
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</font>
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</p><p>
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<img src="./3D-MAPS Many-Core Processor_files/Count.cgi">
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</p></font><p><font color="blue">
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</p></font></body></html>
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