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% $Id: schedule.tex 227 2014-04-14 14:03:54Z guanucoluis $
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\documentclass[11pt,a4paper,oneside]{article}
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\usepackage[utf8]{inputenc}
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\title{Plataforma de hardware reconfigurable \\ \small{Armado final - Observaciones}}
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\author{Luis A. Guanuco}
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\date{Noviembre 2014\\\scriptsize{$LastChangedRevision: 410 $}}
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\pagestyle{fancy}
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\addtolength{\textheight}{2cm}
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%\addtolength{\voffset}{-1cm}
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%\addtolength{\textwidth}{1cm}
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\begin{document}
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\maketitle{}
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%\chead{\includegraphics[width=0.1\textwidth]{images/logov2_ES}}
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\begin{figure}[h]
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\centering
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\includegraphics[width=0.3\textwidth]{images/logov2_ES}
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\end{figure}
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\tableofcontents{}
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\section{Introducción}
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Se realiza una nota con observaciones sobre el armado de las placas
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finales. El servicio de soldado fue realizado por el laboratorio SMT
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de la CIIECCA\footnote{http://ciiecca.org.ar/servicios/cst-y-smt/}.
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\section{Placa PHR}
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\label{sec:armado}
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\subsection{Componentes faltantes}
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Cada placa tiene una numeración de la forma \textbf{\texttt{01}}. Y a
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cada una de estas placas se detallarán los componentes que no se
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encuentran montados.
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\begin{table}[H]
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\centering
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\begin{tabular}{|l | c | c | c | c |}
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\hline
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Placa & \texttt{P3} (JTAG) & \texttt{P2} (GPIO) &
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\texttt{push1}(prog) & \texttt{Q1,Q1} (7-seg) \\
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\hline \hline
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\texttt{01} & $\checkmark$ & $\checkmark$ & & \\
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\hline
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\texttt{02} & $\checkmark$ & $\checkmark$ & & \\
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\hline
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\texttt{03} & $\checkmark$ & $\checkmark$ & $\checkmark$ & \\
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\hline
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\texttt{04} & $\checkmark$ & $\checkmark$ & $\checkmark$ & \\
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\hline
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\texttt{05} & $\checkmark$ & $\checkmark$ & $\checkmark$ &
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$\checkmark$ \\
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\hline
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\texttt{06} & $\checkmark$ & $\checkmark$ & $\checkmark$ &
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$\checkmark$ \\
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\hline
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\end{tabular}
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\end{table}
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\subsection{Malas soldaduras}
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Las placas \emph{PHRboard} tienen varios componentes con polaridad invertida. La Tabla \ref{tab:sold-invert} describe los componentes a corregir por placa.
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\begin{table}[H]
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\centering
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\begin{tabular}{|l | c | c | c | c | c | c |}
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\hline
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Placa & \texttt{Ca10} & \texttt{Co16} & \texttt{Ci16}
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& \texttt{D1} & \texttt{D2} & \texttt{LED1-LED8}\\
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\hline \hline
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\texttt{01} & $\checkmark$ & $\checkmark$ & $\checkmark$ &
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$\checkmark$ & $\checkmark$ & \\
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\hline
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\texttt{02} & $\checkmark$ & $\checkmark$ & $\checkmark$ &
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$\checkmark$ & $\checkmark$ & \\
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\hline
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\texttt{03} & & $\checkmark$ & & & $\checkmark$ & $\checkmark$\\
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\hline
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\texttt{04} & & $\checkmark$ & & & $\checkmark$ & $\checkmark$\\
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\hline
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\texttt{05} & & $\checkmark$ & & & $\checkmark$ & $\checkmark$\\
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\hline
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\texttt{06} & & $\checkmark$ & & & $\checkmark$ & $\checkmark$\\
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\hline
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\hline
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\end{tabular}
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\end{table}
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\subsection{Versiones corregidas}
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Los errores presentes en las versiones recibidas por el laboratorio
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SMT fueron corregidas por los desarrolladores Maximiliano Quinteros y
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Julio Vilca. A continuación se describe las observaciones de cada
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caso,
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\begin{table}[H]
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\centering
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\begin{tabular}{| c | c | l |}
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\hline
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Placa & Estado & Observaciones \\
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\hline \hline
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\texttt{01} & $\checkmark$ & Ninguna. \\
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\hline
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\texttt{02} & $\checkmark$ & Ninguna. \\
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\hline
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\texttt{03} & $\checkmark$ & Tenía problema en \texttt{PBTN3}(cambiado).\\
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\hline
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\texttt{04} & $\checkmark$ & La llave 3 del dip switch
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(\texttt{SWITCHES}) tiene mayor sensibilidad. Se decide aceptarlo. \\
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\hline
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\texttt{05} & $\checkmark$ & Ninguna. \\
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\hline
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\texttt{06} & $\checkmark$ & Ninguna. \\
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\hline
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\texttt{07} & $\checkmark$ & \\
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\hline
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\texttt{08} & $\checkmark$ & \\
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\hline
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\texttt{09} & $\checkmark$ & \\
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\hline
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\hline
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\end{tabular}
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\end{table}
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Las placas \texttt{07} y \texttt{08} son consideradas de respaldo para
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cualquier inconveniente que presenten las placas que se encontrarán en
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uso en el laboratorio LTDI.
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\newpage{}
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\clearpage{}
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\begin{thebibliography}{}
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\bibitem{schedule_2012-08-24} Luis A. Guanuco, ``Plataforma de hardware reconfigurable (Armado - Testeo y Documentación de las placas de prototipaje)'', Agosto 2012, 2.3.4.~FPGA (PHR version BETA), 8~p.
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\bibitem{openocd-manual-autoprobing} \ac{openocd}, ``\ac{openocd} User's Guide'', 25 de Noviembre del 2012, 10.7~Autoprobing, 58~p., Versión 0.7.0-dev
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\bibitem{schedule_2012-03-20} Luis A. Guanuco, ``Plataforma de hardware reconfigurable (JTAG -- Configuración OOCD-Links, (Hardware \& Software)'', Marzo 2013.
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\end{thebibliography}
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\newpage{}
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\clearpage{}
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\appendix{}
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\section{Acrónimos}
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\begin{acronym}
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\acro{CIECCA}{Cámara de Industrias Informáticas, Electrónicas y de
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Comunicaciones del Centro de Argentina}
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\end{acronym}
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\section{Repositorio de proyecto}
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El proyecto se encuentra alojado en los servidores de \emph{OpenCores}. Por lo que se puede acceder a los repositorios mediante el siguiente link, \texttt{http://opencores.org/project,phr}
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De todas formas se pueden comunicar por correo, \texttt{guanucoluis@gmail.com}.
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\end{document}
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