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[/] [phr/] [trunk/] [doc/] [informe-tesis/] [reports/] [catedra-proy-final/] [ante-tesis/] [esquema.svg] - Blame information for rev 272

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           id="flowPara3074">El desarrollo tecnológico resulta fundamental para un país y más aún cuando se cuenta con recursos humanos capacitados en ésta área. Éste sostenido crecimiento se debe acompañar con recursos físicos que permitan afianzar ésta tendencia. Desde el grupo de investigación CUDAR se propone ésta meta  y genera tecnología que pueda ser utilizada en la Universidad.
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           id="flowPara3074-8">El presente trabajo de tesis se enfoca en el ámbito académico, una plataforma educativa abierta para el desarrollo de descripción de hardware en una dispositivo FPGA. Se presenta dicha situación al Departamento de Ingeniería Electrónica con el fin de realizar la transferencia de tecnología desde el Centro de Desarrollo en Automoción y Robótica “CUDAR” y el Laboratorio de Técnicas Digitales e Informática “LTDI”.
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         style="font-style:normal;font-variant:normal;font-weight:normal;font-stretch:normal;font-family:LMRoman9;-inkscape-font-specification:LMRoman9">Guanuco Luis
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437 
         style="font-style:normal;font-variant:normal;font-weight:normal;font-stretch:normal;font-family:LMRoman9;-inkscape-font-specification:LMRoman9">Centro Universitario de Desarrollo en Automación y Robótica “CUDAR”
438 
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         style="font-style:normal;font-variant:normal;font-weight:normal;font-stretch:normal;font-family:LMRoman9;-inkscape-font-specification:LMRoman9">Universidad Tecnológica Nacional - FRC
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444 
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         style="font-style:normal;font-variant:normal;font-weight:normal;font-stretch:normal;font-family:LMRoman9;-inkscape-font-specification:LMRoman9">Córdoba, Argentina
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460 
         ry="9.8888741"
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         y="551.30151"
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468 
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           sodipodi:role="line">JTAG
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480
481 
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       transform="matrix(1.4287312,0,0,1.4287312,-85.894338,-493.2412)"
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       inkscape:export-xdpi="333"
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       inkscape:export-ydpi="333">
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486 
         ry="12.632258"
487 
         y="137.33469"
488 
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         height="324.76913"
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         width="496.60239"
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494 
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501 
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           sodipodi:role="line">Placa Base
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506 
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507
508 
           id="g3334"
509 
           transform="translate(-198.28151,-242.27824)">
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511 
             ry="6.2614241"
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             y="458.94351"
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             x="1010.8688"
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             height="26.029432"
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526 
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527 
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528 
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529 
               sodipodi:role="line">Llaves
530
531
532 
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           transform="matrix(1.2774213,0,0,1.2774213,993.967,-426.3175)">
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535 
             ry="9.8888741"
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             y="491.43539"
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543 
             sodipodi:linespacing="100%"
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             id="text2816-4-6-9"
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             y="641.73395"
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549 
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550 
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551 
               x="27.971724"
552 
               id="tspan2818-6-3-0"
553 
               sodipodi:role="line">Placa FPGA
554
555
556 
           id="g3373"
557 
           transform="translate(-91.127166,-267.54803)">
558
559 
             ry="6.2614241"
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             y="425.74481"
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574 
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576 
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577 
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578
579
580 
           id="g3412"
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583 
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               id="tspan2818-6-7-2-4"
601 
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602
603
604 
           id="g3451"
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           transform="translate(-95.600844,-99.58157)">
606
607 
             ry="6.2614241"
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             y="456.08017"
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623 
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624 
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625 
               sodipodi:role="line">Pulsadores
626
627
628 
           id="g3529"
629 
           transform="translate(-49.053131,-54.973049)">
630
631 
             ry="6.2614241"
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             y="411.47165"
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639 
             sodipodi:linespacing="100%"
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644 
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646 
               y="428.54257"
647 
               x="1202.9515"
648 
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649 
               sodipodi:role="line">USB-Prog
650
651
652 
           id="g3568"
653 
           transform="translate(-83.004393,144.95527)">
654
655 
             ry="6.2614241"
656 
             y="270.25702"
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662
663 
             sodipodi:linespacing="100%"
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             id="text2816-4-5-9-8-3"
665 
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             x="1160.1769"
667 
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668 
             xml:space="preserve">
669 
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670 
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671 
               x="1160.1769"
672 
               id="tspan2818-6-7-2-1-4"
673 
               sodipodi:role="line">RS-232
674
675
676 
           id="g3607"
677 
           transform="translate(-19.454986,-36.353836)">
678
679 
             ry="6.2614241"
680 
             y="253.0191"
681 
             x="1160.6952"
682 
             height="26.029432"
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             width="97.528923"
684 
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686
687 
             sodipodi:linespacing="100%"
688 
             id="text2816-4-5-9-8-3-9"
689 
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690 
             x="1169.3773"
691 
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692 
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693 
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694 
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695 
               x="1169.3773"
696 
               id="tspan2818-6-7-2-1-4-6"
697 
               sodipodi:role="line">Conv. A/D
698
699
700 
           id="g3646"
701 
           transform="translate(-15.368072,4.338079)">
702
703 
             ry="6.2614241"
704 
             y="281.45886"
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             x="1156.6083"
706 
             height="26.029432"
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710
711 
             sodipodi:linespacing="100%"
712 
             id="text2816-4-5-9-8-3-9-4"
713 
             y="298.53793"
714 
             x="1165.098"
715 
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716 
             xml:space="preserve">
717 
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718 
               y="298.53793"
719 
               x="1165.098"
720 
               id="tspan2818-6-7-2-1-4-6-7"
721 
               sodipodi:role="line">Conv. D/A
722
723
724 
           id="g3719"
725 
           transform="translate(-13.75038,-37.252833)">
726
727 
             ry="6.2614241"
728 
             y="323.04977"
729 
             x="826.33765"
730 
             height="26.029432"
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             width="97.528923"
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             id="rect2971-8-3-7-6"
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734
735 
             sodipodi:linespacing="100%"
736 
             id="text2816-4-5-9-2-1-2"
737 
             y="340.12885"
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             x="829.44714"
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740 
             xml:space="preserve">
741 
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742 
               y="340.12885"
743 
               x="829.44714"
744 
               id="tspan2818-6-7-2-4-4-7"
745 
               sodipodi:role="line">I/O Aislados
746
747
748 
           id="g3765"
749 
           transform="translate(-267.7814,53.677679)">
750
751 
             ry="6.2614241"
752 
             y="361.53461"
753 
             x="1178.9431"
754 
             height="26.029432"
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             width="97.528923"
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             id="rect2971-8-6-5"
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             style="fill:none;stroke:#000000;stroke-width:1.46099901;stroke-opacity:1" />
758
759 
             sodipodi:linespacing="100%"
760 
             id="text2816-4-5-9-8-5"
761 
             y="378.60553"
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             x="1179.5891"
763 
             style="font-size:65.02957916px;font-style:normal;font-weight:normal;text-align:start;line-height:100%;writing-mode:lr-tb;text-anchor:start;fill:#000000;fill-opacity:1;stroke:none;font-family:Bitstream Vera Sans"
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             xml:space="preserve">
765 
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766 
               y="378.60553"
767 
               x="1179.5891"
768 
               id="tspan2818-6-7-2-1-6"
769 
               sodipodi:role="line">Conector I/O
770 
               id="tspan3763"
771 
               style="font-size:16.25739479px;font-style:normal;font-variant:normal;font-weight:normal;font-stretch:normal;text-align:start;line-height:100%;writing-mode:lr-tb;text-anchor:start;font-family:LMRoman10;-inkscape-font-specification:LMRoman10"
772 
               y="394.86292"
773 
               x="1179.5891"
774 
               sodipodi:role="line" />
775
776
777 
           id="g3828"
778 
           transform="translate(-271.77222,-17.79461)">
779
780 
             style="fill:#b3b3b3;stroke:#000000;stroke-width:1.46099913;stroke-opacity:1"
781 
             id="rect2847-2"
782 
             width="72.315758"
783 
             height="72.315758"
784 
             x="1297.3798"
785 
             y="301.53839"
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             ry="12.632258" />
787
788 
             xml:space="preserve"
789 
             style="font-size:65.02957916px;font-style:normal;font-weight:normal;text-align:start;line-height:100%;writing-mode:lr-tb;text-anchor:start;fill:#000000;fill-opacity:1;stroke:none;font-family:Bitstream Vera Sans"
790 
             x="1310.2152"
791 
             y="343.33759"
792 
             id="text2816-4-4-9"
793 
             sodipodi:linespacing="100%">
794 
               sodipodi:role="line"
795 
               x="1310.2152"
796 
               y="343.33759"
797 
               style="font-size:16.25739479px;font-style:normal;font-variant:normal;font-weight:normal;font-stretch:normal;text-align:start;line-height:100%;writing-mode:lr-tb;text-anchor:start;font-family:LMRoman10;-inkscape-font-specification:LMRoman10"
798 
               id="tspan3168">FPGA
799
800
801 
           id="g3210"
802 
           transform="matrix(1.2774213,0,0,1.2774213,1314.397,-347.97879)">
803
804 
             ry="9.8888741"
805 
             y="509.51373"
806 
             x="-280.77817"
807 
             height="36.623817"
808 
             width="41.762978"
809 
             id="rect2901-0-2"
810 
             style="fill:none;stroke:#000000;stroke-width:1.14370966;stroke-opacity:1" />
811
812 
             sodipodi:linespacing="100%"
813 
             id="text2816-4-8-8-2"
814 
             y="532.17181"
815 
             x="-276.06598"
816 
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817 
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