OpenCores
URL https://opencores.org/ocsvn/phr/phr/trunk

Subversion Repositories phr

[/] [phr/] [trunk/] [doc/] [informe-tesis/] [reports/] [schedule_2012-08-24/] [schedule.tex] - Blame information for rev 423

Go to most recent revision | Details | Compare with Previous | View Log

Line No. Rev Author Line
1 61 guanucolui 
%$Id $
2 
\documentclass[11pt,a4paper,oneside]{article}
3 
\usepackage[utf8]{inputenc}
4 
\usepackage[spanish]{babel}
5 
\usepackage{graphicx}
6 62 guanucolui 
\usepackage{multicol}
7 
\usepackage{balance}
8 61 guanucolui 
%\usepackage{subfig}
9 
%\usepackage[cm]{fullpage}
10 
\usepackage[a4paper]{geometry}
11 
%\usepackage{subfigure}
12 
\usepackage{float}
13 
\usepackage{fancyhdr}
14 
\usepackage{caption}
15 
\usepackage{subcaption}
16 120 guanucolui 
\title{Plataforma de hardware reconfigurable \\ \small{Armado - Testeo y Documentación de las placas de prototipaje}}
17 61 guanucolui 
\author{Luis A. Guanuco}
18 
\date{Agosto 2012}
19 
\pagestyle{fancy}
20 
\addtolength{\textheight}{2cm}
21 
%\addtolength{\voffset}{-1cm}
22 
%\addtolength{\textwidth}{1cm}
23 
 
24 
\begin{document}
25 
 
26 
\maketitle{}
27 
 
28 125 guanucolui 
%\chead{\includegraphics[width=0.1\textwidth]{images/logov2_ES}}
29 
\begin{figure}[h]
30 
  \centering
31 
  \includegraphics[width=0.3\textwidth]{images/logov2_ES}
32 
\end{figure}
33 61 guanucolui 
 
34 
\section{Introducción}
35 
\label{sec:intro}
36 
 
37 
La documentación que se presenta en éste reporte describe los pasos a seguir para el \emph{armado, testéo y depuración} de las distintas placas que conformarán la \emph{Plataforma de Hardware Reconfigurable -- PHR}.
38 
Se presenta un esquema general de tres etapas, sin embargo, cada una de ellas presenta una complejidad diferente.
39 
 
40 
\begin{figure}[h]
41 
  \centering
42 
  \includegraphics[width=0.6\textwidth]{images/esquema1}
43 
  \caption{Esquema de trabajo a seguir.}
44 
\end{figure}
45 
 
46 
\section{Armado}
47 
\label{sec:armado}
48 
 
49 
\subsection{Placas}
50 
\label{sec:placas}
51 
 
52 
Actualmente se dispone de cuatro placas PCB, ellas son:
53 
\begin{itemize}
54 
\item OT-CPLD
55 
\item OOCD Links (USB/JTAG)
56 
\item S3Power (INTI)
57 
\item FPGA (PHR version BETA)
58 
\end{itemize}
59 
Cada una de éstas placas se encuentra en una versión de \emph{Prototipaje}, lo que implica que su finalidad es únicamente de \emph{testéo} y generar \emph{documentación} que permitan el desarrollo de sus versiones finales, con las correcciones pertinentes.
60 
 
61 
\subsection{Recursos}
62 
\label{sec:recursos}
63 
 
64 
Se adjunta a la presente documentación la lista de componentes a utilizar.
65 
 
66 
\subsection{Placas}
67 
\label{sec:process}
68 
Los esquemáticos se adjuntan al final del documento pero aquí se hace presente a modo de ilustración y que se pueda relacionar con sus correspondientes esquemas PCB.
69 
 
70 
Se recomienda tener cuidado en el proceso de ensamblado/soldado de los componentes. La mayoría de los mismos son SMD, por lo que puede prestarse a confusiones la polarización de capacitores y diodos, como así también la magnitud de cada uno.
71 
 
72 
Se presentan las figuras de cada placa, haciendo énfasis en diferentes vistas con la finalidad de facilitar el armado de las mismas.
73 
 
74 
\subsubsection{OT-CPLD}
75 
La placa \textsl{OT-CPLD} tan solo realiza la adaptación de los pines de un CPLD (XC9572XL) a un formato DIP-40 (40 pines) a fines de ser utilizado en cualquier protoboard. Junto a las dos hileras de pines, la placa contiene un reguladore de tensión para el dispositivo lógico; y un puerto de conexión al interface JTAG del CPLD.
76 
\begin{figure}[H]
77 
  \centering
78 
  \includegraphics[width=\textwidth]{images/ot-cpld_sch}
79 
  \caption{Esquemático}
80 
\end{figure}
81 
\begin{figure}[H]
82 
  \begin{subfigure}[b]{\textwidth}
83 
    \centering
84 
    \includegraphics[width=\textwidth]{images/ot-cpld_brd_top}
85 
    \caption{Top}
86 
  \end{subfigure}
87 
  \begin{subfigure}[b]{\textwidth}
88 
    \centering
89 
    \includegraphics[width=\textwidth]{images/ot-cpld_brd_botton}
90 
    \caption{Botton}
91 
  \end{subfigure}
92 
  \begin{subfigure}[b]{\textwidth}
93 
    \centering
94 
    \includegraphics[width=\textwidth]{images/ot-cpld_brd_top_and_botton}
95 
    \caption{Top \& Botton}
96 
  \end{subfigure}
97 
  \caption{PCB}
98 
\end{figure}
99 
\newpage{}
100 
\subsubsection{OOCD Links}
101 
 
102 
La placa \textsl{OOCD Links} permite acceder a un interface JTAG mediante un puerto USB (hardware \& software). Nacido como un interface para el testéo de hardware mediante software, JTAG se ha convertido en un core clave en la programación de muchos dispisitivos actuales como son FPGAs, CPLDs, $\mu$Cs, $\mu$Ps, etc.
103 
La placa contiene un dispositivo central (FT2232), quién realiza la conversión de los protocolos en forma bidireccional. Los demás bloque simplemente hacen al funcionamiento del FT2232.
104 
\begin{figure}[H]
105 
  \begin{subfigure}{\textwidth}
106 
    \centering
107 
    \includegraphics[width=\textwidth]{images/oocd-links_sch_1}
108 
    \caption{FT2232, IC dispositivo interface USB/JTAG}
109 
  \end{subfigure}
110 
  \caption{Esquemático}
111 
\end{figure}
112 
\begin{figure}[H]
113 
  \addtocounter{figure}{-1}
114 
  \setcounter{subfigure}{1}
115 
  \begin{subfigure}{\textwidth}
116 
    \centering
117 
    \includegraphics[width=\textwidth]{images/oocd-links_sch_2}
118 
    \caption{Periféricos}
119 
  \end{subfigure}
120 
  \caption{Esquemático (Continuación)}
121 
\end{figure}
122 
 
123 
\begin{figure}[H]
124 
\begin{subfigure}[b]{0.5\textwidth}
125 
    \centering
126 
    \includegraphics[width=\textwidth]{images/oocd-links_brd_top}
127 
    \caption{Top}
128 
  \end{subfigure}
129 
  \begin{subfigure}[b]{0.5\textwidth}
130 
    \centering
131 
    \includegraphics[width=\textwidth]{images/oocd-links_brd_botton}
132 
    \caption{Botton}
133 
  \end{subfigure}
134 
  \caption{PCB}
135 
\end{figure}
136 
 
137 
\begin{figure}[H]
138 
  \addtocounter{figure}{-1}
139 
  \setcounter{subfigure}{2}
140 
  \begin{subfigure}[b]{\textwidth}
141 
    \centering
142 
    \includegraphics[width=0.5\textwidth]{images/oocd-links_brd_top_and_botton}
143 
    \caption{Top \& Botton}
144 
  \end{subfigure}
145 
  \caption{PCB (Continuación)}
146 
\end{figure}
147 
 
148 
\subsubsection{S3Power}
149 
 
150 
La placa \textsl{S3Power} fue diseñada por un los miembros del \textbf{INTI}, originalmente destinada a la placa \textbf{S3Proto}, y liberada con licencia \textsl{GPL (General Public License)} en la web \texttt{fpgalibre.sourceforce.net}.
151 
Las características eléctricas, en particular, de potencia son muy importantes debido a los distintos niveles de tensión que manejan las FPGAs que se utilizarán. Texas Instruments ha desarrollado un IC (TPS75003) específico para la familia de las FPGA de Xilinx (Spantan 3 - Xilinx Inc). Aquí se resuelven los tiempos de encendido como la regulación en el consumo de potencia de la FPGA.
152 
\begin{figure}[H]
153 
  \centering
154 
  \includegraphics[width=\textwidth]{images/s3power_sch}
155 
  \caption{Esquemático}
156 
\end{figure}
157 
 
158 
\begin{figure}[H]
159 
  \begin{subfigure}[b]{0.5\textwidth}
160 
    \centering
161 
    \includegraphics[width=\textwidth]{images/s3power_brd_top}
162 
    \caption{Top}
163 
  \end{subfigure}
164 
  \begin{subfigure}[b]{0.5\textwidth}
165 
    \centering
166 
    \includegraphics[width=\textwidth]{images/s3power_brd_botton}
167 
    \caption{Botton}
168 
  \end{subfigure}
169 
%  \caption{PCB}
170 
%\end{figure}
171 
%
172 
%\begin{figure}[H]
173 
%  \addtocounter{figure}{-1}
174 
%  \setcounter{subfigure}{2}
175 
  \begin{subfigure}[b]{\textwidth}
176 
    \centering
177 
    \includegraphics[width=0.5\textwidth]{images/s3power_brd_top_and_botton}
178 
    \caption{Top \& Botton}
179 
  \end{subfigure}
180 
  \caption{PCB}%(Continuación)}
181 
\end{figure}
182 
 
183 
\newpage{}
184 
\subsubsection{FPGA (PHR \small{version BETA})}
185 
 
186 
La placa \textsl{FPGA} que se presenta a continuación, es una versión prototipo que de la placa \textbf{PHR} final. La versión BETA pretende realizar un testeo de las características de potencia y el interface al puerto JTAG que dispone el dispositivo programable. Para la alimentación del mismo, se utiliza la placa \textbf{S3power} que se ha descrito en puntos anteriores.
187 
 
188 
\begin{figure}[H]
189 
  \begin{subfigure}{\textwidth}
190 
    \centering
191 
    \includegraphics[width=\textwidth]{images/fpga_sch_1}
192 
    \caption{FPGA (XC3S50A) \& Memoria de programación (XCF01S)}
193 
  \end{subfigure}
194 
  \caption{Esquemático}
195 
\end{figure}
196 
\begin{figure}[H]
197 
  \addtocounter{figure}{-1}
198 
  \setcounter{subfigure}{1}
199 
  \begin{subfigure}{\textwidth}
200 
    \centering
201 
    \includegraphics[width=0.6\textwidth]{images/fpga_sch_2}
202 
    \caption{Circuito de potencia (Placa S3power)}
203 
  \end{subfigure}
204 
  \caption{Esquemático (Continuación)}
205 
\end{figure}
206 
 
207 
\begin{figure}[H]
208 
\begin{subfigure}[b]{0.5\textwidth}
209 
    \centering
210 
    \includegraphics[width=\textwidth]{images/fpga_brd_top}
211 
    \caption{Top}
212 
  \end{subfigure}
213 
  \begin{subfigure}[b]{0.5\textwidth}
214 
    \centering
215 
    \includegraphics[width=\textwidth]{images/fpga_brd_botton}
216 
    \caption{Botton}
217 
  \end{subfigure}
218 
  \caption{PCB}
219 
\end{figure}
220 
 
221 
\begin{figure}[H]
222 
  \addtocounter{figure}{-1}
223 
  \setcounter{subfigure}{2}
224 
  \begin{subfigure}[b]{\textwidth}
225 
    \centering
226 
    \includegraphics[width=0.5\textwidth]{images/fpga_brd_top_and_botton}
227 
    \caption{Top \& Botton}
228 
  \end{subfigure}
229 
  \caption{PCB (Continuación)}
230 
\end{figure}
231 
 
232 
\section{Documentación}
233 
 
234 
La documentación resulta fundamental en ésta etapa del desarrollo. Si bien se quiere lograr el correcto funcionamiento de las placas, la documentación sirve para realizar correciones a las versiones futuras de cada placa. Otro objetivo es documentar el funcionamiento de cada dispositivo que sirvan al reporte final como así también a los usuarios de la \emph{Plataforma de Hardware Reconfigurable}.
235 
\newpage{}
236 
\appendix{}
237 
\section{Repositorio de proyecto}
238 
 
239 
El proyecto se encuentra alojado en los servidores de \emph{OpenCores}. Por lo que se puede acceder a los repositorios mediante el siguiente link, \texttt{http://opencores.org/project,phr}
240 
De todas formas se pueden comunicar por correo, \texttt{guanucoluis@gmail.com}.
241 
 
242 
\section{Archivos a conciderar}
243 
Se dispone de varios archivos relacionados con esta etapa de ensamblado y testeo.
244 
 
245 
\begin{verbatim}
246 
luis@luis-laptop:to_print$ ls -lX
247 
total 2872
248 
-rw-r--r-- 1 luis luis    1421 jul 10 16:38 cpld.cmp
249 
-rw-r--r-- 1 luis luis    4599 jul 10 17:09 fpga.cmp
250 
-rw-r--r-- 1 luis luis    6126 ago 28 21:34 OOCD_placa.cmp
251 
-rw-r--r-- 1 luis luis    4159 jul 10 16:40 S3Proto_Power.cmp
252 
-rw-r--r-- 1 luis luis  234181 ago 28 21:29 fpga_brd.pdf
253 
-rw-r--r-- 1 luis luis  137037 ago 28 21:55 fpga_sch.pdf
254 
-rw-r--r-- 1 luis luis  177723 ago 28 21:23 OOCD-Links_brd.pdf
255 
-rw-r--r-- 1 luis luis   88397 ago 28 21:55 OOCD-Links_sch.pdf
256 
-rw-r--r-- 1 luis luis  145699 ago 28 21:04 ot-cpld_brd.pdf
257 
-rw-r--r-- 1 luis luis   55105 ago 28 21:55 ot-cpld_sch.pdf
258 
-rw-r--r-- 1 luis luis  121516 ago 28 21:17 S3Proto_Power_brd.pdf
259 
-rw-r--r-- 1 luis luis   63912 ago 28 00:40 S3Proto_Power_sch.pdf
260 
-rw-r--r-- 1 luis luis 1520722 ago 28 20:39 schedule.pdf
261 
-rw-r--r-- 1 luis luis   57478 ago 28 21:35 cpld.png
262 
-rw-r--r-- 1 luis luis   86035 ago 28 21:37 fpga.png
263 
-rw-r--r-- 1 luis luis   66724 ago 28 21:33 OOCD_placa.png
264 
-rw-r--r-- 1 luis luis   70647 ago 28 21:36 S3Proto_Power.png
265 
\end{verbatim}
266 
 
267 
En estos archivos se tiene las figuras presentadas en las anteriores secciones pero con mejor resolución, estos terminan en \texttt{\_sch} o \texttt{\_brd} correspondientes a si se trata del esquemático o el PCB, respectivamente. También se tiene los archivos \texttt{.cmp}, los que contienen la lista de componentes a utilizar y su referencia en el esquemático como así también el encapsulado. Los archivos \texttt{.png} son las distintas placas vista en 3D para tener una idea de como debería quedar al finalizar el desarrollo.
268 62 guanucolui 
\newpage
269 
\section{Lista de componentes}
270 
 
271 
\subsection{OT-CPLD}
272 
 
273 
\begin{multicols}{2}
274 
\begin{verbatim}
275 
BeginCmp
276 
TimeStamp = /4EA65376;
277 
Reference = C1;
278 
ValeurCmp = 1uF;
279 
IdModule  = SM0603;
280 
EndCmp
281 
 
282 
BeginCmp
283 
TimeStamp = /4EA6543A;
284 
Reference = C2;
285 
ValeurCmp = 1uF;
286 
IdModule  = SM0603;
287 
EndCmp
288 
 
289 
BeginCmp
290 
TimeStamp = /4EA882B4;
291 
Reference = C3;
292 
ValeurCmp = .1uF;
293 
IdModule  = SM0603;
294 
EndCmp
295 
 
296 
BeginCmp
297 
TimeStamp = /4EA882BB;
298 
Reference = C4;
299 
ValeurCmp = .01uF;
300 
IdModule  = SM0603;
301 
EndCmp
302 
 
303 
BeginCmp
304 
TimeStamp = /4EA882C2;
305 
Reference = C5;
306 
ValeurCmp = .1uF;
307 
IdModule  = SM0603;
308 
EndCmp
309 
 
310 
BeginCmp
311 
TimeStamp = /4EA882CF;
312 
Reference = C6;
313 
ValeurCmp = 100uF;
314 
IdModule  = SM0805;
315 
EndCmp
316 
 
317 
BeginCmp
318 
TimeStamp = /4EA654D2;
319 
Reference = D1;
320 
ValeurCmp = power;
321 
IdModule  = LED-0805;
322 
EndCmp
323 
 
324 
BeginCmp
325 
TimeStamp = /4EA74DB8;
326 
Reference = P1;
327 
ValeurCmp = CON_1;
328 
IdModule  = 1X20;
329 
EndCmp
330 
 
331 
BeginCmp
332 
TimeStamp = /4EA74DAC;
333 
Reference = P2;
334 
ValeurCmp = CON_2;
335 
IdModule  = 1X20;
336 
EndCmp
337 
 
338 
BeginCmp
339 
TimeStamp = /4EA1F196;
340 
Reference = P3;
341 
ValeurCmp = JTAG-POWER;
342 
IdModule  = 1X06;
343 
EndCmp
344 
 
345 
BeginCmp
346 
TimeStamp = /4EA653DA;
347 
Reference = R1;
348 
ValeurCmp = 470K;
349 
IdModule  = SM0603;
350 
EndCmp
351 
 
352 
BeginCmp
353 
TimeStamp = /4EA654AE;
354 
Reference = R2;
355 
ValeurCmp = 470;
356 
IdModule  = SM0603;
357 
EndCmp
358 
 
359 
BeginCmp
360 
TimeStamp = /4EA652AE;
361 
Reference = U1;
362 
ValeurCmp = SP6200;
363 
IdModule  = SOT23-5;
364 
EndCmp
365 
 
366 
BeginCmp
367 
TimeStamp = /4EA62E7A;
368 
Reference = U2;
369 
ValeurCmp = XC9572XL;
370 
IdModule  = TQFP44;
371 
EndCmp
372 
 
373 
EndListe
374 
\end{verbatim}
375 
\end{multicols}
376 
\newpage
377 
\subsection{OOCD Links}
378 
 
379 
\begin{multicols}{2}
380 
\begin{verbatim}
381 
 BeginCmp
382 
TimeStamp = 4EB85B2D
383 
Path = /4EAE3B06
384 
Reference = X1;
385 
ValeurCmp = USB-MB-H;
386 
IdModule  = con-usb-USB-MB-H;
387 
EndCmp
388 
 
389 
BeginCmp
390 
TimeStamp = 4EAEBF60
391 
Path = /4EAB3FF2
392 
Reference = IC1;
393 
ValeurCmp = FT2232C;
394 
IdModule  = ft2232c-LQFP;
395 
EndCmp
396 
 
397 
BeginCmp
398 
TimeStamp = 4EAEBF62
399 
Path = /4EAE3363
400 
Reference = D4;
401 
ValeurCmp = FT_OK;
402 
IdModule  = LED-0805;
403 
EndCmp
404 
 
405 
BeginCmp
406 
TimeStamp = 4EB0CE47
407 
Path = /4EAE3357
408 
Reference = D3;
409 
ValeurCmp = TX;
410 
IdModule  = LED-0805;
411 
EndCmp
412 
 
413 
BeginCmp
414 
TimeStamp = 4EAEBF66
415 
Path = /4EAE3349
416 
Reference = D2;
417 
ValeurCmp = RX;
418 
IdModule  = LED-0805;
419 
EndCmp
420 
 
421 
BeginCmp
422 
TimeStamp = 4EAEBF68
423 
Path = /4EAE32A1
424 
Reference = D1;
425 
ValeurCmp = +5V;
426 
IdModule  = LED-0805;
427 
EndCmp
428 
 
429 
BeginCmp
430 
TimeStamp = 4EAEBF69
431 
Path = /4EAE3DC9
432 
Reference = JTAG1;
433 
ValeurCmp = JTAG-ARM;
434 
IdModule  = nxp-JTAG-ARM;
435 
EndCmp
436 
 
437 
BeginCmp
438 
TimeStamp = 4EAEBF6A
439 
Path = /4EAE5354
440 
Reference = P1;
441 
ValeurCmp = UART;
442 
IdModule  = PIN_ARRAY_5x2;
443 
EndCmp
444 
 
445 
BeginCmp
446 
TimeStamp = 4EAEBF6B
447 
Path = /4EAE495A
448 
Reference = R19;
449 
ValeurCmp = 100;
450 
IdModule  = SM0603;
451 
EndCmp
452 
 
453 
BeginCmp
454 
TimeStamp = 4EAEBF6D
455 
Path = /4EAE4953
456 
Reference = R18;
457 
ValeurCmp = 100;
458 
IdModule  = SM0603;
459 
EndCmp
460 
 
461 
BeginCmp
462 
TimeStamp = 4EAEBF6F
463 
Path = /4EAE4946
464 
Reference = R17;
465 
ValeurCmp = 100;
466 
IdModule  = SM0603;
467 
EndCmp
468 
 
469 
BeginCmp
470 
TimeStamp = 4EAEBF71
471 
Path = /4EAE4FF4
472 
Reference = R16;
473 
ValeurCmp = 100K;
474 
IdModule  = SM0603;
475 
EndCmp
476 
 
477 
BeginCmp
478 
TimeStamp = 4EAEBF73
479 
Path = /4EAE4ED6
480 
Reference = R15;
481 
ValeurCmp = 100K;
482 
IdModule  = SM0603;
483 
EndCmp
484 
 
485 
BeginCmp
486 
TimeStamp = 4EAEBF75
487 
Path = /4EAE4DA5
488 
Reference = R14;
489 
ValeurCmp = 100K;
490 
IdModule  = SM0603;
491 
EndCmp
492 
 
493 
BeginCmp
494 
TimeStamp = 4EAEBF77
495 
Path = /4EAE4D2D
496 
Reference = R13;
497 
ValeurCmp = 100K;
498 
IdModule  = SM0603;
499 
EndCmp
500 
 
501 
BeginCmp
502 
TimeStamp = 4EAEBF79
503 
Path = /4EAE4E0E
504 
Reference = R12;
505 
ValeurCmp = 100K;
506 
IdModule  = SM0603;
507 
EndCmp
508 
 
509 
BeginCmp
510 
TimeStamp = 4EAEBF7B
511 
Path = /4EAE3F20
512 
Reference = R11;
513 
ValeurCmp = 10K;
514 
IdModule  = SM0603;
515 
EndCmp
516 
 
517 
BeginCmp
518 
TimeStamp = 4EAEBF7D
519 
Path = /4EAE3201
520 
Reference = R10;
521 
ValeurCmp = 470;
522 
IdModule  = SM0603;
523 
EndCmp
524 
 
525 
BeginCmp
526 
TimeStamp = 4EAEBF7F
527 
Path = /4EAE3B8F
528 
Reference = R9;
529 
ValeurCmp = 1K5;
530 
IdModule  = SM0603;
531 
EndCmp
532 
 
533 
BeginCmp
534 
TimeStamp = 4EAEBF81
535 
Path = /4EAE3B4B
536 
Reference = R8;
537 
ValeurCmp = 27;
538 
IdModule  = SM0603;
539 
EndCmp
540 
 
541 
BeginCmp
542 
TimeStamp = 4EAEBF83
543 
Path = /4EAE3B44
544 
Reference = R7;
545 
ValeurCmp = 27;
546 
IdModule  = SM0603;
547 
EndCmp
548 
 
549 
BeginCmp
550 
TimeStamp = 4EAEBF85
551 
Path = /4EAE346C
552 
Reference = R6;
553 
ValeurCmp = 1K;
554 
IdModule  = SM0603;
555 
EndCmp
556 
 
557 
BeginCmp
558 
TimeStamp = 4EB0CE4A
559 
Path = /4EAE3468
560 
Reference = R5;
561 
ValeurCmp = 1K;
562 
IdModule  = SM0603;
563 
EndCmp
564 
 
565 
BeginCmp
566 
TimeStamp = 4EAEBF89
567 
Path = /4EAE3464
568 
Reference = R4;
569 
ValeurCmp = 1K;
570 
IdModule  = SM0603;
571 
EndCmp
572 
 
573 
BeginCmp
574 
TimeStamp = 4EAEBF8B
575 
Path = /4EAE3297
576 
Reference = R3;
577 
ValeurCmp = 1K;
578 
IdModule  = SM0603;
579 
EndCmp
580 
 
581 
BeginCmp
582 
TimeStamp = 4EAEBF8D
583 
Path = /4EAE2459
584 
Reference = R2;
585 
ValeurCmp = 2K2;
586 
IdModule  = SM0603;
587 
EndCmp
588 
 
589 
BeginCmp
590 
TimeStamp = 4EAEBF8F
591 
Path = /4EAE2494
592 
Reference = R1;
593 
ValeurCmp = 10K;
594 
IdModule  = SM0603;
595 
EndCmp
596 
 
597 
BeginCmp
598 
TimeStamp = 4EAEBF91
599 
Path = /4EAE516F
600 
Reference = C21;
601 
ValeurCmp = 100n;
602 
IdModule  = SM0603;
603 
EndCmp
604 
 
605 
BeginCmp
606 
TimeStamp = 4EAEBF93
607 
Path = /4EAE5167
608 
Reference = C20;
609 
ValeurCmp = 100n;
610 
IdModule  = SM0603;
611 
EndCmp
612 
 
613 
BeginCmp
614 
TimeStamp = 4EAEBF95
615 
Path = /4EAE4AF1
616 
Reference = C19;
617 
ValeurCmp = 47p;
618 
IdModule  = SM0603;
619 
EndCmp
620 
 
621 
BeginCmp
622 
TimeStamp = 4EAEBF97
623 
Path = /4EAE4B24
624 
Reference = C18;
625 
ValeurCmp = 47p;
626 
IdModule  = SM0603;
627 
EndCmp
628 
 
629 
BeginCmp
630 
TimeStamp = 4EAEBF99
631 
Path = /4EAE4B2F
632 
Reference = C17;
633 
ValeurCmp = 47p;
634 
IdModule  = SM0603;
635 
EndCmp
636 
 
637 
BeginCmp
638 
TimeStamp = 4EAEBF9B
639 
Path = /4EAE4B56
640 
Reference = C16;
641 
ValeurCmp = 47p;
642 
IdModule  = SM0603;
643 
EndCmp
644 
 
645 
BeginCmp
646 
TimeStamp = 4EAEBF9D
647 
Path = /4EAE4B6A
648 
Reference = C15;
649 
ValeurCmp = 47p;
650 
IdModule  = SM0603;
651 
EndCmp
652 
 
653 
BeginCmp
654 
TimeStamp = 4EAEBF9F
655 
Path = /4EAE4B76
656 
Reference = C14;
657 
ValeurCmp = 47p;
658 
IdModule  = SM0603;
659 
EndCmp
660 
 
661 
BeginCmp
662 
TimeStamp = 4EAEBFA1
663 
Path = /4EAE3EE0
664 
Reference = C13;
665 
ValeurCmp = 100n;
666 
IdModule  = SM0603;
667 
EndCmp
668 
 
669 
BeginCmp
670 
TimeStamp = 4EAEBFA3
671 
Path = /4EAE384B
672 
Reference = C12;
673 
ValeurCmp = C;
674 
IdModule  = SM0603;
675 
EndCmp
676 
 
677 
BeginCmp
678 
TimeStamp = 4EAEBFA5
679 
Path = /4EAE31EE
680 
Reference = C11;
681 
ValeurCmp = 100n;
682 
IdModule  = SM0603;
683 
EndCmp
684 
 
685 
BeginCmp
686 
TimeStamp = 4EAEBFA7
687 
Path = /4EAE31F7
688 
Reference = C10;
689 
ValeurCmp = 100n;
690 
IdModule  = SM0603;
691 
EndCmp
692 
 
693 
BeginCmp
694 
TimeStamp = 4EAEBFA9
695 
Path = /4EAE3A16
696 
Reference = C9;
697 
ValeurCmp = 33n;
698 
IdModule  = SM0603;
699 
EndCmp
700 
 
701 
BeginCmp
702 
TimeStamp = 4EAEBFAB
703 
Path = /4EAE31FD
704 
Reference = C8;
705 
ValeurCmp = 100n;
706 
IdModule  = SM0603;
707 
EndCmp
708 
 
709 
BeginCmp
710 
TimeStamp = 4EAEBFAD
711 
Path = /4EAE24AC
712 
Reference = C7;
713 
ValeurCmp = 100n;
714 
IdModule  = SM0603;
715 
EndCmp
716 
 
717 
BeginCmp
718 
TimeStamp = 4EAEBFAF
719 
Path = /4EAE30A8
720 
Reference = C6;
721 
ValeurCmp = 2u2;
722 
IdModule  = SM0603;
723 
EndCmp
724 
 
725 
BeginCmp
726 
TimeStamp = 4EAEBFB1
727 
Path = /4EAE3C52
728 
Reference = C5;
729 
ValeurCmp = 2u2;
730 
IdModule  = SM0603;
731 
EndCmp
732 
 
733 
BeginCmp
734 
TimeStamp = 4EAEBFB3
735 
Path = /4EAE308F
736 
Reference = C4;
737 
ValeurCmp = 100n;
738 
IdModule  = SM0603;
739 
EndCmp
740 
 
741 
BeginCmp
742 
TimeStamp = 4EAEBFB5
743 
Path = /4EAE3C53
744 
Reference = C3;
745 
ValeurCmp = 100n;
746 
IdModule  = SM0603;
747 
EndCmp
748 
 
749 
BeginCmp
750 
TimeStamp = 4EAEBFB7
751 
Path = /4EAE2C55
752 
Reference = C2;
753 
ValeurCmp = 10n;
754 
IdModule  = SM0603;
755 
EndCmp
756 
 
757 
BeginCmp
758 
TimeStamp = 4EAEBFB9
759 
Path = /4EAE3C56
760 
Reference = C1;
761 
ValeurCmp = 10n;
762 
IdModule  = SM0603;
763 
EndCmp
764 
 
765 
BeginCmp
766 
TimeStamp = 4EAEBFBA
767 
Path = /4EAE3061
768 
Reference = L2;
769 
ValeurCmp = 742792095;
770 
IdModule  = SM0805;
771 
EndCmp
772 
 
773 
BeginCmp
774 
TimeStamp = 4EAEBFBC
775 
Path = /4EAE3C54
776 
Reference = L1;
777 
ValeurCmp = 742792095;
778 
IdModule  = SM0805;
779 
EndCmp
780 
 
781 
BeginCmp
782 
TimeStamp = 4EAEBFBD
783 
Path = /4EAE4851
784 
Reference = U3;
785 
ValeurCmp = SN74AUP1G125;
786 
IdModule  = SOT23-5;
787 
EndCmp
788 
 
789 
BeginCmp
790 
TimeStamp = 4EAEBFBF
791 
Path = /4EAE4848
792 
Reference = U2;
793 
ValeurCmp = SN74AUP1G125;
794 
IdModule  = SOT23-5;
795 
EndCmp
796 
 
797 
BeginCmp
798 
TimeStamp = 4EAEBFC0
799 
Path = /4EAE22F9
800 
Reference = U1;
801 
ValeurCmp = 93LC46BT;
802 
IdModule  = SOT23_6;
803 
EndCmp
804 
 
805 
BeginCmp
806 
TimeStamp = 4EAEBF61
807 
Path = /4EAE26A6
808 
Reference = F1;
809 
ValeurCmp = 6MHz;
810 
IdModule  = -CSTCC;
811 
EndCmp
812 
 
813 
BeginCmp
814 
TimeStamp = 4EB863DD
815 
Path =
816 
Reference = ref;
817 
ValeurCmp = logo_min;
818 
IdModule  = ;
819 
EndCmp
820 
 
821 
EndListe
822 
\end{verbatim}
823 
\end{multicols}
824 
 
825 
\newpage
826 
\subsection{S3Power}
827 
 
828 
\begin{multicols}{2}
829 
\begin{verbatim}
830 
BeginCmp
831 
TimeStamp = 48FC941B;
832 
Reference = C1;
833 
ValeurCmp = 100uf_6v;
834 
IdModule  = -B/3528-21W;
835 
EndCmp
836 
 
837 
BeginCmp
838 
TimeStamp = 48FC9514;
839 
Reference = C2;
840 
ValeurCmp = 100nf;
841 
IdModule  = SM0805;
842 
EndCmp
843 
 
844 
BeginCmp
845 
TimeStamp = 48FC9531;
846 
Reference = C3;
847 
ValeurCmp = 100nf;
848 
IdModule  = SM0805;
849 
EndCmp
850 
 
851 
BeginCmp
852 
TimeStamp = 48FC9532;
853 
Reference = C4;
854 
ValeurCmp = 100nf;
855 
IdModule  = SM0805;
856 
EndCmp
857 
 
858 
BeginCmp
859 
TimeStamp = 48FC94F6;
860 
Reference = C5;
861 
ValeurCmp = 1.5nf;
862 
IdModule  = SM0805;
863 
EndCmp
864 
 
865 
BeginCmp
866 
TimeStamp = 48FCB2A9;
867 
Reference = C6;
868 
ValeurCmp = 1.5nf;
869 
IdModule  = SM0805;
870 
EndCmp
871 
 
872 
BeginCmp
873 
TimeStamp = 48FC94AF;
874 
Reference = C7;
875 
ValeurCmp = 10nf;
876 
IdModule  = SM0805;
877 
EndCmp
878 
 
879 
BeginCmp
880 
TimeStamp = 48FC948C;
881 
Reference = C8;
882 
ValeurCmp = 10uf_6v;
883 
IdModule  = -A/3216-18R;
884 
EndCmp
885 
 
886 
BeginCmp
887 
TimeStamp = 48FC948A;
888 
Reference = C9;
889 
ValeurCmp = 10uf_6v;
890 
IdModule  = -A/3216-18R;
891 
EndCmp
892 
 
893 
BeginCmp
894 
TimeStamp = 48FDDDFF;
895 
Reference = C10;
896 
ValeurCmp = 10uf_6v;
897 
IdModule  = -A/3216-18R;
898 
EndCmp
899 
 
900 
BeginCmp
901 
TimeStamp = 48FC9564;
902 
Reference = C11;
903 
ValeurCmp = 10pf;
904 
IdModule  = SM0805;
905 
EndCmp
906 
 
907 
BeginCmp
908 
TimeStamp = 48FC9463;
909 
Reference = C12;
910 
ValeurCmp = 100uf_3v;
911 
IdModule  = -B/3528-21W;
912 
EndCmp
913 
 
914 
BeginCmp
915 
TimeStamp = 48FDDDFE;
916 
Reference = C13;
917 
ValeurCmp = 100uf_3v;
918 
IdModule  = -B/3528-21W;
919 
EndCmp
920 
 
921 
BeginCmp
922 
TimeStamp = 48FC939B;
923 
Reference = D1;
924 
ValeurCmp = SM6T6V6A;
925 
IdModule  = DO_214AA;
926 
EndCmp
927 
 
928 
BeginCmp
929 
TimeStamp = 48FC97B2;
930 
Reference = D2;
931 
ValeurCmp = SS32;
932 
IdModule  = DO214AB;
933 
EndCmp
934 
 
935 
BeginCmp
936 
TimeStamp = 48FDDE02;
937 
Reference = D3;
938 
ValeurCmp = SS32;
939 
IdModule  = DO214AB;
940 
EndCmp
941 
 
942 
BeginCmp
943 
TimeStamp = 4900D275;
944 
Reference = D4;
945 
ValeurCmp = LED;
946 
IdModule  = -1206;
947 
EndCmp
948 
 
949 
BeginCmp
950 
TimeStamp = 4900C810;
951 
Reference = D5;
952 
ValeurCmp = LED;
953 
IdModule  = -1206;
954 
EndCmp
955 
 
956 
BeginCmp
957 
TimeStamp = 48FC9598;
958 
Reference = L1;
959 
ValeurCmp = 15uHy;
960 
IdModule  = wuerth_elektronik_WE-PD4;
961 
EndCmp
962 
 
963 
BeginCmp
964 
TimeStamp = 48FDDE00;
965 
Reference = L2;
966 
ValeurCmp = 5uHy;
967 
IdModule  = wuerth_elektronik_v5-WE-TPC_XL/XLH;
968 
EndCmp
969 
 
970 
BeginCmp
971 
TimeStamp = 4907220B;
972 
Reference = P1;
973 
ValeurCmp = TST_Vin;
974 
IdModule  = PINTST;
975 
EndCmp
976 
 
977 
BeginCmp
978 
TimeStamp = 48FDE089;
979 
Reference = P3;
980 
ValeurCmp = TST_Vaux;
981 
IdModule  = PINTST;
982 
EndCmp
983 
 
984 
BeginCmp
985 
TimeStamp = 48FDDD65;
986 
Reference = P4;
987 
ValeurCmp = TST_Vcore;
988 
IdModule  = PINTST;
989 
EndCmp
990 
 
991 
BeginCmp
992 
TimeStamp = 48FDDE09;
993 
Reference = P5;
994 
ValeurCmp = TST_Vcco;
995 
IdModule  = PINTST;
996 
EndCmp
997 
 
998 
BeginCmp
999 
TimeStamp = 491C3ECB;
1000 
Reference = P6;
1001 
ValeurCmp = CONN_4;
1002 
IdModule  = header_1x4;
1003 
EndCmp
1004 
 
1005 
BeginCmp
1006 
TimeStamp = 49256388;
1007 
Reference = P7;
1008 
ValeurCmp = CONN_7;
1009 
IdModule  = header_1x7;
1010 
EndCmp
1011 
 
1012 
BeginCmp
1013 
TimeStamp = 499DB3E3;
1014 
Reference = P8;
1015 
ValeurCmp = TST_GND;
1016 
IdModule  = PINTST;
1017 
EndCmp
1018 
 
1019 
BeginCmp
1020 
TimeStamp = 48FC9789;
1021 
Reference = Q1;
1022 
ValeurCmp = G2309;
1023 
IdModule  = SOT23GDS;
1024 
EndCmp
1025 
 
1026 
BeginCmp
1027 
TimeStamp = 48FDDE01;
1028 
Reference = Q2;
1029 
ValeurCmp = G2309;
1030 
IdModule  = SOT23GDS;
1031 
EndCmp
1032 
 
1033 
BeginCmp
1034 
TimeStamp = 48FDE587;
1035 
Reference = R1;
1036 
ValeurCmp = 22K;
1037 
IdModule  = SM0805;
1038 
EndCmp
1039 
 
1040 
BeginCmp
1041 
TimeStamp = 48FDE584;
1042 
Reference = R2;
1043 
ValeurCmp = 22K;
1044 
IdModule  = SM0805;
1045 
EndCmp
1046 
 
1047 
BeginCmp
1048 
TimeStamp = 48FDE56A;
1049 
Reference = R3;
1050 
ValeurCmp = 22K;
1051 
IdModule  = SM0805;
1052 
EndCmp
1053 
 
1054 
BeginCmp
1055 
TimeStamp = 48FDE06A;
1056 
Reference = R4;
1057 
ValeurCmp = 620K;
1058 
IdModule  = SM0805;
1059 
EndCmp
1060 
 
1061 
BeginCmp
1062 
TimeStamp = 48FDE06B;
1063 
Reference = R5;
1064 
ValeurCmp = 154K;
1065 
IdModule  = SM0805;
1066 
EndCmp
1067 
 
1068 
BeginCmp
1069 
TimeStamp = 48FDD021;
1070 
Reference = R6;
1071 
ValeurCmp = 33m;
1072 
IdModule  = SM2512;
1073 
EndCmp
1074 
 
1075 
BeginCmp
1076 
TimeStamp = 48FDDE03;
1077 
Reference = R7;
1078 
ValeurCmp = 33m;
1079 
IdModule  = SM2512;
1080 
EndCmp
1081 
 
1082 
BeginCmp
1083 
TimeStamp = 4900D274;
1084 
Reference = R8;
1085 
ValeurCmp = 330;
1086 
IdModule  = SM0805;
1087 
EndCmp
1088 
 
1089 
BeginCmp
1090 
TimeStamp = 48FDE2B6;
1091 
Reference = R9;
1092 
ValeurCmp = 56;
1093 
IdModule  = SM0805;
1094 
EndCmp
1095 
 
1096 
BeginCmp
1097 
TimeStamp = 48FDDF37;
1098 
Reference = R10;
1099 
ValeurCmp = 620K;
1100 
IdModule  = SM0805;
1101 
EndCmp
1102 
 
1103 
BeginCmp
1104 
TimeStamp = 48FDDF3E;
1105 
Reference = R11;
1106 
ValeurCmp = 365K;
1107 
IdModule  = SM0805;
1108 
EndCmp
1109 
 
1110 
BeginCmp
1111 
TimeStamp = 4900C7F6;
1112 
Reference = R12;
1113 
ValeurCmp = 330;
1114 
IdModule  = SM0805;
1115 
EndCmp
1116 
 
1117 
BeginCmp
1118 
TimeStamp = 48FC9227;
1119 
Reference = U1;
1120 
ValeurCmp = TPS75003;
1121 
IdModule  = TPS75003;
1122 
EndCmp
1123 
 
1124 
EndListe
1125 
\end{verbatim}
1126 
\end{multicols}
1127 
 
1128 
\newpage
1129 
\subsection{FPGA}
1130 
 
1131 
\begin{multicols}{2}
1132 
\begin{verbatim}
1133 
BeginCmp
1134 
TimeStamp = /4F4D3964;
1135 
Reference = C1;
1136 
ValeurCmp = C_clk;
1137 
IdModule  = SM0603_Capa;
1138 
EndCmp
1139 
 
1140 
BeginCmp
1141 
TimeStamp = /4F58A802;
1142 
Reference = Ca1;
1143 
ValeurCmp = 10n;
1144 
IdModule  = SM0603_Capa;
1145 
EndCmp
1146 
 
1147 
BeginCmp
1148 
TimeStamp = /4F69141B;
1149 
Reference = Ca2;
1150 
ValeurCmp = 10n;
1151 
IdModule  = SM0603_Capa;
1152 
EndCmp
1153 
 
1154 
BeginCmp
1155 
TimeStamp = /4F69141F;
1156 
Reference = Ca3;
1157 
ValeurCmp = 10n;
1158 
IdModule  = SM0603_Capa;
1159 
EndCmp
1160 
 
1161 
BeginCmp
1162 
TimeStamp = /4F691428;
1163 
Reference = Ca4;
1164 
ValeurCmp = 10n;
1165 
IdModule  = SM0603_Capa;
1166 
EndCmp
1167 
 
1168 
BeginCmp
1169 
TimeStamp = /4F58BF85;
1170 
Reference = Ca5;
1171 
ValeurCmp = 10u;
1172 
IdModule  = SM1206POL;
1173 
EndCmp
1174 
 
1175 
BeginCmp
1176 
TimeStamp = /4F69144A;
1177 
Reference = Ca6;
1178 
ValeurCmp = 100u;
1179 
IdModule  = SM1210L;
1180 
EndCmp
1181 
 
1182 
BeginCmp
1183 
TimeStamp = /4F6913AD;
1184 
Reference = Ci1;
1185 
ValeurCmp = 10n;
1186 
IdModule  = SM0603_Capa;
1187 
EndCmp
1188 
 
1189 
BeginCmp
1190 
TimeStamp = /4F6913AC;
1191 
Reference = Ci2;
1192 
ValeurCmp = 10n;
1193 
IdModule  = SM0603_Capa;
1194 
EndCmp
1195 
 
1196 
BeginCmp
1197 
TimeStamp = /4F6913AA;
1198 
Reference = Ci3;
1199 
ValeurCmp = 10n;
1200 
IdModule  = SM0603_Capa;
1201 
EndCmp
1202 
 
1203 
BeginCmp
1204 
TimeStamp = /4F6913AB;
1205 
Reference = Ci4;
1206 
ValeurCmp = 10n;
1207 
IdModule  = SM0603_Capa;
1208 
EndCmp
1209 
 
1210 
BeginCmp
1211 
TimeStamp = /4F6913A7;
1212 
Reference = Ci5;
1213 
ValeurCmp = 10u;
1214 
IdModule  = SM1206POL;
1215 
EndCmp
1216 
 
1217 
BeginCmp
1218 
TimeStamp = /4F6913A9;
1219 
Reference = Ci6;
1220 
ValeurCmp = 100u;
1221 
IdModule  = SM1210L;
1222 
EndCmp
1223 
 
1224 
BeginCmp
1225 
TimeStamp = /4F58BBF5;
1226 
Reference = Co1;
1227 
ValeurCmp = 1n;
1228 
IdModule  = SM0603_Capa;
1229 
EndCmp
1230 
 
1231 
BeginCmp
1232 
TimeStamp = /4F58BC49;
1233 
Reference = Co2;
1234 
ValeurCmp = 1n;
1235 
IdModule  = SM0603_Capa;
1236 
EndCmp
1237 
 
1238 
BeginCmp
1239 
TimeStamp = /4F58BC4C;
1240 
Reference = Co3;
1241 
ValeurCmp = 1n;
1242 
IdModule  = SM0603_Capa;
1243 
EndCmp
1244 
 
1245 
BeginCmp
1246 
TimeStamp = /4F58BC4F;
1247 
Reference = Co4;
1248 
ValeurCmp = 1n;
1249 
IdModule  = SM0603_Capa;
1250 
EndCmp
1251 
 
1252 
BeginCmp
1253 
TimeStamp = /4F58BEE2;
1254 
Reference = Co5;
1255 
ValeurCmp = 1u;
1256 
IdModule  = SM1206POL;
1257 
EndCmp
1258 
 
1259 
BeginCmp
1260 
TimeStamp = /4F58BF10;
1261 
Reference = Co6;
1262 
ValeurCmp = 1u;
1263 
IdModule  = SM1206POL;
1264 
EndCmp
1265 
 
1266 
BeginCmp
1267 
TimeStamp = /4F58BF12;
1268 
Reference = Co7;
1269 
ValeurCmp = 1u;
1270 
IdModule  = SM1206POL;
1271 
EndCmp
1272 
 
1273 
BeginCmp
1274 
TimeStamp = /4F58BF17;
1275 
Reference = Co8;
1276 
ValeurCmp = 1u;
1277 
IdModule  = SM1206POL;
1278 
EndCmp
1279 
 
1280 
BeginCmp
1281 
TimeStamp = /4F58BF30;
1282 
Reference = Co9;
1283 
ValeurCmp = 10u;
1284 
IdModule  = SM1206POL;
1285 
EndCmp
1286 
 
1287 
BeginCmp
1288 
TimeStamp = /4E4D4DD3;
1289 
Reference = D1;
1290 
ValeurCmp = DONE;
1291 
IdModule  = LED-0805;
1292 
EndCmp
1293 
 
1294 
BeginCmp
1295 
TimeStamp = /4F4D2E32;
1296 
Reference = H1;
1297 
ValeurCmp = PCB_HOLE;
1298 
IdModule  = HOLE;
1299 
EndCmp
1300 
 
1301 
BeginCmp
1302 
TimeStamp = /4F4D2E38;
1303 
Reference = H2;
1304 
ValeurCmp = PCB_HOLE;
1305 
IdModule  = HOLE;
1306 
EndCmp
1307 
 
1308 
BeginCmp
1309 
TimeStamp = /4F4D2E36;
1310 
Reference = H3;
1311 
ValeurCmp = PCB_HOLE;
1312 
IdModule  = HOLE;
1313 
EndCmp
1314 
 
1315 
BeginCmp
1316 
TimeStamp = /4F4D2E3A;
1317 
Reference = H4;
1318 
ValeurCmp = PCB_HOLE;
1319 
IdModule  = HOLE;
1320 
EndCmp
1321 
 
1322 
BeginCmp
1323 
TimeStamp = /4E178DD4;
1324 
Reference = IC1;
1325 
ValeurCmp = XCF01S-VO20;
1326 
IdModule  = xilinx_virtexii-xc2v80&flashprom-VO20;
1327 
EndCmp
1328 
 
1329 
BeginCmp
1330 
TimeStamp = /4E178908;
1331 
Reference = K1;
1332 
ValeurCmp = MODE_PROG;
1333 
IdModule  = PIN_ARRAY_3X1;
1334 
EndCmp
1335 
 
1336 
BeginCmp
1337 
TimeStamp = /4F4D2E41;
1338 
Reference = OSC1;
1339 
ValeurCmp = OSC;
1340 
IdModule  = DIP4-8_OSC;
1341 
EndCmp
1342 
 
1343 
BeginCmp
1344 
TimeStamp = /4F4807B3;
1345 
Reference = P1;
1346 
ValeurCmp = A;
1347 
IdModule  = 1X20_MOD;
1348 
EndCmp
1349 
 
1350 
BeginCmp
1351 
TimeStamp = /4F480E3E;
1352 
Reference = P2;
1353 
ValeurCmp = B;
1354 
IdModule  = 1X20_MOD;
1355 
EndCmp
1356 
 
1357 
BeginCmp
1358 
TimeStamp = /4F4D2C3A;
1359 
Reference = P3;
1360 
ValeurCmp = JTAG;
1361 
IdModule  = PIN_ARRAY-6X1;
1362 
EndCmp
1363 
 
1364 
BeginCmp
1365 
TimeStamp = /4F47FC62;
1366 
Reference = P4;
1367 
ValeurCmp = POWER;
1368 
IdModule  = bornier2;
1369 
EndCmp
1370 
 
1371 
BeginCmp
1372 
TimeStamp = /4F4810C2;
1373 
Reference = P5;
1374 
ValeurCmp = PUDC;
1375 
IdModule  = PIN_ARRAY_2X1;
1376 
EndCmp
1377 
 
1378 
BeginCmp
1379 
TimeStamp = /4F46B535;
1380 
Reference = R1;
1381 
ValeurCmp = 330;
1382 
IdModule  = SM0805;
1383 
EndCmp
1384 
 
1385 
BeginCmp
1386 
TimeStamp = /4F46B5A2;
1387 
Reference = R2;
1388 
ValeurCmp = 4K7;
1389 
IdModule  = SM0805;
1390 
EndCmp
1391 
 
1392 
BeginCmp
1393 
TimeStamp = /4F46B626;
1394 
Reference = R3;
1395 
ValeurCmp = 4K7;
1396 
IdModule  = SM0805;
1397 
EndCmp
1398 
 
1399 
BeginCmp
1400 
TimeStamp = /4E4D4DC9;
1401 
Reference = R4;
1402 
ValeurCmp = R_LED;
1403 
IdModule  = SM0805;
1404 
EndCmp
1405 
 
1406 
BeginCmp
1407 
TimeStamp = /4F4D3968;
1408 
Reference = R5;
1409 
ValeurCmp = R_clk;
1410 
IdModule  = SM0805;
1411 
EndCmp
1412 
 
1413 
BeginCmp
1414 
TimeStamp = /4E4D5328;
1415 
Reference = R6;
1416 
ValeurCmp = 10K;
1417 
IdModule  = SM0805;
1418 
EndCmp
1419 
 
1420 
BeginCmp
1421 
TimeStamp = /4F4801C9;
1422 
Reference = R7;
1423 
ValeurCmp = R_push;
1424 
IdModule  = SM0805;
1425 
EndCmp
1426 
 
1427 
BeginCmp
1428 
TimeStamp = /4F481067;
1429 
Reference = R8;
1430 
ValeurCmp = 100;
1431 
IdModule  = SM0805;
1432 
EndCmp
1433 
 
1434 
BeginCmp
1435 
TimeStamp = /4F4801A4;
1436 
Reference = SW1;
1437 
ValeurCmp = RESET_PROG;
1438 
IdModule  = SW_PUSH_SMALL;
1439 
EndCmp
1440 
 
1441 
BeginCmp
1442 
TimeStamp = /4F4675A1;
1443 
Reference = U1;
1444 
ValeurCmp = XC3S50A-VQ100;
1445 
IdModule  = VQFP100;
1446 
EndCmp
1447 
 
1448 
BeginCmp
1449 
TimeStamp = /4F47E8FD;
1450 
Reference = U2;
1451 
ValeurCmp = TPS75003_PM;
1452 
IdModule  = TPS75003_PM_INV;
1453 
EndCmp
1454 
 
1455 
EndListe
1456 
\end{verbatim}
1457 
\end{multicols}
1458 61 guanucolui 
\end{document}

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.