OpenCores
URL https://opencores.org/ocsvn/phr/phr/trunk

Subversion Repositories phr

[/] [phr/] [trunk/] [doc/] [informe-tesis/] [tesis-beamer/] [PrimeraVersion.tex] - Blame information for rev 346

Go to most recent revision | Details | Compare with Previous | View Log

Line No. Rev Author Line
1 317 guanucolui
%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
2
\section[Desarrollo]{Desarrollo del Proyecto PHR}
3
%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
4
 
5
\begin{frame}
6
\frametitle{El proyecto PHR}
7
\begin{center}
8
\includegraphics[width=\textwidth]{phr_small.png}
9
\end{center}
10
\end{frame}
11
 
12
 
13
\begin{frame}
14
  \frametitle{Recursos de hardware vs. Nivel de enseñanza}
15
  % \transfade
16
 
17
  \begin{block}{Consideración}
18
    En función del perfil del usuario de la plataforma se definen los dispositivos que se utilizarán
19
  \end{block}
20
 
21
  \vfill
22
 
23
  \begin{center}
24
      \begin{tabular}{|l|c|c|c|}
25
        \hline
26
        \multirow{2}{*}{Nivel} & Llaves/pulsadores & ADC\&DAC/SPI & USB/ETH \\
27
        & Diodos LED & Display LCD/VGA & HDMI \\ \hline
28
        \hline
29
        Inicial & $\checkmark$ & & \\
30
        \hline
31
        Medio & $\checkmark$ & $\checkmark$ & \\
32
        \hline
33
        Avanzado & $\checkmark$ & $\checkmark$ & $\checkmark$ \\
34
        \hline
35
      \end{tabular}
36
 
37
  \end{center}
38
\end{frame}
39
 
40
 
41
\subsection{Diagrama en bloques}
42
 
43
\begin{frame}
44
\frametitle{Diagrama de bloques del Hardware}
45
%\transfade
46
\begin{center}
47
    \includegraphics<1>[width=0.9\textwidth]{block1.pdf}
48
    \includegraphics<2>[width=0.9\textwidth]{block2.pdf}
49
    \includegraphics<3>[width=0.9\textwidth]{block3.pdf}
50
\end{center}
51
\end{frame}
52
 
53
 
54
\subsection{Placa PHRBoard} %%%%%%%%%%%%%%%%%%%%%%%%%%%
55
 
56
\begin{frame}
57
\frametitle{Características}
58
 
59
\begin{description}[Memoria PROM:]
60
 
61
\item [FPGA:] Xilinx Spartan-3A XC3S200A (VQG100)
62
\pause
63
\item [Memoria PROM:] Xilinx XCF02S
64
\pause
65
\item [Voltaje entrada:] 5V
66
\pause
67
\item [Relojes:] Un reloj fijo y tres seleccionables:
68
 
69
        \begin{enumerate}
70
        \item 50 MHz
71
        \item 16 MHz, 1 MHz, 500 kHz y 250 kHz
72
        \item 125 kHz, 62.5 kHz, 31.25 kHz, 15.625 kHz
73
        \item 3.9062 kHz, 1.9531 kHz, 976,56251 Hz
74
   \end{enumerate}
75
\pause
76
\item [GPIO:] 28 pines en total
77
\end{description}
78
 
79
\end{frame}
80
 
81
\begin{frame}[b]
82
\frametitle{Periféricos}
83
\only<1-5>{
84
\begin{itemize}
85
\item \textbf<1>{8 LEDs}
86
\item \textbf<2>{8 llaves (\emph{DIP switch})}
87
\item \textbf<3>{4 pulsadores}
88
\item \textbf<4>{Display de 7 segmentos cuádruple}
89
\item \textbf<5>{Puerto serie}
90
\end{itemize}
91
}
92
 
93
%\vspace{3cm}
94
\begin{center}
95
\includegraphics<1>[width=1\textwidth]{phr_top_leds.png}
96
\includegraphics<2>[width=1\textwidth]{phr_top_switches.png}
97
\includegraphics<3>[width=1\textwidth]{phr_top_botones.png}
98
\includegraphics<4>[width=1\textwidth]{phr_top_display.png}
99
\includegraphics<5>[width=1\textwidth]{phr_top_nada.png}
100
\includegraphics<6>[width=1\textwidth]{phr_top.png}
101
\end{center}
102
 
103
\vspace{1ex}
104
 
105
\end{frame}
106
 
107
 
108
\subsection{Placa S3Power} %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
109
 
110
\begin{frame}
111
\frametitle{Placa S3Power}
112
\begin{center}
113
\includegraphics[width=0.8\textwidth]{s3power_small.png}
114
\end{center}
115
\end{frame}
116
 
117
\begin{frame}
118
\frametitle{Voltajes elegidos}
119
\begin{itemize}
120
\item 1.2V y 2.5A para la lógica interna.
121
\item 3.3V y 2.5A para los bancos de pines.
122
\item 2.5V y 200mA para el módulo de comunicación JTAG.
123
\end{itemize}
124
\end{frame}
125
 
126
\begin{frame}
127
\frametitle{El chip TPS75003}
128
\begin{itemize}
129 318 guanucolui
\item Posee tres reguladores de tensión: Dos tipo Buck de 3A y eficiencia del 95\% y otro regulador lineal de 300 mA.
130
\item Voltaje de entrada de entre 2.2V y 6.5 V.
131
\item Arranque suave e independiente para cada regulador.
132
\item Tensiones ajustables de 1.2 V a 6.5 V para los convertidores Buck y de 1.0 V a 6.5 V para el convertidor lineal.
133 317 guanucolui
\end{itemize}
134
\end{frame}
135
 
136
%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
137
\subsection{Placa OOCDLink}
138
%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
139
 
140
\begin{frame}
141
\frametitle{Placa OOCDLink}
142
\begin{center}
143
\includegraphics[width=0.8\textwidth]{oocdlink_small.png}
144
\end{center}
145
\end{frame}
146
 
147
 
148
\subsubsection{FTDI chip} %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
149
 
150
\begin{frame}
151
\frametitle{El chip FT2232D}
152
\begin{itemize}
153 318 guanucolui
\item Cumple con USB 2.0 Full Speed (12 Mbits/sec)
154
\item Tiene una tasa de transferencia de entre 300 y 3 MBaud
155
\item Forma dos canales de comunicación
156
\item Desde el SO, la interfaz puede verse como un \emph{puerto serie virtual}
157
\item Existen librerías para implementar JTAG, I2C y SPI
158 317 guanucolui
\end{itemize}
159
\end{frame}
160
 
161
\begin{frame}
162
\frametitle{El chip FT2232D}
163
\begin{center}
164
\includegraphics[width=1\textwidth]{FTblock.pdf}
165
\end{center}
166
\end{frame}
167
 
168
\subsection{Software} %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
169
 
170
\begin{frame}
171
\frametitle{xc3sprog}
172
\begin{center}
173
\includegraphics[width=1\textwidth]{xc3sprog.pdf}
174
\end{center}
175
\end{frame}
176
 
177
\begin{frame}
178
\frametitle{PHR GUI (utiliza el \textsl{software} xc3sprog)}
179
\begin{center}
180
\includegraphics[width=0.8\textwidth]{front-end.pdf}
181
\end{center}
182
\end{frame}
183
 
184
 
185
 
186
 

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.