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\title{Plataforma de Hardware Reconfigurable para el Diseño de Sistemas Digitales}

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\author{\IEEEauthorblockN{Alexis Maximiliano Quiteros, Luis Alberto Guanuco, Sergio Daniel Olmedo}

\IEEEauthorblockA{Centro Universitario de Desarrollo en Automoción y Robótica\\

Universidad Tecnológica Nacional\\

Facultad Regional Córdoba\\

Email: maximiliano.quinteros@gmail.com, lguanuco@electronica.frc.utn.edu.ar, solmedo@scdt.frc.utn.edu.ar}

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%Georgia Institute of Technology,

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\begin{abstract}

La contaste evolución de los sistemas electrónicos (digitales y analógicos) exige la búsqueda de nuevas herramientas para la formación académica. En el caso del diseños de sistemas digitales una excelente alternativa es el uso placas de evaluación basadas en dispositivos lógicos programables (PLDs). En función de los requerimientos y necesidades académicas que demandan recursos de hardware, y las oportunidades concretas de desarrollar una plataforma personalizada a las necesidades plateadas es que se presenta una plataforma reconfigurable con especificaciones abiertas. Este diseño cuenta con periféricos básicos con que se pueda interactuar en la implementación de sistemas digitales, pero además cuenta con una FPGA que dispone de una gran cantidad de recursos internos para el uso en sistemas digitales avanzados que requieren gran capacidad de procesamiento. El proyecto se publica en forma libre (licencia GPL) buscando incentivar a otras grupos académicos en la  modificación y adaptación de este trabajo a sus necesidades como así también proponer mejoras en versiones futuras de la plataforma.

\end{abstract}

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\section{Introducción}

Las áreas académicas vinculadas a la electrónica y la computación se encuentran en constante demanda de recursos educativos de hardware y software en virtud de potenciar los conocimientos de los estudiantes. En el caso de las tecnologías con poca difusión o implementación en la industria regional, la principal opción en la importación de plataformas educativas adquiridas a empresas destinadas a la manufacturación de sistemas embebidos. Estas plataformas comerciales se clasifican según su implementación por lo que no siempre cubren los requerimientos académicos, por ejemplo, los requerimientos de hardware para las cátedras iniciales difieren de las cátedras avanzadas. Esta situación presenta la oportunidad de desarrollar una plataforma a la medida de las necesidades de las instituciones académicas. Si se dispone de las especificaciones por parte de los docentes, con la articulación de otras unidades académicas como laboratorios y grupos de investigación, es posible obtener un desarrollo que cubra las expectativas y aliente a la producción regional mediante la transferencias de tecnología.

En el proceso de aprendizaje de las denominadas Técnicas Digitales necesariamente se debe implementar los diseños digitales. El Álgebra de Bool con operaciones digitales simples, hasta la implementación de un microprocesador son prácticas comunes de los sistemas digitales lógicos y  resulta fundamental su ejercitación para concluir el ciclo de enseñanza.

Existen varios trabajos ya en la década de los 90s donde se plantaba \cite{ASArev.1} la necesidad de contar con una plataforma educativa que permitiera el estudio e implementación del diseño digital, sobre todo nuevas arquitecturas de microprocesadores. Si bien no se contaba con la capacidad de integración en la fabricación de circuitos integrados que se alcanzó en esta época, se apuntaba en aquel entonces al uso de nuevos dispositivos denominados FPGA\cite{PLD-hist}. Esta tendencia continuo al punto tal que se avanzaban con desarrollos de placas más avanzadas que ofrecían mucho más recursos debido al constante avance en el proceso de integración de los semiconductores. Se generaron proyectos académicos \cite{FPGA-platform-CPU-design}\cite{Low-Cost-Interactive-Rapid-Prototyping}\cite{FPGA-Based-Experiment-Platform-for-Multi-Core-System}, abiertos \cite{Building-an-Evolvable-Low-Cost-HWSW-Platform}\cite{NetFPGA} y comerciales \cite{Port-Emb-Linux-XUP-Virtex-II.Dev-Board}.

En estas últimas décadas los sistemas embebidos han cobrado una gran importancia, en particular se hace referencia a los Dispositivos Lógicos Programables (PLDs, siglas en inglés). Estos dispositivos lógicos actualmente ofrecen grandes recursos de hardware debido a los avances en los procesos de integración en su fabricación, obviamente que ha beneficiado a todos los circuitos integrados (ICs, siglas en inglés) en general.

Los Dispositivos Lógicos Programables fueron introducidos a medidos de 1970s. Se basaba en la idea de construir circuitos lógicos combinacionales que fueran programables. Contrariamente a los microprocesadores, los cuales pueden correr un programa sobre un hardware fijo, la programabilidad de los PLDs hace referencia a niveles de hardware. En otras palabras, un PLD es un chip de propósitos generales cuyo hardware puede ser reconfigurado dependiendo de especificaciones particulares del desarrollador.

Si bien las diferentes industrias (militar[REF], automotriz[REF], comunicaciones[REF], de consumo[REF], etc.) son quienes demandan constantemente avances tecnológicos, muchas veces el sector académico resulta ser el gestor de grandes desarrollos e investigaciones que beneficia a estas industrias. En nuestra región la tecnología PLDs se encuentra en su auge hace unos años. Instituciones gubernamentales de defensa[REF], aeroespaciales[REF], comunicaciones[REF] están implementando dispositivos como FPGAs y CPLDs en sus diseños. Además existe una constante actualización por parte de las instituciones académicas en los programas analíticos de las carreras relacionadas a los sistemas embebidos[REF].

En el estudio de nuevos sistemas digitales las herramientas de software son eficientes, pues permiten realizar simulaciones que se asemejan a la implementación física. Pero muchas veces son necesarias las implementaciones en hardware y es ahí donde se hacen necesarias las plataformas evaluadoras. Estas placas disponen de un diseño que cubre un gran espectro de aplicación según la tecnología y la complejidad del desarrollo. Este concepto no solo se aplica a los sistemas embebidos, pues varias áreas científicas requieren de un gran porcentaje de laboratorio[REF].

La mayoría de las plataformas de evaluación comerciales son fabricadas en el exterior del país. Se han encontrado desarrollos nacionales pero no son comercializados sino usados en laboratorios universitarios. Entre las empresas fabricantes de sistemas embebidos basados en dispositivos PLDs, se destacan: Xilix, Altera y Digilent. Los principales perfiles de sus desarrollos se encuentran orientados a,

\begin{itemize}

\item Sistemas de comunicaciones

\item Procesamiento de Señales Digitales (DSP)

\item Automovilismo

\end{itemize}

En la Figura [REF] se pueden ver tres diferentes plataformas orientadas al diseño de sistemas digitales \footnote{Alguna de estas plataformas disponen de módulos conversores ADC y DAC, por lo que se podría decir que también permiten la implementación de sistemas analógicos en dominio discreto.}. Los recursos de hardware que ofrecen estos desarrollos son:

\begin{itemize}

\item Puerto USB

\item Four 6-pin Pmod connectors

\item VGA

\item PS/2

\end{itemize}

Atmel AT90USB2 Full-speed USB2 port providing board power and programming/data transfer interface

Xilinx Platform Flash ROM to store FPGA configurations

8 LEDs, 4-digit 7-segment display, 4 buttons, 8 slide switches

PS/2 port and 8-bit VGA port

User-settable clock (25/50/100MHz), plus socket for 2 clock

Four 6-pin header expansion connectors

ESD and short-circuit protection on all I/O signals.

\begin{figure*}[!t]

  \centerline{

    \subfloat[Avnet Spartan-6 LX150T (Xilinx/Avnet)]{\includegraphics[width=2in]{img/Avnet-Spartan-6-lx9-MicroBoard}%

      \label{fig:xilinx-board}}

    \hfil

    \subfloat[DE0-Nano (Altera)]{\includegraphics[width=2in]{img/de0-nano}%

      \label{fig:altera-board}}

  \hfil

    \subfloat[BASYS2 (Digilent)]{\includegraphics[width=2in]{img/BASYS2-top-400}%

      \label{fig:digilent-board}}}

  \caption{Plataformas de desarrollo educativas basadas en FPGAs}

  \label{fig:board-fpga}

\end{figure*}

\section{Elección del PLD}

\section{Interfaz JTAG}

\subsection{Hardware}

\subsection{Software}

\section{Características}

\subsection{Perifericos}

\subsection{Potencia}

\section{Software}

\subsection{XC3Prog}

\subsection{OpenOCD}

\section{Implementación}

\section{Código abierto}

\section{Discusión}

Existen dos formas de solventar esta demanda, la primera opción es la adquisición de estos recursos a empresas que ofrecen plataformas educativas que cumplan con las especificaciones, pero aquí se presenta una segunda opción que es generar estas plataformas personalizadas a las necesidades de la región. Actualmente se dispone de los conocimientos necesarios para emprender un ciclo de trabajo donde las mismas unidades académicas cubren sus demandas a través de diferentes espacios como son los grupos de investigación y laboratorios

\section{Conclusiones}

% use section* for acknowledgement

\section*{Acknowledgment}

The authors would like to thank...

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% Note that \label must occur AFTER (or within) \caption.

% For figures, \caption should occur after the \includegraphics.

% Note that IEEEtran v1.7 and later has special internal code that

% is designed to preserve the operation of \label within \caption

% even when the captionsoff option is in effect. However, because

% of issues like this, it may be the safest practice to put all your

% \label just after \caption rather than within \caption{}.

%

% Reminder: the "draftcls" or "draftclsnofoot", not "draft", class

% option should be used if it is desired that the figures are to be

% displayed while in draft mode.

%

%\begin{figure}[!t]

%\centering

%\includegraphics[width=2.5in]{myfigure}

% where an .eps filename suffix will be assumed under latex,

% and a .pdf suffix will be assumed for pdflatex; or what has been declared

% via \DeclareGraphicsExtensions.

%\caption{Simulation Results}

%\label{fig_sim}

%\end{figure}

% Note that IEEE typically puts floats only at the top, even when this

% results in a large percentage of a column being occupied by floats.

% An example of a double column floating figure using two subfigures.

% (The subfig.sty package must be loaded for this to work.)

% The subfigure \label commands are set within each subfloat command, the

% \label for the overall figure must come after \caption.

% \hfil must be used as a separator to get equal spacing.

% The subfigure.sty package works much the same way, except \subfigure is

% used instead of \subfloat.

%

%\begin{figure*}[!t]

%\centerline{\subfloat[Case I]\includegraphics[width=2.5in]{subfigcase1}%

%\label{fig_first_case}}

%\hfil

%\subfloat[Case II]{\includegraphics[width=2.5in]{subfigcase2}%

%\label{fig_second_case}}}

%\caption{Simulation results}

%\label{fig_sim}

%\end{figure*}

%

% Note that often IEEE papers with subfigures do not employ subfigure

% captions (using the optional argument to \subfloat), but instead will

% reference/describe all of them (a), (b), etc., within the main caption.

% An example of a floating table. Note that, for IEEE style tables, the

% \caption command should come BEFORE the table. Table text will default to

% \footnotesize as IEEE normally uses this smaller font for tables.

% The \label must come after \caption as always.

%

%\begin{table}[!t]

%% increase table row spacing, adjust to taste

%\renewcommand{\arraystretch}{1.3}

% if using array.sty, it might be a good idea to tweak the value of

% \extrarowheight as needed to properly center the text within the cells

%\caption{An Example of a Table}

%\label{table_example}

%\centering

%% Some packages, such as MDW tools, offer better commands for making tables

%% than the plain LaTeX2e tabular which is used here.

%\begin{tabular}{|c||c|}

%\hline

%One & Two\\

%\hline

%Three & Four\\

%\hline

%\end{tabular}

%\end{table}

% Note that IEEE does not put floats in the very first column - or typically

% anywhere on the first page for that matter. Also, in-text middle ("here")

% positioning is not used. Most IEEE journals/conferences use top floats

% exclusively. Note that, LaTeX2e, unlike IEEE journals/conferences, places

% footnotes above bottom floats. This can be corrected via the \fnbelowfloat

% command of the stfloats package.

% trigger a \newpage just before the given reference

% number - used to balance the columns on the last page

% adjust value as needed - may need to be readjusted if

% the document is modified later

%\IEEEtriggeratref{8}

% The "triggered" command can be changed if desired:

%\IEEEtriggercmd{\enlargethispage{-5in}}

% references section

% can use a bibliography generated by BibTeX as a .bbl file

% BibTeX documentation can be easily obtained at:

% http://www.ctan.org/tex-archive/biblio/bibtex/contrib/doc/

% The IEEEtran BibTeX style support page is at:

% http://www.michaelshell.org/tex/ieeetran/bibtex/

%\bibliographystyle{IEEEtran}

% argument is your BibTeX string definitions and bibliography database(s)

%\bibliography{IEEEabrv,../bib/paper}

%

% <OR> manually copy in the resultant .bbl file

% set second argument of \begin to the number of references

% (used to reserve space for the reference number labels box)

\begin{thebibliography}{1}

% \bibitem{IEEEhowto:kopka}

% H.~Kopka and P.~W. Daly, \emph{A Guide to \LaTeX}, 3rd~ed.\hskip 1em plus

%   0.5em minus 0.4em\relax Harlow, England: Addison-Wesley, 1999.

\bibitem{ASArev.1}

Hiroyuki~Ochi, \emph{ASAver.1: An FPGA-Based Education Board for Computer Architecture/system Design}, Design Automation Conference 1997. Proceeding of the ASP-DAC'97. Asia and South Pacific. January 1997.

\bibitem{FPGA-platform-CPU-design}

C.~Chang, C.~Huang, Y.~Lin, Z.~Huang and T.~Hu, \emph{FPGA Platform for CPU Design and Applications},  5th. IEEE Conference on Nanotechnology. Nagoya, Japan. July 2005.

\bibitem{Building-an-Evolvable-Low-Cost-HWSW-Platform}

A.~Cicuttin, M.~Crespo, A.~Shapiro, N.~Abdallah, \emph{Building an Evolvable Low-Cost HW/SW Educational Platform -- Application to Virtual Instrumentation},  IEEE International Conference on Microelectronic Systems Education, MSE'07. 2007.

\bibitem{Low-Cost-Interactive-Rapid-Prototyping}

D.~Kang, S.~Hwang, K.~Jhang, K.~Yi, \emph{A Low Cost and Interactive Rapid Prototyping Platform For Digital System Design Education}, IEEE International Conference on Microelectronic Systems Education, MSE'07. 2007.

\bibitem{NetFPGA}

J.~Lockwood, N.~McKeown, G.~Watson, G.~Gibb, P.~Hartke, J.~Naous, R.~Raghuraman and J.~Luo, \emph{NetFPGA - An Open Platform for Gigabit-rate Network Switching and Routing}, IEEE International Conference on Microelectronic Systems Education, MSE'07. 2007.

\bibitem{FPGA-Based-Experiment-Platform-for-Multi-Core-System}

J.~Xing, W.~Zhao and H.~Hu, \emph{An FPGA-Based Experiment Platform for Multi-Cores System}, 9th. International Conference for Young Computer Scientistis, ICYCS'08. 2008.

\bibitem{Port-Emb-Linux-XUP-Virtex-II.Dev-Board}

Z.~Qingguo, Y.~Qi, L.~Chanjuan, H.~Bin, \emph{Port Embedded Linux to XUP Virtex-II Por Development Board}, IEEE. 2009.

\bibitem{PLD-hist}

K.~Parnell and N.~Mehta, \emph{Programmable Logic Design Quick Start Handbook}, Rev.~4. Xilinx Inc. 2004.

\end{thebibliography}

% that's all folks

\end{document}