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%% bare_conf.tex
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%% V1.3
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%% 2007/01/11
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%% by Michael Shell
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%% See:
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%% http://www.michaelshell.org/
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%% for current contact information.
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%%
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%% This is a skeleton file demonstrating the use of IEEEtran.cls
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%% (requires IEEEtran.cls version 1.7 or later) with an IEEE conference paper.
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%%
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%% Support sites:
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%% http://www.michaelshell.org/tex/ieeetran/
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%% http://www.ctan.org/tex-archive/macros/latex/contrib/IEEEtran/
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%% and
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%% http://www.ieee.org/
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%%*************************************************************************
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%% Legal Notice:
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%% This code is offered as-is without any warranty either expressed or
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%% implied; without even the implied warranty of MERCHANTABILITY or
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%% FITNESS FOR A PARTICULAR PURPOSE!
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%% User assumes all risk.
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%% In no event shall IEEE or any contributor to this code be liable for
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%% any damages or losses, including, but not limited to, incidental,
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%% consequential, or any other damages, resulting from the use or misuse
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%% of any information contained here.
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%%
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%% All comments are the opinions of their respective authors and are not
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%% necessarily endorsed by the IEEE.
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%%
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%% This work is distributed under the LaTeX Project Public License (LPPL)
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%% ( http://www.latex-project.org/ ) version 1.3, and may be freely used,
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%% distributed and modified. A copy of the LPPL, version 1.3, is included
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%% in the base LaTeX documentation of all distributions of LaTeX released
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%% 2003/12/01 or later.
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%% Retain all contribution notices and credits.
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%% ** Modified files should be clearly indicated as such, including  **
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%% ** renaming them and changing author support contact information. **
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%%
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%% File list of work: IEEEtran.cls, IEEEtran_HOWTO.pdf, bare_adv.tex,
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%%                    bare_conf.tex, bare_jrnl.tex, bare_jrnl_compsoc.tex
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%%*************************************************************************
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% *** Authors should verify (and, if needed, correct) their LaTeX system  ***
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% *** with the testflow diagnostic prior to trusting their LaTeX platform ***
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% *** with production work. IEEE's font choices can trigger bugs that do  ***
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% *** not appear when using other class files.                            ***
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% The testflow support page is at:
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% http://www.michaelshell.org/tex/testflow/
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% Note that the a4paper option is mainly intended so that authors in
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% countries using A4 can easily print to A4 and see how their papers will
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% look in print - the typesetting of the document will not typically be
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% affected with changes in paper size (but the bottom and side margins will).
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% Use the testflow package mentioned above to verify correct handling of
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% both paper sizes by the user's LaTeX system.
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%
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% Also note that the "draftcls" or "draftclsnofoot", not "draft", option
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% should be used if it is desired that the figures are to be displayed in
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% draft mode.
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%
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\documentclass[conference]{IEEEtran}
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% Add the compsoc option for Computer Society conferences.
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%
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% If IEEEtran.cls has not been installed into the LaTeX system files,
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% manually specify the path to it like:
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% \documentclass[conference]{../sty/IEEEtran}
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% Some very useful LaTeX packages include:
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% (uncomment the ones you want to load)
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% *** MISC UTILITY PACKAGES ***
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%
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%\usepackage{ifpdf}
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% Heiko Oberdiek's ifpdf.sty is very useful if you need conditional
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% compilation based on whether the output is pdf or dvi.
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% usage:
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% \ifpdf
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%   % pdf code
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% \else
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%   % dvi code
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% \fi
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% The latest version of ifpdf.sty can be obtained from:
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% http://www.ctan.org/tex-archive/macros/latex/contrib/oberdiek/
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% Also, note that IEEEtran.cls V1.7 and later provides a builtin
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% \ifCLASSINFOpdf conditional that works the same way.
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% When switching from latex to pdflatex and vice-versa, the compiler may
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% have to be run twice to clear warning/error messages.
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% *** CITATION PACKAGES ***
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%
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%\usepackage{cite}
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% cite.sty was written by Donald Arseneau
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% V1.6 and later of IEEEtran pre-defines the format of the cite.sty package
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% \cite{} output to follow that of IEEE. Loading the cite package will
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% result in citation numbers being automatically sorted and properly
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% "compressed/ranged". e.g., [1], [9], [2], [7], [5], [6] without using
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% cite.sty will become [1], [2], [5]--[7], [9] using cite.sty. cite.sty's
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% \cite will automatically add leading space, if needed. Use cite.sty's
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% noadjust option (cite.sty V3.8 and later) if you want to turn this off.
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% cite.sty is already installed on most LaTeX systems. Be sure and use
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% version 4.0 (2003-05-27) and later if using hyperref.sty. cite.sty does
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% not currently provide for hyperlinked citations.
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% The latest version can be obtained at:
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% http://www.ctan.org/tex-archive/macros/latex/contrib/cite/
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% The documentation is contained in the cite.sty file itself.
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% *** GRAPHICS RELATED PACKAGES ***
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%
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\ifCLASSINFOpdf
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\usepackage[pdftex]{graphicx}
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  % declare the path(s) where your graphic files are
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  % \graphicspath{{../pdf/}{../jpeg/}}
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  % and their extensions so you won't have to specify these with
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  % every instance of \includegraphics
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  % \DeclareGraphicsExtensions{.pdf,.jpeg,.png}
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\else
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  % or other class option (dvipsone, dvipdf, if not using dvips). graphicx
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  % will default to the driver specified in the system graphics.cfg if no
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  % driver is specified.
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  % \usepackage[dvips]{graphicx}
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  % declare the path(s) where your graphic files are
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  % \graphicspath{{../eps/}}
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  % and their extensions so you won't have to specify these with
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  % every instance of \includegraphics
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  % \DeclareGraphicsExtensions{.eps}
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\fi
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% graphicx was written by David Carlisle and Sebastian Rahtz. It is
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% required if you want graphics, photos, etc. graphicx.sty is already
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% installed on most LaTeX systems. The latest version and documentation can
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% be obtained at:
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% http://www.ctan.org/tex-archive/macros/latex/required/graphics/
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% Another good source of documentation is "Using Imported Graphics in
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% LaTeX2e" by Keith Reckdahl which can be found as epslatex.ps or
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% epslatex.pdf at: http://www.ctan.org/tex-archive/info/
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%
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% latex, and pdflatex in dvi mode, support graphics in encapsulated
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% postscript (.eps) format. pdflatex in pdf mode supports graphics
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% in .pdf, .jpeg, .png and .mps (metapost) formats. Users should ensure
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% that all non-photo figures use a vector format (.eps, .pdf, .mps) and
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% not a bitmapped formats (.jpeg, .png). IEEE frowns on bitmapped formats
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% which can result in "jaggedy"/blurry rendering of lines and letters as
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% well as large increases in file sizes.
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%
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% You can find documentation about the pdfTeX application at:
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% http://www.tug.org/applications/pdftex
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% *** MATH PACKAGES ***
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%
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%\usepackage[cmex10]{amsmath}
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% A popular package from the American Mathematical Society that provides
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% many useful and powerful commands for dealing with mathematics. If using
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% it, be sure to load this package with the cmex10 option to ensure that
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% only type 1 fonts will utilized at all point sizes. Without this option,
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% it is possible that some math symbols, particularly those within
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% footnotes, will be rendered in bitmap form which will result in a
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% document that can not be IEEE Xplore compliant!
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%
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% Also, note that the amsmath package sets \interdisplaylinepenalty to 10000
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% thus preventing page breaks from occurring within multiline equations. Use:
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%\interdisplaylinepenalty=2500
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% after loading amsmath to restore such page breaks as IEEEtran.cls normally
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% does. amsmath.sty is already installed on most LaTeX systems. The latest
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% version and documentation can be obtained at:
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% http://www.ctan.org/tex-archive/macros/latex/required/amslatex/math/
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% *** SPECIALIZED LIST PACKAGES ***
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%\usepackage{algorithmic}
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% algorithmic.sty was written by Peter Williams and Rogerio Brito.
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% This package provides an algorithmic environment fo describing algorithms.
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% You can use the algorithmic environment in-text or within a figure
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% environment to provide for a floating algorithm. Do NOT use the algorithm
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% floating environment provided by algorithm.sty (by the same authors) or
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% algorithm2e.sty (by Christophe Fiorio) as IEEE does not use dedicated
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% algorithm float types and packages that provide these will not provide
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% correct IEEE style captions. The latest version and documentation of
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% algorithmic.sty can be obtained at:
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% http://www.ctan.org/tex-archive/macros/latex/contrib/algorithms/
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% There is also a support site at:
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% http://algorithms.berlios.de/index.html
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% Also of interest may be the (relatively newer and more customizable)
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% algorithmicx.sty package by Szasz Janos:
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% http://www.ctan.org/tex-archive/macros/latex/contrib/algorithmicx/
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% *** ALIGNMENT PACKAGES ***
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%
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%\usepackage{array}
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% Frank Mittelbach's and David Carlisle's array.sty patches and improves
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% the standard LaTeX2e array and tabular environments to provide better
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% appearance and additional user controls. As the default LaTeX2e table
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% generation code is lacking to the point of almost being broken with
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% respect to the quality of the end results, all users are strongly
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% advised to use an enhanced (at the very least that provided by array.sty)
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% set of table tools. array.sty is already installed on most systems. The
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% latest version and documentation can be obtained at:
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%\usepackage{mdwmath}
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% Also highly recommended is Mark Wooding's extremely powerful MDW tools,
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% especially mdwmath.sty and mdwtab.sty which are used to format equations
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% and tables, respectively. The MDWtools set is already installed on most
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% LaTeX systems. The lastest version and documentation is available at:
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% http://www.ctan.org/tex-archive/macros/latex/contrib/mdwtools/
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% (automatically sized) equal width boxes - aka "natural width parboxes".
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% *** SUBFIGURE PACKAGES ***
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%\usepackage[tight,footnotesize]{subfigure}
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% subfigure.sty was written by Steven Douglas Cochran. This package makes it
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% easy to put subfigures in your figures. e.g., "Figure 1a and 1b". For IEEE
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% work, it is a good idea to load it with the tight package option to reduce
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% the amount of white space around the subfigures. subfigure.sty is already
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% installed on most LaTeX systems. The latest version and documentation can
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% http://www.ctan.org/tex-archive/obsolete/macros/latex/contrib/subfigure/
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% subfigure.sty has been superceeded by subfig.sty.
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%\usepackage[caption=false]{caption}
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\usepackage[font=footnotesize,caption=false]{subfig}
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% subfig.sty, also written by Steven Douglas Cochran, is the modern
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% automatically loads Axel Sommerfeldt's caption.sty which will override
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% IEEEtran.cls handling of captions and this will result in nonIEEE style
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% figure/table captions. To prevent this problem, be sure and preload
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% caption.sty with its "caption=false" package option. This is will preserve
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% IEEEtran.cls handing of captions. Version 1.3 (2005/06/28) and later
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% (recommended due to many improvements over 1.2) of subfig.sty supports
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% the caption=false option directly:
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%\usepackage[caption=false,font=footnotesize]{subfig}
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% http://www.ctan.org/tex-archive/macros/latex/contrib/subfig/
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% The latest version and documentation of caption.sty can be obtained at:
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% http://www.ctan.org/tex-archive/macros/latex/contrib/caption/
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%\usepackage{fixltx2e}
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% guaranteed to be preserved. Thus, an unpatched LaTeX2e can allow a
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% Documentation is contained in the stfloats.sty comments as well as in the
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% --------------- USEPACKAGE agregados por guanucoluis ----------------
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%\usepackage[spanish]{babel}
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%\usepackage[pdftex]{graphicx}
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% ------------------------- Agregados por maxi ------------------------
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\renewcommand{\abstractname}{Resumen}
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%\abstractname   Abstract
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% *** PDF, URL AND HYPERLINK PACKAGES ***
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\hyphenation{op-tical net-works semi-conduc-tor}
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\begin{document}
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%
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\title{Plataforma de Hardware Reconfigurable para el Diseño de Sistemas Digitales}
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\author{\IEEEauthorblockN{Alexis Maximiliano Quiteros, Luis Alberto Guanuco, Sergio Daniel Olmedo}
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\IEEEauthorblockA{Centro Universitario de Desarrollo en Automoción y Robótica\\
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Universidad Tecnológica Nacional\\
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Facultad Regional Córdoba\\
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Email: maximiliano.quinteros@gmail.com, lguanuco@electronica.frc.utn.edu.ar, solmedo@scdt.frc.utn.edu.ar}
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% \and
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% \IEEEauthorblockN{Luis Alberto Guanuco}
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% \IEEEauthorblockA{Departamento de Ingeniería Electrónica\\
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% Universidad Tecnológica Nacional\\
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% Facultad Regional Córdoba\\
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% Email: lguanuco@electronica.frc.utn.edu.ar}
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% \and
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% \IEEEauthorblockN{Sergio Daniel Olmedo}
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% \IEEEauthorblockA{CUDAR\\%Centro Universitario de Desarrollo en Automoción y Robótica\\
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% Universidad Tecnológica Nacional\\
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% Facultad Regional Córdoba\\
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% Email: solmedo@scdt.frc.utn.edu.ar}
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}
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%\author{\IEEEauthorblockN{Michael Shell\IEEEauthorrefmark{1},
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%Homer Simpson\IEEEauthorrefmark{2},
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%Eldon Tyrell\IEEEauthorrefmark{4}}
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%\IEEEauthorblockA{\IEEEauthorrefmark{1}School of Electrical and Computer Engineering\\
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%Georgia Institute of Technology,
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%Atlanta, Georgia 30332--0250\\ Email: see http://www.michaelshell.org/contact.html}
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%\IEEEauthorblockA{\IEEEauthorrefmark{2}Twentieth Century Fox, Springfield, USA\\
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%Email: homer@thesimpsons.com}
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%\IEEEauthorblockA{\IEEEauthorrefmark{3}Starfleet Academy, San Francisco, California 96678-2391\\
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%Telephone: (800) 555--1212, Fax: (888) 555--1212}
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\begin{abstract}
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La contaste evolución de los sistemas electrónicos (digitales y analógicos) exige la búsqueda de nuevas herramientas para la formación académica. En el caso del diseños de sistemas digitales una excelente alternativa es el uso placas de evaluación basadas en dispositivos lógicos programables (PLDs). En función de los requerimientos y necesidades académicas que demandan recursos de hardware, y las oportunidades concretas de desarrollar una plataforma personalizada a las necesidades plateadas es que se presenta una plataforma reconfigurable con especificaciones abiertas. Este diseño cuenta con periféricos básicos con que se pueda interactuar en la implementación de sistemas digitales, pero además cuenta con una FPGA que dispone de una gran cantidad de recursos internos para el uso en sistemas digitales avanzados que requieren gran capacidad de procesamiento. El proyecto se publica en forma libre (licencia GPL) buscando incentivar a otras grupos académicos en la  modificación y adaptación de este trabajo a sus necesidades como así también proponer mejoras en versiones futuras de la plataforma.
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\end{abstract}
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\IEEEpeerreviewmaketitle
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\section{Introducción}
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Las áreas académicas vinculadas a la electrónica y la computación se encuentran en constante demanda de recursos educativos de hardware y software en virtud de potenciar los conocimientos de los estudiantes. En el caso de las tecnologías con poca difusión o implementación en la industria regional, la principal opción en la importación de plataformas educativas adquiridas a empresas destinadas a la manufacturación de sistemas embebidos. Estas plataformas comerciales se clasifican según su implementación por lo que no siempre cubren los requerimientos académicos. Por ejemplo, en el área de las técnicas digitales, los requerimientos de hardware para las cátedras iniciales difieren de las cátedras avanzadas. Esta situación presenta la oportunidad de desarrollar una plataforma a la medida de las necesidades de las instituciones académicas. Si se dispone de las especificaciones por parte de los docentes, la articulación de otras unidades académicas como laboratorios y grupos de investigación, es posible obtener un desarrollo que cubra las expectativas y aliente a la producción regional de plataformas educativas en un marco de transferencia de tecnología.
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En el proceso de aprendizaje de las denominadas Técnicas Digitales necesariamente se debe implementar los diseños digitales. Desde el Álgebra de Bool, con operaciones digitales simples, hasta la implementación de un microprocesador son prácticas comunes de los sistemas digitales lógicos y resulta fundamental su ejercitación para concluir el ciclo de enseñanza.
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Al comienzo de la década de los 90s surgieron varios trabajos donde se planteaba la necesidad de una plataforma educativa orientada a la implementación de diseños lógicos digitales basados en PLDs. Los principales demandantes de estas plataformas eran diseñadores de arquitecturas de microprocesadores \cite{ASArev.1}, desarrollos que años anteriores resultaban imposibles por el costo de la implementación en hardware. El avance en el proceso de integración de los circuitos integrados han llevado a que se desarrollen plataformas más complejas que ofrecen una gran cantidad de recursos de hardware. Al día de hoy se han generado varios proyectos desarrollados por instituciones académicas \cite{FPGA-platform-CPU-design}\cite{Low-Cost-Interactive-Rapid-Prototyping}\cite{FPGA-Based-Experiment-Platform-for-Multi-Core-System}, otras con especificaciones abiertas \cite{Building-an-Evolvable-Low-Cost-HWSW-Platform}\cite{NetFPGA} y también con fines comerciales \cite{Port-Emb-Linux-XUP-Virtex-II.Dev-Board}. Todos estos trabajos tienen algunas características en común:
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\begin{itemize}
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\item El dispositivo lógico programable base es una FPGA
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\item Memoria de programación de la FPGA
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\item Acceso de programación JTAG
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\item Software para interactuar con la plataforma desde una computadora
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\item Dos perfiles de diseño:
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  \begin{itemize}
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  \item Para la implementación de sistemas lógicos generales
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  \item Orientado a un área específica
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  \end{itemize}
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\end{itemize}
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La caracterización anterior no es un intento de generalizar a todas las plataformas educativas basadas en PLDs, pero sí resulta útil para definir el perfil de la plataforma que se describe en este trabajo. Sin la especificación de a que usuarios se destina una plataforma, no se puede comenzar con el estudio de los diferentes dispositivos que se utilizarán. La Figura \ref{fig:rec-plataforma} ilustra una clasificación en bloques de los recursos que ofrecen diferentes plataformas basada en dispositivos PLDs. Donde a niveles iniciales en el estudio de la lógica digital se requieren periféricos básicos como ser llaves conmutadoras de los estados lógicos, dispositivos indicadores como diodos LED, etc. Mientras que a estudios más avanzados se requieren otros tipos de dispositivos como ser a un nivel medio controladores para display gráficos LCD/LED, comunicaciones entre varios dispositivos mediante SPI, I2C, etc. Y por últimos, en la formación de especialistas de sistemas embebidos, requieren recursos como interfaces físicos para ethernet, controladores HDMI, PS2, USB, etc.
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\begin{figure}[!t]
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\centering
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\includegraphics[width=5cm]{img/recursos-plataformas}
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\caption{Recursos de hardware en función de los niveles de aprendizaje.}
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\label{fig:rec-plataforma}
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\end{figure}
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La mayoría de las plataformas de evaluación comerciales son fabricadas en el exterior del país. Se han encontrado desarrollos nacionales pero no son comercializados sino usados en laboratorios universitarios. Entre las empresas fabricantes de sistemas embebidos basados en dispositivos PLDs, se destacan: Xilix, Altera y Digilent. Los principales perfiles de sus desarrollos se encuentran orientados a,
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\begin{itemize}
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\item Sistemas de comunicaciones
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\item Procesamiento de Señales Digitales (DSP)
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\item Automovilismo
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\end{itemize}
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En la Figura [REF] se pueden ver tres diferentes plataformas orientadas al diseño de sistemas digitales \footnote{Alguna de estas plataformas disponen de módulos conversores ADC y DAC, por lo que se podría decir que también permiten la implementación de sistemas analógicos en dominio discreto.}. Los recursos de hardware que ofrecen estos desarrollos son:
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\begin{itemize}
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\item FPGA
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\item Memoria de programación de la FPGA
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\item Periféricos básicos (LEDs, display, pulsadores, llaves, etc.)
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\item Puerto USB
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\item Puerto para módulos externos
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\item Puerto para propósitos generales
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\item Varias señales de reloj (clok)
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\item VGA y PS/2
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\item Memorias ROM/RAM
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\item ADC/DAC
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\end{itemize}
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% \begin{figure*}[!t]
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%   \centerline{
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%     \subfloat[Avnet Spartan-6 LX150T (Xilinx/Avnet)]{\includegraphics[width=2in]{img/Avnet-Spartan-6-lx9-MicroBoard}%
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%       \label{fig:xilinx-board}}
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%     \hfil
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%       \label{fig:digilent-board}}}
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%   \caption{Plataformas de desarrollo educativas basadas en FPGAs}
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%   \label{fig:board-fpga}
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% \end{figure*}
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En nuestra región la tecnología PLDs se encuentra en su auge hace unos años. Instituciones gubernamentales de defensa[REF], aeroespaciales[REF], comunicaciones[REF] están implementando dispositivos como FPGAs y CPLDs en sus diseños. Además existe una constante actualización por parte de las instituciones académicas en los programas analíticos de las carreras relacionadas a los sistemas embebidos[REF].
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En base al planteamiento anterior lleva al desarrollo de la Plataforma de Hardware Reconfigurable (PHR). Esta plataforma es un proyecto a medida de las necesidades en la  enseñanza de los sistemas digitales lógicos en las cátedras iniciales. Ofrece recursos básicos para que los estudiantes interactúen con la tecnología de los dispositivos PLDs, pero también dispone de puertos para conectar otros recursos físicos permitiendo que estudiantes avanzados puedan hacer uso de ellas sin limitaciones. Además al ser publicado bajo licencia libre/abierta permitirá a que el diseño, o parte de él, sirva como referencias a otras instituciones académicas que se encuentren en búsqueda de una plataforma para implementar en sus diferentes cátedras.
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\section{Elección del PLD}
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\section{Interfaz JTAG}
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\subsection{Hardware}
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\subsection{Software}
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\section{Características}
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\subsection{Perifericos}
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\subsection{Potencia}
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\section{Software}
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\subsection{XC3Prog}
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\subsection{OpenOCD}
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\section{Implementación}
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\section{Código abierto}
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\section{Discusión}
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Existen dos formas de solventar esta demanda, la primera opción es la adquisición de estos recursos a empresas que ofrecen plataformas educativas que cumplan con las especificaciones, pero aquí se presenta una segunda opción que es generar estas plataformas personalizadas a las necesidades de la región. Actualmente se dispone de los conocimientos necesarios para emprender un ciclo de trabajo donde las mismas unidades académicas cubren sus demandas a través de diferentes espacios como son los grupos de investigación y laboratorios
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\section{Conclusiones}
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% use section* for acknowledgement
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\section*{Acknowledgment}
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The authors would like to thank...
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% H.~Kopka and P.~W. Daly, \emph{A Guide to \LaTeX}, 3rd~ed.\hskip 1em plus
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%   0.5em minus 0.4em\relax Harlow, England: Addison-Wesley, 1999.
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\bibitem{ASArev.1}
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Hiroyuki~Ochi, \emph{ASAver.1: An FPGA-Based Education Board for Computer Architecture/system Design}, Design Automation Conference 1997. Proceeding of the ASP-DAC'97. Asia and South Pacific. January 1997.
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\bibitem{FPGA-platform-CPU-design}
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C.~Chang, C.~Huang, Y.~Lin, Z.~Huang and T.~Hu, \emph{FPGA Platform for CPU Design and Applications},  5th. IEEE Conference on Nanotechnology. Nagoya, Japan. July 2005.
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\bibitem{Building-an-Evolvable-Low-Cost-HWSW-Platform}
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A.~Cicuttin, M.~Crespo, A.~Shapiro, N.~Abdallah, \emph{Building an Evolvable Low-Cost HW/SW Educational Platform -- Application to Virtual Instrumentation},  IEEE International Conference on Microelectronic Systems Education, MSE'07. 2007.
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\bibitem{Low-Cost-Interactive-Rapid-Prototyping}
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D.~Kang, S.~Hwang, K.~Jhang, K.~Yi, \emph{A Low Cost and Interactive Rapid Prototyping Platform For Digital System Design Education}, IEEE International Conference on Microelectronic Systems Education, MSE'07. 2007.
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\bibitem{NetFPGA}
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J.~Lockwood, N.~McKeown, G.~Watson, G.~Gibb, P.~Hartke, J.~Naous, R.~Raghuraman and J.~Luo, \emph{NetFPGA - An Open Platform for Gigabit-rate Network Switching and Routing}, IEEE International Conference on Microelectronic Systems Education, MSE'07. 2007.
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\bibitem{FPGA-Based-Experiment-Platform-for-Multi-Core-System}
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J.~Xing, W.~Zhao and H.~Hu, \emph{An FPGA-Based Experiment Platform for Multi-Cores System}, 9th. International Conference for Young Computer Scientistis, ICYCS'08. 2008.
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\bibitem{Port-Emb-Linux-XUP-Virtex-II.Dev-Board}
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Z.~Qingguo, Y.~Qi, L.~Chanjuan, H.~Bin, \emph{Port Embedded Linux to XUP Virtex-II Por Development Board}, IEEE. 2009.
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\bibitem{PLD-hist}
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K.~Parnell and N.~Mehta, \emph{Programmable Logic Design Quick Start Handbook}, Rev.~4. Xilinx Inc. 2004.
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\end{thebibliography}
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% that's all folks
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\end{document}
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