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%\documentclass[handout]{beamer}
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\documentclass{beamer}
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\usepackage [utf8] {inputenc}
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\usepackage [spanish] {babel}
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\usepackage{graphicx}
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\graphicspath{{images/}}
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%\setbeamertemplate{navigation symbols}{} % borra los controles de navegación
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\usetheme{Warsaw}
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%\usetheme{Frankfurt}
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\usecolortheme[RGB={70,70,255}]{structure}
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\setbeamercovered{transparent=0}
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%\setbeamercovered{transparent=40}
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%\beamersetuncovermixins{\opaqueness<1>{25}}{\opaqueness<2->{15}}
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\title{Plataforma de Hardware Reconfigurable}
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\author{Luis Guanuco, Sergio Olmedo, Maximiliano Quinteros}
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\date{\today}
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\institute{Centro Universitario de Desarrollo en Automoción y Robótica\\Universidad Tecnológica Nacional, Facultad Regional Córdoba}
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\titlegraphic{\includegraphics[width=5.5cm]{phr_small.png}}
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\AtBeginSection[]{
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\begin{frame}
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\frametitle{Contenidos}
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\tableofcontents[currentsection,hideallsubsections]
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\end{frame}
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}
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\begin{document}
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\begin{frame}
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\titlepage
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%\transfade
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\end{frame}
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\begin{frame}\frametitle{Contenidos}
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%\transfade
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\tableofcontents[hideallsubsections]
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\end{frame}
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\section{Introducción}
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\begin{frame}
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\frametitle{Introducción}
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\begin{center}
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\includegraphics[width=0.6\textwidth]{prof.pdf}
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\end{center}
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\end{frame}
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\begin{frame}
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\frametitle{Kit CPLD}
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\begin{center}
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\includegraphics[height=0.5\textheight]{kit_cpld_per.png} \hspace{1ex}
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\includegraphics[height=0.4\textheight]{kit_cpld.png}
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\end{center}
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\end{frame}
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\begin{frame}
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\frametitle{Plataforma de Hardware Reconfigurable}
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\begin{center}
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\includegraphics[width=1\textwidth]{phr_small.png}
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\end{center}
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\end{frame}
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\section[Diagrama de bloques]{Diagrama de bloques del Hardware}
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\begin{frame}
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\frametitle{Diagrama de bloques del Hardware}
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\transfade
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\begin{center}
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\includegraphics<1>[width=0.9\textwidth]{block1.pdf}
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\includegraphics<2>[width=0.9\textwidth]{block2.pdf}
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\includegraphics<3>[width=0.9\textwidth]{block3.pdf}
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\end{center}
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\end{frame}
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\section{Placa PHR}
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\begin{frame}
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\frametitle{Placa PHR}
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\begin{center}
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\includegraphics[width=\textwidth]{phr_text.png}
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\end{center}
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\end{frame}
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\subsection{Características}
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\begin{frame}
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\frametitle{Características}
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\begin{description}[Memoria PROM:]
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\item [FPGA:] Xilinx Spartan-3A XC3S200A (VQG100).
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\pause
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\item [Memoria PROM:] Xilinx XCF02S.
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\pause
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\item [Voltaje entrada:] 5V.
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\pause
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\item [Relojes:] Un reloj fijo y tres seleccionables:
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\begin{enumerate}
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\item 50 MHz.
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\item 16 MHz, 1 MHz, 500 kHz y 250 kHz.
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\item 125 kHz, 62.5 kHz, 31.25 kHz, 15.625 kHz.
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\item 3.9062 kHz, 1.9531 kHz, 976,56251 Hz.
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\end{enumerate}
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\pause
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\item [GPIO:] 28 pines en total.
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\end{description}
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\end{frame}
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\begin{frame}[b]
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\frametitle{Periféricos}
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\only<1-5>{
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\begin{itemize}
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\item \textbf<1>{8 LEDs}
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\item \textbf<2>{8 llaves (DIP switch)}
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\item \textbf<3>{4 pulsadores}
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\item \textbf<4>{Display de 7 segmentos cuádruple}
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\item \textbf<5>{Puerto serie}
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\end{itemize}
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}
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%\vspace{3cm}
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\begin{center}
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\includegraphics<1>[width=1\textwidth]{phr_top_leds.png}
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\includegraphics<2>[width=1\textwidth]{phr_top_switches.png}
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\includegraphics<3>[width=1\textwidth]{phr_top_botones.png}
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\includegraphics<4>[width=1\textwidth]{phr_top_display.png}
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\includegraphics<5>[width=1\textwidth]{phr_top_nada.png}
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\includegraphics<6>[width=1\textwidth]{phr_top.png}
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\end{center}
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\vspace{1ex}
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\end{frame}
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\section{Placa S3Power}
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\begin{frame}
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\frametitle{Placa S3Power}
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\begin{center}
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\includegraphics[width=0.8\textwidth]{s3power_small.png}
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\end{center}
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\end{frame}
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\subsection{INTI}
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\begin{frame}
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\frametitle{INTI}
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\begin{center}
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\includegraphics[width=0.6\textwidth]{s3power_inti.png}
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Christian Huy y Diego Brengi
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Instituto Nacional de Tecnología Industrial
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\end{center}
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\end{frame}
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\subsection{Requerimientos de alimentación de la FPGA}
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\begin{frame}
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\frametitle{Voltajes de alimentación}
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\begin{center}
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\begin{tabular}{|c|p{4.5cm}|p{3cm}|}
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\hline
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\textbf{Entrada} & \textbf{Alimienta a} & \textbf{Tensión nominal} \\ \hline
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\hline
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VCCINT & Núcleo interno (CLBs, bloques de RAM). & 1.2V \\ \hline
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VCCAUX & DCMs, drivers diferenciales, pines de configuración dedicados y la interfaz JTAG. & 2.5V o 3.3V \\ \hline
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VCCO0 & Banco de E/S número 0. & 3.3V, 3.0V, 2.5V, 1.8V, 1.5V y 1.2V. \\ \hline
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VCCO1 & Banco de E/S número 1. & 3.3V, 3.0V, 2.5V, 1.8V, 1.5V y 1.2V. \\ \hline
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VCCO2 & Banco de E/S número 2. & 3.3V, 3.0V, 2.5V, 1.8V, 1.5V y 1.2V. \\ \hline
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VCCO3 & Banco de E/S número 3. & 3.3V, 3.0V, 2.5V, 1.8V, 1.5V y 1.2V. \\ \hline
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\end{tabular}
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\end{center}
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\end{frame}
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\begin{frame}
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\frametitle{Circuito POR}
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El circuito \emph{Power On RESET} verifica:
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\begin{itemize}
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\item VCCINT
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\item VCCAUX
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\item VCCO2
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\end{itemize}
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\pause
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Tiempos de encendido:
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\begin{center}
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\begin{tabular}{|c|l|c|c|}
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\hline
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\textbf{Símbolo} & \textbf{Rampa de} & \textbf{Min} & \textbf{Max} \\ \hline
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\hline
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VCCINTR & VCCINT & 0.2 ms & 100 ms \\ \hline
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VCCAUXR & VCCAUX & 0.2 ms & 100 ms \\ \hline
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VCCO2R & VCCO del Banco 2 & 0.2 ms & 100 ms \\ \hline
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\end{tabular}
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\end{center}
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\end{frame}
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\subsection{S3Power}
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\begin{frame}
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\frametitle{Voltajes elegidos}
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\begin{itemize}
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\item 1.2V y 2.5A para la lógica interna.
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\item 3.3V y 2.5A para los bancos de pines.
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\item 2.5V y 200mA para el módulo de comunicación JTAG.
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\end{itemize}
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\end{frame}
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\begin{frame}
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\frametitle{El chip TPS75003}
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\begin{itemize}
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\item<1-> Posee tres reguladores de tensión: Dos tipo Buck de 3A y eficiencia del 95\% y otro regulador lineal de 300 mA.
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\item<2-> Voltaje de entrada de entre 2.2V y 6.5 V.
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\item<3-> Arranque suave e independiente para cada regulador.
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\item<4-> Tensiones ajustables de 1.2 V a 6.5 V para los convertidores Buck y de 1.0 V a 6.5 V para el convertidor lineal.
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\end{itemize}
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\end{frame}
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\begin{frame}
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\frametitle{Arranque medido}
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\begin{center}
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\includegraphics[width=0.9\textwidth]{arranque.pdf}
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\end{center}
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\end{frame}
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\section{Placa OOCDLink}
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\begin{frame}
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\frametitle{Placa OOCDLink}
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\begin{center}
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\includegraphics[width=0.8\textwidth]{oocdlink_small.png}
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\end{center}
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\end{frame}
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\subsection{FTDI chip}
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\begin{frame}
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\frametitle{FTDIchip}
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\begin{center}
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\includegraphics[width=1\textwidth]{FTblock.pdf}
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\end{center}
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\end{frame}
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\section{Configuración de la FPGA}
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\begin{frame}
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\frametitle{Modos de configuración (familia Spartan-3A)}
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\begin{itemize}
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\item \textbf<2>{\textsl{Master Serial} desde una memoria PROM Flash de Xilinx}
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\item \textsl{Serial Peripheral Interface} (SPI) desde una memoria Flash SPI
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\item \textsl{Byte Peripheral Interface} (BPI) desde una memoria NOR Flash
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\item \textsl{Slave Serial}, típicamente cargada desde un procesador
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\item \textsl{Slave Parallel}, típicamente cargada desde un procesador
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\item \textbf<2>{\textsl{Boundary Scan} (JTAG), típicamente cargada desde un procesador}
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\end{itemize}
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\end{frame}
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\begin{frame}
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\frametitle{Selección de los modos de configuración}
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\includegraphics[width=1\textwidth]{config_modes.pdf}
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\end{frame}
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\begin{frame}
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\frametitle{Circuito de configuración}
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\includegraphics[width=1\textwidth]{conf_mod_sche.pdf}
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\end{frame}
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\subsection{Software}
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\begin{frame}
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\frametitle{xc3sprog}
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\begin{center}
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\includegraphics[width=1\textwidth]{xc3sprog.pdf}
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\end{center}
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\end{frame}
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\begin{frame}
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\frametitle{xc3sprog}
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\begin{center}
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\includegraphics[width=0.8\textwidth]{front-end.pdf}
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\end{center}
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\end{frame}
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\begin{frame}
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\frametitle{PHR GUI}
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\begin{center}
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\includegraphics[width=0.8\textwidth]{phr-gui.png}
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\end{center}
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\end{frame}
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\appendix
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\section*{Terminando}
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\begin{frame}
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\begin{center}
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\includegraphics[width=1\textwidth]{opencores.png}
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\end{center}
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\end{frame}
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\begin{frame}
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\frametitle{¿Preguntas?}
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\begin{center}
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\includegraphics[width=0.8\textwidth]{question.pdf}
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\end{center}
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\end{frame}
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\begin{frame}
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\frametitle{¿Preguntas?}
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\begin{center}
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| 331 |
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\includegraphics[height=0.9\textheight]{question_.pdf}
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| 332 |
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\end{center}
|
| 333 |
|
|
\end{frame}
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| 334 |
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|
|
| 335 |
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|
|
| 336 |
277 |
maximiq |
\end{document}
|
