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%\documentclass[handout]{beamer}
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\documentclass{beamer}
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\usepackage [utf8] {inputenc}
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\usepackage [spanish] {babel}
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\usepackage{graphicx}
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\graphicspath{{images/}}
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%\setbeamertemplate{navigation symbols}{} % borra los controles de navegación
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%\usetheme{Warsaw}
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\usetheme{Frankfurt}
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\usecolortheme[RGB={70,70,255}]{structure}
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%\setbeamercovered{transparent=40}
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%\beamersetuncovermixins{\opaqueness<1>{25}}{\opaqueness<2->{15}}
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\title{Plataforma de Hardware Reconfigurable}
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\author{Luis Guanuco, Sergio Olmedo, Maximiliano Quinteros}
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\date{\today}
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\institute{Centro Universitario de Desarrollo en Automoción y Robótica\\Universidad Tecnológica Nacional, Facultad Regional Córdoba}
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% \logo{%
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% \includegraphics[width=0.1\paperwidth,keepaspectratio]{CUDARlogo}%
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% \hspace{\dimexpr\paperwidth-2cm-5pt}%
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% \includegraphics[width=0.05\paperwidth,keepaspectratio]{UTNlogo}%
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%}
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% logo of my university
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% \titlegraphic{\includegraphics[width=2cm]{logopolito}\hspace*{4.75cm}~%
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% \includegraphics[width=2cm]{logopolito}
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% }
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\titlegraphic{\includegraphics[width=5.5cm]{phr_small.png}}
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\AtBeginSection[]{
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\begin{frame}
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\frametitle{Contenidos}
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\tableofcontents[currentsection,hideallsubsections]
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\end{frame}
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}
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\begin{document}
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\begin{frame}
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\titlepage
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\end{frame}
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\begin{frame}
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\frametitle{Contenidos}
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\tableofcontents[hideallsubsections]
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\end{frame}
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%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
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\section{Introducción}
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%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
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\begin{frame}
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\frametitle{Introducción}
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\begin{center}
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\includegraphics[width=0.6\textwidth]{prof.pdf}
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\end{center}
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\end{frame}
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\begin{frame}
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\frametitle{Kit CPLD}
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\begin{center}
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\includegraphics[height=0.5\textheight]{kit_cpld_per.png} \hspace{1ex}
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\includegraphics[height=0.4\textheight]{kit_cpld.png}
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\end{center}
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\end{frame}
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\begin{frame}
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\frametitle{Plataforma de Hardware Reconfigurable}
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\begin{center}
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\includegraphics[width=1\textwidth]{phr_small.png}
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\end{center}
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\end{frame}
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\begin{frame}
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\frametitle{Hardware libre}
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\begin{center}
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\includegraphics[width=0.9\textwidth]{Ohw-logo.pdf}
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\end{center}
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\end{frame}
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\section[Diagrama de bloques]{Diagrama de bloques del Hardware}
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\begin{frame}
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\frametitle{Diagrama de bloques del Hardware}
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\transfade
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\begin{center}
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\includegraphics<1>[width=0.9\textwidth]{block1.pdf}
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\includegraphics<2>[width=0.9\textwidth]{block2.pdf}
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\includegraphics<3>[width=0.9\textwidth]{block3.pdf}
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\end{center}
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\end{frame}
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%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
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\section{Placa PHR}
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%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
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\begin{frame}
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\frametitle{Placa PHR}
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\begin{center}
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\includegraphics[width=\textwidth]{phr_text.png}
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\end{center}
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\end{frame}
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\subsection{Características} %%%%%%%%%%%%%%%%%%%%%%%%%%%
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\begin{frame}
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\frametitle{Características}
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\begin{description}[Memoria PROM:]
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\item [FPGA:] Xilinx Spartan-3A XC3S200A (VQG100).
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\pause
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\item [Memoria PROM:] Xilinx XCF02S.
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\pause
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\item [Voltaje entrada:] 5V.
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\pause
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\item [Relojes:] Un reloj fijo y tres seleccionables:
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\begin{enumerate}
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\item 50 MHz.
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\item 16 MHz, 1 MHz, 500 kHz y 250 kHz.
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\item 125 kHz, 62.5 kHz, 31.25 kHz, 15.625 kHz.
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\item 3.9062 kHz, 1.9531 kHz, 976,56251 Hz.
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\end{enumerate}
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\pause
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\item [GPIO:] 28 pines en total.
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\end{description}
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\end{frame}
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\begin{frame}
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\frametitle{El chip FPGA (XC3S200A)}
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\begin{description}[E/S pares diferenciales máximo:]
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\item [Número de compuertas:] 200K
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\item [Celdas lógicas equivalentes:] 4032
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\item [CLBs:] 448
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\item [Bits de RAM distribuida:] 28K
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\item [Bits de Bloques de RAM:] 288K
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\item [Multiplicadores dedicados:] 16
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\item [DCMs:] 4
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\item [Máximo número de E/S:] 248
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\item [E/S pares diferenciales máximo:] 112
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\end{description}
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\end{frame}
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\begin{frame}[b]
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\frametitle{Periféricos}
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\only<1-5>{
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\begin{itemize}
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\item \textbf<1>{8 LEDs}
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\item \textbf<2>{8 llaves (\emph{DIP switch})}
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\item \textbf<3>{4 pulsadores}
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\item \textbf<4>{Display de 7 segmentos cuádruple}
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\item \textbf<5>{Puerto serie}
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\end{itemize}
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}
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%\vspace{3cm}
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\begin{center}
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\includegraphics<1>[width=1\textwidth]{phr_top_leds.png}
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\includegraphics<2>[width=1\textwidth]{phr_top_switches.png}
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\includegraphics<3>[width=1\textwidth]{phr_top_botones.png}
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\includegraphics<4>[width=1\textwidth]{phr_top_display.png}
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\includegraphics<5>[width=1\textwidth]{phr_top_nada.png}
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\includegraphics<6>[width=1\textwidth]{phr_top.png}
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\end{center}
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\vspace{1ex}
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\end{frame}
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%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
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\section{Placa S3Power}
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%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
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%
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\begin{frame}
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\frametitle{Placa S3Power}
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\begin{center}
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\includegraphics[width=0.8\textwidth]{s3power_small.png}
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\end{center}
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\end{frame}
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%
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\begin{frame}
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\frametitle{Desarrollo del INTI}
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\begin{center}
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\includegraphics[width=0.6\textwidth]{s3power_inti.png}
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Christian Huy y Diego Brengi
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\emph{Instituto Nacional de Tecnología Industrial}
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\end{center}
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\end{frame}
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\subsection{Requerimientos de alimentación de la FPGA} %%%%%%%%%%%%%%%%
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%
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\begin{frame}
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\frametitle{Voltajes de alimentación}
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\begin{center}
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\begin{tabular}{|c|p{4.5cm}|p{3cm}|}
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\hline
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\textbf{Entrada} & \textbf{Alimienta a} & \textbf{Tensión nominal} \\ \hline
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\hline
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VCCINT & Núcleo interno (CLBs, bloques de RAM). & 1.2V \\ \hline
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VCCAUX & DCMs, drivers diferenciales, pines de configuración dedicados y la interfaz JTAG. & 2.5V o 3.3V \\ \hline
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VCCO0 & Banco de E/S número 0. & 3.3V, 3.0V, 2.5V, 1.8V, 1.5V y 1.2V. \\ \hline
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VCCO1 & Banco de E/S número 1. & 3.3V, 3.0V, 2.5V, 1.8V, 1.5V y 1.2V. \\ \hline
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VCCO2 & Banco de E/S número 2. & 3.3V, 3.0V, 2.5V, 1.8V, 1.5V y 1.2V. \\ \hline
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VCCO3 & Banco de E/S número 3. & 3.3V, 3.0V, 2.5V, 1.8V, 1.5V y 1.2V. \\ \hline
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\end{tabular}
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\end{center}
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\end{frame}
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%
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\begin{frame}
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\frametitle{Circuito POR}
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El circuito \emph{Power On RESET} verifica:
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\begin{itemize}
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\item VCCINT
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\item VCCAUX
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\item VCCO2
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\end{itemize}
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\pause
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Tiempos de encendido:
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\begin{center}
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\begin{tabular}{|c|l|c|c|}
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\hline
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\textbf{Símbolo} & \textbf{Rampa de} & \textbf{Min} & \textbf{Max} \\ \hline
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\hline
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VCCINTR & VCCINT & 0.2 ms & 100 ms \\ \hline
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VCCAUXR & VCCAUX & 0.2 ms & 100 ms \\ \hline
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VCCO2R & VCCO del Banco 2 & 0.2 ms & 100 ms \\ \hline
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\end{tabular}
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\end{center}
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\end{frame}
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\subsection{S3Power} %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
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\begin{frame}
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\frametitle{Voltajes elegidos}
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\begin{itemize}
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\item 1.2V y 2.5A para la lógica interna.
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\item 3.3V y 2.5A para los bancos de pines.
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\item 2.5V y 200mA para el módulo de comunicación JTAG.
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\end{itemize}
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\end{frame}
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\begin{frame}
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\frametitle{El chip TPS75003}
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\begin{itemize}
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\item<1-> Posee tres reguladores de tensión: Dos tipo Buck de 3A y eficiencia del 95\% y otro regulador lineal de 300 mA.
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\item<2-> Voltaje de entrada de entre 2.2V y 6.5 V.
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\item<3-> Arranque suave e independiente para cada regulador.
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\item<4-> Tensiones ajustables de 1.2 V a 6.5 V para los convertidores Buck y de 1.0 V a 6.5 V para el convertidor lineal.
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\end{itemize}
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\end{frame}
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\begin{frame}
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\frametitle{Arranque}
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\begin{center}
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\includegraphics[width=0.9\textwidth]{arranque.pdf}
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\end{center}
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\end{frame}
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%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
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\section{Placa OOCDLink}
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%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
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\begin{frame}
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\frametitle{Placa OOCDLink}
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\begin{center}
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\includegraphics[width=0.8\textwidth]{oocdlink_small.png}
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\end{center}
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\end{frame}
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\subsection{FTDI chip} %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
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\begin{frame}
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\frametitle{El chip FT2232D}
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\begin{itemize}
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\item <1->Cumple con USB 2.0 Full Speed (12 Mbits/sec)
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\item <2->Tiene una tasa de transferencia de entre 300 y 3 MBaud
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\item <3->Forma dos canales de comunicación
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\item <4->Desde el SO, la interfaz puede verse como un \emph{puerto serie virtual}
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\item <5->Existen librerías para implementar JTAG, I2C y SPI
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\end{itemize}
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\end{frame}
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\begin{frame}
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\frametitle{El chip FT2232D}
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\begin{center}
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\includegraphics[width=1\textwidth]{FTblock.pdf}
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\end{center}
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\end{frame}
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%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
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\section{Configuración de la FPGA}
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%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
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\begin{frame}
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\frametitle{Modos de configuración (familia Spartan-3A)}
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\begin{itemize}
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\item \textbf<2>{\textsl{Master Serial} desde una memoria PROM Flash de Xilinx}
|
| 319 |
|
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\item \textsl{Serial Peripheral Interface} (SPI) desde una memoria Flash SPI
|
| 320 |
|
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\item \textsl{Byte Peripheral Interface} (BPI) desde una memoria NOR Flash
|
| 321 |
|
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\item \textsl{Slave Serial}, típicamente cargada desde un procesador
|
| 322 |
|
|
\item \textsl{Slave Parallel}, típicamente cargada desde un procesador
|
| 323 |
|
|
\item \textbf<2>{\textsl{Boundary Scan} (JTAG), típicamente cargada desde un procesador}
|
| 324 |
|
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\end{itemize}
|
| 325 |
|
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\end{frame}
|
| 326 |
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|
| 327 |
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|
|
| 328 |
|
|
\begin{frame}
|
| 329 |
|
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\frametitle{Selección de los modos de configuración}
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| 330 |
|
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\includegraphics[width=1\textwidth]{config_modes.pdf}
|
| 331 |
|
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\end{frame}
|
| 332 |
|
|
|
| 333 |
|
|
\begin{frame}
|
| 334 |
|
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\frametitle{Circuito de configuración}
|
| 335 |
|
|
\includegraphics[width=1\textwidth]{conf_mod_sche.pdf}
|
| 336 |
|
|
\end{frame}
|
| 337 |
|
|
|
| 338 |
|
|
|
| 339 |
282 |
maximiq |
\subsection{Software} %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
|
| 340 |
277 |
maximiq |
|
| 341 |
|
|
\begin{frame}
|
| 342 |
|
|
\frametitle{xc3sprog}
|
| 343 |
|
|
\begin{center}
|
| 344 |
279 |
maximiq |
\includegraphics[width=1\textwidth]{xc3sprog.pdf}
|
| 345 |
277 |
maximiq |
\end{center}
|
| 346 |
|
|
\end{frame}
|
| 347 |
|
|
|
| 348 |
|
|
\begin{frame}
|
| 349 |
|
|
\frametitle{xc3sprog}
|
| 350 |
|
|
\begin{center}
|
| 351 |
|
|
\includegraphics[width=0.8\textwidth]{front-end.pdf}
|
| 352 |
|
|
\end{center}
|
| 353 |
|
|
\end{frame}
|
| 354 |
|
|
|
| 355 |
279 |
maximiq |
\begin{frame}
|
| 356 |
|
|
\frametitle{PHR GUI}
|
| 357 |
277 |
maximiq |
\begin{center}
|
| 358 |
|
|
\includegraphics[width=0.8\textwidth]{phr-gui.png}
|
| 359 |
|
|
\end{center}
|
| 360 |
|
|
\end{frame}
|
| 361 |
|
|
|
| 362 |
|
|
\appendix
|
| 363 |
|
|
|
| 364 |
282 |
maximiq |
%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
|
| 365 |
277 |
maximiq |
\section*{Terminando}
|
| 366 |
282 |
maximiq |
%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
|
| 367 |
|
|
|
| 368 |
|
|
\subsection{Comunidad}
|
| 369 |
|
|
|
| 370 |
277 |
maximiq |
\begin{frame}
|
| 371 |
282 |
maximiq |
\frametitle{Comunidad de hardware abierto}
|
| 372 |
279 |
maximiq |
\begin{center}
|
| 373 |
282 |
maximiq |
\includegraphics[width=0.6\textwidth]{oc.jpg}
|
| 374 |
279 |
maximiq |
\end{center}
|
| 375 |
277 |
maximiq |
\end{frame}
|
| 376 |
|
|
|
| 377 |
279 |
maximiq |
\begin{frame}
|
| 378 |
282 |
maximiq |
\frametitle{Otros proyectos Open Hardware}
|
| 379 |
|
|
\begin{itemize}
|
| 380 |
|
|
\item <1-2>OpenRISC
|
| 381 |
|
|
\item <2-2>LEON
|
| 382 |
|
|
\item <3>Arduino
|
| 383 |
|
|
\item <4>CUBEBUG-1
|
| 384 |
|
|
\end{itemize}
|
| 385 |
279 |
maximiq |
\begin{center}
|
| 386 |
282 |
maximiq |
\includegraphics<3>[width=1\textwidth]{ohwp_arduino.jpg}
|
| 387 |
|
|
\includegraphics<4>[width=1\textwidth]{ohwp_cubeBug1.jpg}
|
| 388 |
279 |
maximiq |
\end{center}
|
| 389 |
|
|
\end{frame}
|
| 390 |
277 |
maximiq |
|
| 391 |
282 |
maximiq |
|
| 392 |
|
|
\subsection{Sitio web del proyecto}
|
| 393 |
|
|
|
| 394 |
279 |
maximiq |
\begin{frame}
|
| 395 |
282 |
maximiq |
\begin{center}
|
| 396 |
|
|
\includegraphics[width=1\textwidth]{opencores.png}
|
| 397 |
|
|
\end{center}
|
| 398 |
|
|
\end{frame}
|
| 399 |
|
|
|
| 400 |
|
|
\subsection{Fin}
|
| 401 |
|
|
|
| 402 |
|
|
\begin{frame}
|
| 403 |
279 |
maximiq |
\frametitle{¿Preguntas?}
|
| 404 |
|
|
\begin{center}
|
| 405 |
|
|
\includegraphics[height=0.9\textheight]{question_.pdf}
|
| 406 |
|
|
\end{center}
|
| 407 |
|
|
\end{frame}
|
| 408 |
|
|
|
| 409 |
|
|
|
| 410 |
277 |
maximiq |
\end{document}
|
