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%\documentclass[handout]{beamer}
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\usepackage{multirow}
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%\setbeamertemplate{navigation symbols}{} % borra los controles de navegación
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%\beamersetuncovermixins{\opaqueness<1>{25}}{\opaqueness<2->{15}}
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\title{Plataforma de Hardware Reconfigurable para el Diseño de Sistemas Digitales}
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\author{Luis Guanuco, Sergio Olmedo, Maximiliano Quinteros}
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\date[uEA2014]{V Congreso de Microelectrónica Aplicada\\14 de Mayo, 2014}
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\institute{Centro Universitario de Desarrollo en Automoción y Robótica\\Universidad Tecnológica Nacional, Facultad Regional Córdoba}
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% \logo{%
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% \includegraphics[width=0.1\paperwidth,keepaspectratio]{CUDARlogo}%
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% \hspace{\dimexpr\paperwidth-2cm-5pt}%
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% \includegraphics[width=0.05\paperwidth,keepaspectratio]{UTNlogo}%
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%}
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% logo of my university
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% \titlegraphic{\includegraphics[width=2cm]{logopolito}\hspace*{4.75cm}~%
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% }
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%\titlegraphic{\includegraphics[width=5.5cm]{phr_small.png}}
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\titlegraphic{
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\includegraphics[width=0.2\textwidth]{CUDARlogo}\hspace{0.22\textwidth}
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\includegraphics[width=0.12\textwidth]{uEA14-logo}\hspace{0.32\textwidth}
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\includegraphics[width=0.1\textwidth]{UTNlogo}
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}
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\AtBeginSection[]{
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\begin{frame}
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\frametitle{Contenidos}
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\tableofcontents[currentsection,hideallsubsections]
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}
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\begin{document}
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\begin{frame}
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\titlepage
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\end{frame}
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\begin{frame}
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\frametitle{Contenidos}
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\tableofcontents[hideallsubsections]
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\end{frame}
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%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
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\section{Introducción}
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%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
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\begin{frame}
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\frametitle{Una breve introducción}
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\begin{center}
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\includegraphics[width=0.6\textwidth]{prof.pdf}
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\end{center}
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\end{frame}
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\begin{frame}
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\frametitle{Contexto del desarrollo y oportunidades}
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% \transfade
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\begin{center}
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\begin{itemize}
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\item Necesidad de recursos educativos (HW \& SW)
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\begin{description}
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\item [Nuevas tecnologías:] Adquirir plataformas comerciales
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\item [Desarrollos a medida:] Diseño de plataformas locales
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\end{description}
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\pause{}
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\vfill{}
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\item Experiencia en Ingeniería Electrónica
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\begin{description}
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\item [Desarrollo de HW:] Plataforma educativa basada en CPLD
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\item [Creación de Cátedra Electiva:] Técnicas Digitales IV
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\end{description}
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\pause{}
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\vfill{}
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\item Oportunidades
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\begin{itemize}
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\item Desarrollo de recursos de HW con herramientas de \emph{Software Libre}
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\item Articulación de laboratorio, centros I+D e industria para el desarrollo de recursos de HW locales
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\end{itemize}
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\end{itemize}
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\end{center}
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\end{frame}
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\begin{frame}
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\frametitle{Características comunes de las plataformas}
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% \transfade
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\begin{center}
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\begin{itemize}
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\item El dispositivo lógico programable central es una FPGA
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\vfill
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\item Poseen Memoria de configuración de la FPGA
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\vfill
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\item El acceso al dispositivo es a través de JTAG
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\vfill
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\item Disponen de algún software para interactuar con la plataforma desde una computadora
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\vfill
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\item Tienen dos perfiles de diseño:
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\begin{itemize}
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\item Para la implementación de sistemas lógicos generales
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\item Orientado a un área específica
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\end{itemize}
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\end{itemize}
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\end{center}
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\end{frame}
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\begin{frame}
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\frametitle{Recursos de hardware vs. Nivel de enseñanza}
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% \transfade
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\begin{block}{Consideración}
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En función del perfil del usuario de la plataforma se definen los dispositivos que se utilizarán
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\end{block}
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\vfill
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\begin{center}
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\begin{tabular}{|l|c|c|c|}
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\hline
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\multirow{2}{*}{Nivel} & Llaves/pulsadores & ADC\&DAC/SPI & USB/ETH \\
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& Diodos LED & Display LCD/VGA & HDMI \\ \hline
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\hline
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Inicial & $\checkmark$ & & \\
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\hline
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Medio & $\checkmark$ & $\checkmark$ & \\
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\hline
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Avanzado & $\checkmark$ & $\checkmark$ & $\checkmark$ \\
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\hline
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\end{tabular}
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% \includegraphics[width=0.2\textwidth]{BASYS2-top-400}%
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% \hfil
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% \includegraphics[width=0.2\textwidth]{de0-nano}%
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% \hfil
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% \includegraphics[width=0.2\textwidth]{Avnet-Spartan-6-lx9-MicroBoard}%
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\end{center}
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\end{frame}
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\begin{frame}
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\frametitle{Plataformas comerciales}
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% \transfade
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\begin{columns}[onlytextwidth]
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\begin{column}{0.4\textwidth}
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\centering
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\vfill
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\includegraphics<1>[width=0.5\textwidth]{digilent}%
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\hfill
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\includegraphics<1>[width=\textwidth]{BASYS2-top-400}%
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\vfill
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\includegraphics<2>[width=0.5\textwidth]{altera-logo}%
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\hfill
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\includegraphics<2>[width=\textwidth]{de0-nano}%
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\vfill
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\includegraphics<3>[width=0.5\textwidth]{avnetlogo}%
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\hfill
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\includegraphics<3>[width=\textwidth]{Avnet-Spartan-6-lx9-MicroBoard}%
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\vfill
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\end{column}
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\begin{column}{0.55\textwidth}
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\only<1>{
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\begin{itemize}
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\item Xilinx Spartan 3-E FPGA, 100K gates
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\item Multiplicadores, RAM y 500MHz+
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\item Puerto USB 2 full-speed (configuración y transferencia)
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\item Memoria de Configuración Flash PROM XCF02
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\item 8 LEDs, display 7-seg de 4-dig, 4 pulsadores, 8 llaves, puerto PS/2 y VGA
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\end{itemize}
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}
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\only<2>{
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\begin{itemize}
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\item Cyclone IV EP4CE22F17C6N, 22,320 LEs
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\item Multiplicadores, RAM y 4 PLLs
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\item Memoria de configuración EPCS16, SDRAM 32MB, EEPROM 2Kb (I2C)
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\item 8 LEDs, 2 pulsadores,
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\item Sensores: Acelerómetro de 3 ejes ADI ADXL345, ADC ADC128S022 de 12-bits/8-canales
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\item Alimentación: USB (5 V), cable DC 5-V
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\end{itemize}
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}
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\only<3>{
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\begin{itemize}
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\item Spartan-6 XC6SLX9-2CSG324C FPGA
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\item Memoria de configuración SPI flash 128Mb, SDRAM 64MB
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\item 10/100 Ethernet PHY
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\item Sistema de alimentación (3-rail) con indicador de estado
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\item 4 LEDs, llave DIP 4-bit
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\end{itemize}
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}
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\end{column}
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\end{columns}
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\end{frame}
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\begin{frame}
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\frametitle{Recursos básicos de las plataformas}
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\begin{center}
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\begin{itemize}
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\item FPGA
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\item Memoria de configuración de la FPGA
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\item Periféricos básicos (LEDs, display, pulsadores, llaves, etc.)
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\item Puerto USB
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\item Puerto para módulos externos
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\item Puerto para propósitos generales
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\item Varias señales de reloj (clock)
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\item VGA
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\item PS/2
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\item Memorias ROM/RAM
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\item ADC/DAC
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\end{itemize}
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\end{center}
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\end{frame}
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\begin{frame}
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\frametitle{Estado del arte de las FPGA en Argentina}
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\begin{center}
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\begin{block}{}
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En nuestra región las tecnologías PLD se encuentran integradas en varias líneas de investigación y desarrollos hace algunos años. Instituciones gubernamentales de defensa, aeroespaciales, comunicaciones están implementando dispositivos como FPGAs y CPLDs en sus sistemas electrónicos. Además existe una constante actualización por parte de las instituciones académicas en los programas analíticos de las carreras relacionadas a los sistemas embebidos.
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\end{block}
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\end{center}
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\end{frame}
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\begin{frame}
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\frametitle{Kit de Desarrollo educativo con CPLD}
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\begin{center}
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\includegraphics<1>[width=0.9\textwidth]{block1cpld}
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\includegraphics<2>[width=0.9\textwidth]{block2cpld}
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\end{center}
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\end{frame}
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\begin{frame}
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\frametitle{Kit de Desarrollo educativo con CPLD}
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\begin{center}
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\includegraphics[height=0.5\textheight]{kit_cpld_per.png} \hspace{1ex}
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\includegraphics[height=0.4\textheight]{kit_cpld.png}
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\end{center}
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\end{frame}
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\begin{frame}
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\frametitle{FPGALibre.sourceforge.net}
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\begin{center}
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\includegraphics[width=\textwidth]{fpgalibreweb}
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\end{center}
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\end{frame}
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\begin{frame}
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\frametitle{S3PROTO}
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\begin{center}
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\includegraphics[width=\textwidth]{fpgalibreweb}
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\end{center}
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\end{frame}
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\begin{frame}
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\frametitle{Plataforma de Hardware Reconfigurable}
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\begin{center}
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\includegraphics[width=1\textwidth]{phr_small.png}
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\end{center}
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\end{frame}
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\begin{frame}
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\frametitle{Hardware libre}
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\begin{center}
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\includegraphics[width=0.9\textwidth]{Ohw-logo.pdf}
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\end{center}
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\end{frame}
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\section[Diagrama de bloques]{Diagrama de bloques del Hardware}
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\begin{frame}
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\frametitle{Diagrama de bloques del Hardware}
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%\transfade
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\begin{center}
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\includegraphics<1>[width=0.9\textwidth]{block1.pdf}
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\includegraphics<2>[width=0.9\textwidth]{block2.pdf}
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\includegraphics<3>[width=0.9\textwidth]{block3.pdf}
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\end{center}
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\end{frame}
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%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
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\section{Placa PHR}
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%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
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\begin{frame}
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\frametitle{Placa PHR}
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\begin{center}
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\includegraphics[width=\textwidth]{phr_text.png}
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\end{center}
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\end{frame}
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\subsection{Características} %%%%%%%%%%%%%%%%%%%%%%%%%%%
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\begin{frame}
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\frametitle{Características}
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\begin{description}[Memoria PROM:]
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guanucolui |
\item [FPGA:] Xilinx Spartan-3A XC3S200A (VQG100)
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| 321 |
277 |
maximiq |
\pause
|
| 322 |
291 |
guanucolui |
\item [Memoria PROM:] Xilinx XCF02S
|
| 323 |
277 |
maximiq |
\pause
|
| 324 |
291 |
guanucolui |
\item [Voltaje entrada:] 5V
|
| 325 |
277 |
maximiq |
\pause
|
| 326 |
|
|
\item [Relojes:] Un reloj fijo y tres seleccionables:
|
| 327 |
|
|
|
| 328 |
|
|
\begin{enumerate}
|
| 329 |
291 |
guanucolui |
\item 50 MHz
|
| 330 |
|
|
\item 16 MHz, 1 MHz, 500 kHz y 250 kHz
|
| 331 |
|
|
\item 125 kHz, 62.5 kHz, 31.25 kHz, 15.625 kHz
|
| 332 |
|
|
\item 3.9062 kHz, 1.9531 kHz, 976,56251 Hz
|
| 333 |
277 |
maximiq |
\end{enumerate}
|
| 334 |
|
|
\pause
|
| 335 |
291 |
guanucolui |
\item [GPIO:] 28 pines en total
|
| 336 |
277 |
maximiq |
\end{description}
|
| 337 |
|
|
|
| 338 |
|
|
\end{frame}
|
| 339 |
|
|
|
| 340 |
282 |
maximiq |
\begin{frame}
|
| 341 |
|
|
\frametitle{El chip FPGA (XC3S200A)}
|
| 342 |
|
|
\begin{description}[E/S pares diferenciales máximo:]
|
| 343 |
|
|
\item [Número de compuertas:] 200K
|
| 344 |
|
|
\item [Celdas lógicas equivalentes:] 4032
|
| 345 |
|
|
\item [CLBs:] 448
|
| 346 |
|
|
\item [Bits de RAM distribuida:] 28K
|
| 347 |
|
|
\item [Bits de Bloques de RAM:] 288K
|
| 348 |
|
|
\item [Multiplicadores dedicados:] 16
|
| 349 |
|
|
\item [DCMs:] 4
|
| 350 |
|
|
\item [Máximo número de E/S:] 248
|
| 351 |
|
|
\item [E/S pares diferenciales máximo:] 112
|
| 352 |
|
|
\end{description}
|
| 353 |
|
|
\end{frame}
|
| 354 |
|
|
|
| 355 |
|
|
|
| 356 |
277 |
maximiq |
\begin{frame}[b]
|
| 357 |
|
|
\frametitle{Periféricos}
|
| 358 |
|
|
\only<1-5>{
|
| 359 |
|
|
\begin{itemize}
|
| 360 |
|
|
\item \textbf<1>{8 LEDs}
|
| 361 |
282 |
maximiq |
\item \textbf<2>{8 llaves (\emph{DIP switch})}
|
| 362 |
277 |
maximiq |
\item \textbf<3>{4 pulsadores}
|
| 363 |
|
|
\item \textbf<4>{Display de 7 segmentos cuádruple}
|
| 364 |
|
|
\item \textbf<5>{Puerto serie}
|
| 365 |
|
|
\end{itemize}
|
| 366 |
|
|
}
|
| 367 |
|
|
|
| 368 |
|
|
%\vspace{3cm}
|
| 369 |
|
|
\begin{center}
|
| 370 |
|
|
\includegraphics<1>[width=1\textwidth]{phr_top_leds.png}
|
| 371 |
|
|
\includegraphics<2>[width=1\textwidth]{phr_top_switches.png}
|
| 372 |
|
|
\includegraphics<3>[width=1\textwidth]{phr_top_botones.png}
|
| 373 |
|
|
\includegraphics<4>[width=1\textwidth]{phr_top_display.png}
|
| 374 |
|
|
\includegraphics<5>[width=1\textwidth]{phr_top_nada.png}
|
| 375 |
|
|
\includegraphics<6>[width=1\textwidth]{phr_top.png}
|
| 376 |
|
|
\end{center}
|
| 377 |
|
|
|
| 378 |
|
|
\vspace{1ex}
|
| 379 |
|
|
|
| 380 |
|
|
\end{frame}
|
| 381 |
|
|
|
| 382 |
282 |
maximiq |
%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
|
| 383 |
|
|
\section{Placa S3Power}
|
| 384 |
|
|
%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
|
| 385 |
277 |
maximiq |
|
| 386 |
282 |
maximiq |
%
|
| 387 |
277 |
maximiq |
\begin{frame}
|
| 388 |
|
|
\frametitle{Placa S3Power}
|
| 389 |
|
|
\begin{center}
|
| 390 |
|
|
\includegraphics[width=0.8\textwidth]{s3power_small.png}
|
| 391 |
|
|
\end{center}
|
| 392 |
|
|
\end{frame}
|
| 393 |
|
|
|
| 394 |
282 |
maximiq |
%
|
| 395 |
277 |
maximiq |
\begin{frame}
|
| 396 |
282 |
maximiq |
\frametitle{Desarrollo del INTI}
|
| 397 |
279 |
maximiq |
\begin{center}
|
| 398 |
|
|
\includegraphics[width=0.6\textwidth]{s3power_inti.png}
|
| 399 |
|
|
|
| 400 |
|
|
Christian Huy y Diego Brengi
|
| 401 |
|
|
|
| 402 |
282 |
maximiq |
\emph{Instituto Nacional de Tecnología Industrial}
|
| 403 |
279 |
maximiq |
\end{center}
|
| 404 |
277 |
maximiq |
\end{frame}
|
| 405 |
|
|
|
| 406 |
282 |
maximiq |
\subsection{Requerimientos de alimentación de la FPGA} %%%%%%%%%%%%%%%%
|
| 407 |
|
|
|
| 408 |
|
|
%
|
| 409 |
277 |
maximiq |
\begin{frame}
|
| 410 |
|
|
\frametitle{Voltajes de alimentación}
|
| 411 |
|
|
\begin{center}
|
| 412 |
|
|
\begin{tabular}{|c|p{4.5cm}|p{3cm}|}
|
| 413 |
|
|
\hline
|
| 414 |
|
|
\textbf{Entrada} & \textbf{Alimienta a} & \textbf{Tensión nominal} \\ \hline
|
| 415 |
|
|
\hline
|
| 416 |
291 |
guanucolui |
VCCINT & Núcleo interno (CLBs, bloques de RAM) & 1.2V \\ \hline
|
| 417 |
|
|
VCCAUX & DCMs, drivers diferenciales, pines de configuración dedicados y la interfaz JTAG & 2.5V o 3.3V \\ \hline
|
| 418 |
|
|
VCCO0 & Banco de E/S número 0 & 3.3V, 3.0V, 2.5V, 1.8V, 1.5V y 1.2V \\ \hline
|
| 419 |
|
|
VCCO1 & Banco de E/S número 1 & 3.3V, 3.0V, 2.5V, 1.8V, 1.5V y 1.2V \\ \hline
|
| 420 |
|
|
VCCO2 & Banco de E/S número 2 & 3.3V, 3.0V, 2.5V, 1.8V, 1.5V y 1.2V \\ \hline
|
| 421 |
|
|
VCCO3 & Banco de E/S número 3 & 3.3V, 3.0V, 2.5V, 1.8V, 1.5V y 1.2V \\ \hline
|
| 422 |
277 |
maximiq |
\end{tabular}
|
| 423 |
|
|
\end{center}
|
| 424 |
|
|
\end{frame}
|
| 425 |
|
|
|
| 426 |
282 |
maximiq |
%
|
| 427 |
277 |
maximiq |
\begin{frame}
|
| 428 |
|
|
\frametitle{Circuito POR}
|
| 429 |
|
|
El circuito \emph{Power On RESET} verifica:
|
| 430 |
|
|
\begin{itemize}
|
| 431 |
|
|
\item VCCINT
|
| 432 |
|
|
\item VCCAUX
|
| 433 |
|
|
\item VCCO2
|
| 434 |
|
|
\end{itemize}
|
| 435 |
|
|
\pause
|
| 436 |
|
|
Tiempos de encendido:
|
| 437 |
|
|
\begin{center}
|
| 438 |
|
|
\begin{tabular}{|c|l|c|c|}
|
| 439 |
|
|
\hline
|
| 440 |
|
|
\textbf{Símbolo} & \textbf{Rampa de} & \textbf{Min} & \textbf{Max} \\ \hline
|
| 441 |
|
|
\hline
|
| 442 |
|
|
VCCINTR & VCCINT & 0.2 ms & 100 ms \\ \hline
|
| 443 |
|
|
VCCAUXR & VCCAUX & 0.2 ms & 100 ms \\ \hline
|
| 444 |
|
|
VCCO2R & VCCO del Banco 2 & 0.2 ms & 100 ms \\ \hline
|
| 445 |
|
|
\end{tabular}
|
| 446 |
|
|
\end{center}
|
| 447 |
|
|
\end{frame}
|
| 448 |
|
|
|
| 449 |
|
|
|
| 450 |
282 |
maximiq |
\subsection{S3Power} %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
|
| 451 |
277 |
maximiq |
|
| 452 |
|
|
\begin{frame}
|
| 453 |
|
|
\frametitle{Voltajes elegidos}
|
| 454 |
|
|
\begin{itemize}
|
| 455 |
|
|
\item 1.2V y 2.5A para la lógica interna.
|
| 456 |
|
|
\item 3.3V y 2.5A para los bancos de pines.
|
| 457 |
|
|
\item 2.5V y 200mA para el módulo de comunicación JTAG.
|
| 458 |
|
|
\end{itemize}
|
| 459 |
|
|
\end{frame}
|
| 460 |
|
|
|
| 461 |
|
|
\begin{frame}
|
| 462 |
|
|
\frametitle{El chip TPS75003}
|
| 463 |
|
|
\begin{itemize}
|
| 464 |
|
|
\item<1-> Posee tres reguladores de tensión: Dos tipo Buck de 3A y eficiencia del 95\% y otro regulador lineal de 300 mA.
|
| 465 |
|
|
\item<2-> Voltaje de entrada de entre 2.2V y 6.5 V.
|
| 466 |
|
|
\item<3-> Arranque suave e independiente para cada regulador.
|
| 467 |
|
|
\item<4-> Tensiones ajustables de 1.2 V a 6.5 V para los convertidores Buck y de 1.0 V a 6.5 V para el convertidor lineal.
|
| 468 |
|
|
\end{itemize}
|
| 469 |
|
|
\end{frame}
|
| 470 |
|
|
|
| 471 |
|
|
\begin{frame}
|
| 472 |
282 |
maximiq |
\frametitle{Arranque}
|
| 473 |
277 |
maximiq |
\begin{center}
|
| 474 |
|
|
\includegraphics[width=0.9\textwidth]{arranque.pdf}
|
| 475 |
|
|
\end{center}
|
| 476 |
|
|
\end{frame}
|
| 477 |
|
|
|
| 478 |
|
|
|
| 479 |
282 |
maximiq |
%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
|
| 480 |
277 |
maximiq |
\section{Placa OOCDLink}
|
| 481 |
282 |
maximiq |
%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
|
| 482 |
|
|
|
| 483 |
277 |
maximiq |
\begin{frame}
|
| 484 |
|
|
\frametitle{Placa OOCDLink}
|
| 485 |
|
|
\begin{center}
|
| 486 |
|
|
\includegraphics[width=0.8\textwidth]{oocdlink_small.png}
|
| 487 |
|
|
\end{center}
|
| 488 |
|
|
\end{frame}
|
| 489 |
|
|
|
| 490 |
282 |
maximiq |
\subsection{FTDI chip} %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
|
| 491 |
|
|
|
| 492 |
277 |
maximiq |
\begin{frame}
|
| 493 |
282 |
maximiq |
\frametitle{El chip FT2232D}
|
| 494 |
|
|
\begin{itemize}
|
| 495 |
|
|
\item <1->Cumple con USB 2.0 Full Speed (12 Mbits/sec)
|
| 496 |
|
|
\item <2->Tiene una tasa de transferencia de entre 300 y 3 MBaud
|
| 497 |
|
|
\item <3->Forma dos canales de comunicación
|
| 498 |
|
|
\item <4->Desde el SO, la interfaz puede verse como un \emph{puerto serie virtual}
|
| 499 |
|
|
\item <5->Existen librerías para implementar JTAG, I2C y SPI
|
| 500 |
|
|
\end{itemize}
|
| 501 |
|
|
\end{frame}
|
| 502 |
|
|
|
| 503 |
|
|
\begin{frame}
|
| 504 |
|
|
\frametitle{El chip FT2232D}
|
| 505 |
277 |
maximiq |
\begin{center}
|
| 506 |
|
|
\includegraphics[width=1\textwidth]{FTblock.pdf}
|
| 507 |
|
|
\end{center}
|
| 508 |
|
|
\end{frame}
|
| 509 |
|
|
|
| 510 |
282 |
maximiq |
|
| 511 |
|
|
%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
|
| 512 |
277 |
maximiq |
\section{Configuración de la FPGA}
|
| 513 |
282 |
maximiq |
%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
|
| 514 |
|
|
|
| 515 |
277 |
maximiq |
\begin{frame}
|
| 516 |
|
|
\frametitle{Modos de configuración (familia Spartan-3A)}
|
| 517 |
|
|
\begin{itemize}
|
| 518 |
|
|
\item \textbf<2>{\textsl{Master Serial} desde una memoria PROM Flash de Xilinx}
|
| 519 |
|
|
\item \textsl{Serial Peripheral Interface} (SPI) desde una memoria Flash SPI
|
| 520 |
|
|
\item \textsl{Byte Peripheral Interface} (BPI) desde una memoria NOR Flash
|
| 521 |
|
|
\item \textsl{Slave Serial}, típicamente cargada desde un procesador
|
| 522 |
|
|
\item \textsl{Slave Parallel}, típicamente cargada desde un procesador
|
| 523 |
|
|
\item \textbf<2>{\textsl{Boundary Scan} (JTAG), típicamente cargada desde un procesador}
|
| 524 |
|
|
\end{itemize}
|
| 525 |
|
|
\end{frame}
|
| 526 |
|
|
|
| 527 |
|
|
|
| 528 |
|
|
\begin{frame}
|
| 529 |
|
|
\frametitle{Selección de los modos de configuración}
|
| 530 |
|
|
\includegraphics[width=1\textwidth]{config_modes.pdf}
|
| 531 |
|
|
\end{frame}
|
| 532 |
|
|
|
| 533 |
|
|
\begin{frame}
|
| 534 |
|
|
\frametitle{Circuito de configuración}
|
| 535 |
|
|
\includegraphics[width=1\textwidth]{conf_mod_sche.pdf}
|
| 536 |
|
|
\end{frame}
|
| 537 |
|
|
|
| 538 |
|
|
|
| 539 |
282 |
maximiq |
\subsection{Software} %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
|
| 540 |
277 |
maximiq |
|
| 541 |
|
|
\begin{frame}
|
| 542 |
|
|
\frametitle{xc3sprog}
|
| 543 |
|
|
\begin{center}
|
| 544 |
279 |
maximiq |
\includegraphics[width=1\textwidth]{xc3sprog.pdf}
|
| 545 |
277 |
maximiq |
\end{center}
|
| 546 |
|
|
\end{frame}
|
| 547 |
|
|
|
| 548 |
|
|
\begin{frame}
|
| 549 |
|
|
\frametitle{xc3sprog}
|
| 550 |
|
|
\begin{center}
|
| 551 |
|
|
\includegraphics[width=0.8\textwidth]{front-end.pdf}
|
| 552 |
|
|
\end{center}
|
| 553 |
|
|
\end{frame}
|
| 554 |
|
|
|
| 555 |
279 |
maximiq |
\begin{frame}
|
| 556 |
|
|
\frametitle{PHR GUI}
|
| 557 |
277 |
maximiq |
\begin{center}
|
| 558 |
|
|
\includegraphics[width=0.8\textwidth]{phr-gui.png}
|
| 559 |
|
|
\end{center}
|
| 560 |
|
|
\end{frame}
|
| 561 |
|
|
|
| 562 |
|
|
\appendix
|
| 563 |
|
|
|
| 564 |
282 |
maximiq |
%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
|
| 565 |
277 |
maximiq |
\section*{Terminando}
|
| 566 |
282 |
maximiq |
%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
|
| 567 |
|
|
|
| 568 |
|
|
\subsection{Comunidad}
|
| 569 |
|
|
|
| 570 |
277 |
maximiq |
\begin{frame}
|
| 571 |
282 |
maximiq |
\frametitle{Comunidad de hardware abierto}
|
| 572 |
279 |
maximiq |
\begin{center}
|
| 573 |
282 |
maximiq |
\includegraphics[width=0.6\textwidth]{oc.jpg}
|
| 574 |
279 |
maximiq |
\end{center}
|
| 575 |
277 |
maximiq |
\end{frame}
|
| 576 |
|
|
|
| 577 |
279 |
maximiq |
\begin{frame}
|
| 578 |
282 |
maximiq |
\frametitle{Otros proyectos Open Hardware}
|
| 579 |
|
|
\begin{itemize}
|
| 580 |
|
|
\item <1-2>OpenRISC
|
| 581 |
|
|
\item <2-2>LEON
|
| 582 |
|
|
\item <3>Arduino
|
| 583 |
|
|
\item <4>CUBEBUG-1
|
| 584 |
|
|
\end{itemize}
|
| 585 |
279 |
maximiq |
\begin{center}
|
| 586 |
282 |
maximiq |
\includegraphics<3>[width=1\textwidth]{ohwp_arduino.jpg}
|
| 587 |
|
|
\includegraphics<4>[width=1\textwidth]{ohwp_cubeBug1.jpg}
|
| 588 |
279 |
maximiq |
\end{center}
|
| 589 |
|
|
\end{frame}
|
| 590 |
277 |
maximiq |
|
| 591 |
282 |
maximiq |
|
| 592 |
|
|
\subsection{Sitio web del proyecto}
|
| 593 |
|
|
|
| 594 |
279 |
maximiq |
\begin{frame}
|
| 595 |
282 |
maximiq |
\begin{center}
|
| 596 |
|
|
\includegraphics[width=1\textwidth]{opencores.png}
|
| 597 |
|
|
\end{center}
|
| 598 |
|
|
\end{frame}
|
| 599 |
|
|
|
| 600 |
|
|
\subsection{Fin}
|
| 601 |
|
|
|
| 602 |
|
|
\begin{frame}
|
| 603 |
279 |
maximiq |
\frametitle{¿Preguntas?}
|
| 604 |
|
|
\begin{center}
|
| 605 |
|
|
\includegraphics[height=0.9\textheight]{question_.pdf}
|
| 606 |
|
|
\end{center}
|
| 607 |
|
|
\end{frame}
|
| 608 |
|
|
|
| 609 |
|
|
|
| 610 |
277 |
maximiq |
\end{document}
|
